CN112864807B - Preparation method of buried heterojunction - Google Patents

Preparation method of buried heterojunction Download PDF

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CN112864807B
CN112864807B CN202110451693.6A CN202110451693A CN112864807B CN 112864807 B CN112864807 B CN 112864807B CN 202110451693 A CN202110451693 A CN 202110451693A CN 112864807 B CN112864807 B CN 112864807B
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inp
amorphous semiconductor
semiconductor material
grating
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CN112864807A (en
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李鸿建
郭娟
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Wuhan Yunling Optoelectronics Co ltd
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Wuhan Yunling Photoelectric Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18322—Position of the structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18344—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] characterized by the mesa, e.g. dimensions or shape of the mesa
    • H01S5/18352—Mesa with inclined sidewall

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

The invention relates to a preparation method of a buried heterojunction, which comprises the following steps: s1, manufacturing a grating layer on the surface of the epitaxial layer; s2, growing InP cover layer on the grating layer to fill the grooves on the grating layerObtaining a flat surface; s3, growing a sacrificial layer and an amorphous semiconductor material layer on the InP cover layer to obtain a transition structure; s4, continuing to grow SiO on the transition structure2/SiNxA mask layer is formed, and then the transition structure is etched to form a table-shaped structure; s5, removing SiO after the mesa structure is formed2/SiNxAnd a mask layer, wherein an amorphous semiconductor material layer is taken as the current mask layer to continue to grow a P-InP layer and an N-InP layer on the mesa structure in sequence. The invention removes SiO before growing the limiting layer2/SiNxThe mask layer is removed, the amorphous semiconductor material layer is used as a self-aligned mask, MOCVD current limiting layer growth is carried out, the amorphous epitaxial layers are easy to remove, the function of taking the self-aligned amorphous semiconductor material as the mask is achieved, and the eave structure in the conventional technology is avoided.

Description

Preparation method of buried heterojunction
Technical Field
The invention relates to the technical field of optical communication, in particular to a preparation method of a buried heterojunction.
Background
In the existing buried heterojunction technology, SiO2/SiNx is used as a mask before a limiting layer is buried, a very long eave structure (underslot for short) can be formed on the left and right sides of a final platform by the SiO2/SiNx mask above a mesa-shaped structure, and when a current limiting layer is grown by MOCVD (metal organic chemical vapor deposition), due to the presence of the underslot, a Selective Area Growth (SAG) phenomenon can occur, and finally, high-rise effective current limiting structures cannot be formed on the two sides of the current limiting layer, so that the current injection effect of a laser is poor, and the reliability and high and low temperature performance of the laser are affected finally.
At present, the waveguide structure of the edge-emitting laser can be roughly divided into two types, one is a ridge waveguide type; the other is of the buried waveguide type. Buried waveguide structures are favored by the industry for their superior performance in terms of divergence angle, power and reliability. However, the requirements of the buried structure laser on the manufacturing process are very strict, and especially the current confinement layer structure and the growth quality play a crucial role in the characteristics of the whole device. At present, a common current limiting layer is a P/N/P structure, the manufacturing process is roughly divided into three steps, firstly, a platform-shaped structure is formed in a photoetching and dry-wet etching mode, as shown in figure 1; then, using metal organic chemical vapor deposition equipment (MOCVD) to grow P/N type indium phosphide to form a current limiting layer, as shown in FIG. 3; and finally, removing the SiO2/SiNx mask layer, and growing the P-type indium phosphide cover layer 7 and the contact layer by using Metal Organic Chemical Vapor Deposition (MOCVD). Due to the isotropy of wet etching in the etching process of the table-shaped structure, after the wet etching is finished, the mask above the table-shaped structure can form a long eave structure which is called as undercut for short on the left and the right of a final platform. When a current limiting layer is grown by MOCVD, due to the existence of undercut, a Selective Area Growth (SAG) phenomenon occurs, so that the two sides of the mesa structure cannot form a high-rise effective current limiting layer, the current injection effect of the laser is poor, and the reliability and the normal-high temperature power characteristic of the laser are affected finally.
Publication No. CN209358061U, discloses a current confinement structure for a buried heterojunction laser, which makes a mesa waveguide structure on a grating layer; forming a traditional table-shaped waveguide by using a yellow light process and an etching mode, then recoating photoresist, and forming a self-selective morphology in a region except the InP surface waveguide; etching the photoresist by using a plasma etching (RIE) technology to expose the suspended partial silicon oxide mask; and etching the redundant exposed area by using a wet etching technology, removing the surface photoresist by using a yellow light process, and finally growing the required P/N/P type indium phosphide by using a metal organic chemical vapor deposition mode to form a current limiting layer. The laser manufactured by the method has a complex process, and because the undercut length is in a micron or even nanometer level, the method is only used, so that the process repeatability is poor, the yield is low, and the laser cannot realize industrial mass production.
Disclosure of Invention
The invention aims to provide a preparation method of a buried heterojunction, which can form a high-rise effective current limiting layer, improve the current injection efficiency of a laser, further improve the reliability and high-low temperature characteristics of the laser, has simple process, can improve the uniformity and yield and realizes industrialized mass production.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions: a method of fabricating a buried heterojunction, comprising the steps of:
s1, manufacturing a grating layer on the surface of the epitaxial layer;
s2, growing an InP cover layer on the grating layer to fill and level the groove on the surface of the grating layer to obtain a flat surface;
s3, growing a sacrificial layer and an amorphous semiconductor material layer on the InP cover layer to obtain a transition structure;
s4, continuing to grow SiO on the transition structure2/SiNxA mask layer, and then etching the transition structure to form a platform-shaped structure;
s5, removing the SiO after the platform-shaped structure is formed2/SiNxAnd continuing to grow a P-InP layer and an N-InP layer on the mesa structure in sequence by taking the amorphous semiconductor material layer as the current mask layer to obtain a current limiting layer.
Further, the amorphous semiconductor material layer is a material layer formed by adding an oxygen-containing atmosphere into an AlGaInAs material, an InAlAs material, an InGaAs material or an InP material.
Further, the amorphous semiconductor material layer is a material layer formed by oxidizing an AlGaInAs material, an InAlAs material, an InGaAs material or an InP material exposed to an oxygen-containing environment.
Further, the epitaxial layer comprises a substrate and an InP buffer layer manufactured on the substrate, and the grating layer grows above the InP buffer layer.
Further, an active layer and an InP layer are grown between the InP buffer layer and the grating layer.
Further, an InP layer and an active layer are sequentially grown on the grating layer.
Furthermore, the growth methods of the active layer, the InP layer, the sacrificial layer and the amorphous semiconductor material layer all adopt a metal organic chemical vapor deposition method.
Further, in the step S1, a grating layer is fabricated on the surface of the epitaxial layer by using a holographic and etching process or an electron beam and etching process.
Further, in the step S2 and the step S5, the grown InP cap layer, the P-InP layer, and the N-InP layer are grown using metal organic chemical vapor deposition.
Further, in the step S4, a pattern is transferred to the SiO by using a photolithography process2/SiNxAnd then, forming the mesa structure by adopting a dry method and wet method combined etching process.
Compared with the prior art, the invention has the beneficial effects that: a method of fabricating a buried heterojunction by removing SiO before the growth of a confinement layer2/SiNxThe mask layer is removed, the eave structure is removed, the amorphous semiconductor material layer is used as a self-aligned mask, the MOCVD current limiting layer is grown, the amorphous epitaxial layers are easy to remove, the function of taking the self-aligned amorphous semiconductor material as the mask is realized, and accordingly undercut in the conventional buried heterojunction technology is avoided; the current injection efficiency of the laser can be improved, the reliability and the high-low temperature characteristics of the laser are further improved, meanwhile, the technical scheme is simple in process, the uniformity and the yield of the whole wafer can be improved, and industrial mass production is realized.
Drawings
FIG. 1 is a schematic view of a conventional mesa configuration;
FIG. 2 is an epitaxial schematic view of a conventional mesa structure;
FIG. 3 is a schematic diagram of a conventional buried heterojunction structure;
FIG. 4 is a schematic diagram of a mesa structure of a method of fabricating a buried heterojunction according to an embodiment of the present invention;
fig. 5 is a first epitaxial schematic view of a mesa structure of a method of fabricating a buried heterojunction according to an embodiment of the present invention;
fig. 6 is a second epitaxy diagram of the mesa structure of the method for fabricating a buried heterojunction according to the embodiment of the present invention;
FIG. 7 is a schematic diagram of a buried heterojunction structure of a method of fabricating a buried heterojunction according to an embodiment of the present invention;
in the reference symbols: 1-SiO2/SiNxA mask layer; 2-a mesa structure; 3-a substrate; 4-eave structure; 5-a layer of amorphous semiconductor material; 6-a sacrificial layer; a 7-InP cap layer; 8-a grating layer; 9-InP layer; 10-an active layer; 11-An InP buffer layer; a 12-N-InP layer; a 13-P-InP layer; 14-N-InP voids were grown.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 5, 6 and 7, an embodiment of the invention provides a method for fabricating a buried heterojunction, including the following steps: s1, manufacturing a grating layer 8 on the surface of the epitaxial layer; s2, growing an InP capping layer 7 on the grating layer 8 to fill and level the grooves on the surface of the grating layer 8, so as to obtain a flat surface; s3, growing a sacrificial layer 6 and an amorphous semiconductor material layer 5 on the InP capping layer 7 to obtain a transition structure; s4, continuing to grow SiO on the transition structure2/SiNx A mask layer 1, and then etching the transition structure to form a table-shaped structure 2; s5, removing the SiO after the platform-shaped structure 2 is formed2/SiNxAnd (3) a mask layer 1, and continuing to grow a P-InP layer 13 and an N-InP layer 12 on the mesa structure 2 in sequence by taking the amorphous semiconductor material layer 5 as the current mask layer to obtain a current limiting layer. In this embodiment, the SiO is removed before the growth of the confinement layer2/SiNxThe mask layer 1 is removed, so that the eave structure 4 is removed, the amorphous semiconductor material layer 5 is used as a self-aligned mask, the MOCVD current limiting layer is grown, the amorphous epitaxial layers are easy to remove, the function of taking the self-aligned amorphous semiconductor material as the mask is realized, and accordingly undercut in the conventional buried heterojunction technology is avoided; the current injection efficiency of the laser can be improved, the reliability and the high-low temperature characteristics of the laser are further improved, meanwhile, the technical scheme is simple in process, the uniformity and the yield of the whole wafer can be improved, and industrial mass production is realized. In a conventional buried heterojunction, as shown in FIG. 1, it comprises SiO2/SiNxMask layer1 mesa epitaxial layer 2, substrate 3, and in SiO2/SiNxAnd an eave structure 4 (underscut for short) is formed on the left and the right of the mask layer 1. As shown in fig. 2, the substrate 3, the InP buffer layer 11, the active layer 10, the InP layer 9, the grating layer 8, the InP cap layer 7, and the sacrificial layer 6 are arranged in this order from bottom to top. In FIG. 3, there are, from bottom to top, a substrate 3, a mesa 2, a P-InP layer 13, an N-InP layer 12, an N-InP growth void 14 and SiO2/SiNxMask layer 1. The traditional table structure diagram 1 utilizes a metal organic chemical vapor deposition method to grow an active layer 10 on a substrate 3, then utilizes a holographic etching process or an electron beam exposure and etching process to manufacture a grating layer 8 on the surface of an epitaxial layer, then utilizes a metal organic chemical vapor deposition method to grow an InP cover layer 7 and a sacrificial layer 6, and fills up grooves on the surface of the grating to enable the surface to be flat. Then, a mesa structure is formed on the grating layer 8 by growing SiO2/SiNxMask layer 1, transferring pattern to SiO by photolithography2/SiNxOn the mask layer 1, a conventional mesa structure is formed by an etching process combining a dry method and a wet method. Due to the isotropy of the wet etching, SiO is generated2/SiNxA very long eaves structure undercut is formed on the left and right of the mask layer 1, and the undercut can prevent InP atoms in heterojunction growth from migrating to the interior of an eaves, so that an effective high-rise current limiting layer cannot be formed after heterojunction growth, as shown in fig. 3. The lower current limiting layer causes poor current injection effect of the laser, and finally affects the reliability and high and low temperature power characteristics of the laser. Meanwhile, the eaves structure undercut can cause an N-InP growth cavity 14, and when a mask layer is removed and a cover layer InP grows again, growth defects are easily caused, and the reliability of the laser is affected. Before heterojunction burying, removing SiO2/SiNxThe mask layer, which is formed by using the amorphous semiconductor material layer 5 as a mask layer, does not have the conventional undercut to prevent the migration of InP atoms, so that the P-InP layer 13 and the N-InP layer 12 can form a high-rise current confinement layer after growth, as shown in fig. 7. Preferably, SiO2/SiNxThe width range of the mask layer 1 is 1-10um, and the width of the mesa structure is 0.5-5 um. Preferably, the P-InP layers 13 are formed on both sides of the mesa waveguide structure; an N-InP layer is formed on the P-InP layer 1312. Wherein the top of the P-InP layer 13 is at the same level as the bottom of the amorphous semiconductor material layer 5, the top of the N-InP layer 12 is higher than the top of the amorphous semiconductor material layer 5, and a funnel structure is formed between the N-InP layer 12 and the amorphous semiconductor material layer 5.
As an optimized solution of the embodiment of the present invention, please refer to fig. 5, fig. 6, and fig. 7, the amorphous semiconductor material layer 5 is a material layer formed by adding an oxygen-containing atmosphere to an AlGaInAs material, an InAlAs material, an InGaAs material, or an InP material. In this embodiment, this is a preparation method of the first amorphous semiconductor material layer 5, and AlGaInAs material, InAlAs material, InGaAs material or InP material may be added to the oxygen-containing atmosphere. In addition, the amorphous semiconductor material layer 5 is formed by oxidizing an AlGaInAs material, an InAlAs material, an InGaAs material, or an InP material exposed to an oxygen-containing atmosphere. This is a way to fabricate the second amorphous semiconductor material layer 5, and may be formed by exposing AlGaInAs material, InAlAs material, InGaAs material, or InP material to an oxygen-containing environment.
As an optimized solution of the embodiment of the present invention, please refer to fig. 5, 6, and 7, the epitaxial layer includes a substrate 3 and an InP buffer layer 11 fabricated on the substrate 3, and the grating layer 8 is grown on the InP buffer layer. In this embodiment, there are two growth modes, one is to grow an active layer 10 and an InP layer 9 between the InP buffer layer 11 and the grating layer 8, and the other is to sequentially grow an InP layer 9 and an active layer 10 on the grating layer 8. The difference between the two is that the grating layer 8 is below the active layer 10 in the mesa structure 2.
As an optimized solution of the embodiment of the present invention, the growth method of the active layer 10 adopts a metal organic chemical vapor deposition method. And manufacturing a grating layer 8 on the surface of the epitaxial layer by adopting a holographic and etching process or an electron beam and etching process. The grown InP cap layer 7, the P-InP layer 13, and the N-InP layer 12 are grown using metal organic chemical vapor deposition. Transferring a pattern to the SiO using a photolithographic process2/SiNxAnd forming the mesa structure 2 by adopting a dry method and wet method combined etching process after the mask layer 1 is formed.
Two embodiments based on the above embodiments are:
the first embodiment is as follows:
growing an active layer 10 on the substrate 3 by using a metal organic chemical vapor deposition method;
utilizing a holographic and etching process or an electron beam and etching process to manufacture a grating layer 8 on the surface of the epitaxial layer, then utilizing metal organic chemical vapor deposition to grow an InP cover layer 7, and filling grooves on the surface of the grating layer 8 to level the surface; then, a sacrificial layer 6 and an amorphous semiconductor material layer 5 formed by AlGaInAs material, InAlAs material, InGaAs material or InP material and the like are sequentially grown; the amorphous semiconductor material layer 5 is generated by adding oxygen-containing atmosphere in metal organic chemical vapor deposition;
growing SiO2/SiNxMask layer 1, transferring pattern to SiO by photolithography2/SiNxOn the mask layer 1, forming a traditional table-shaped structure 1 by utilizing a dry method and wet method combined etching process;
SiO removal2/SiNxMask layer 1 is shown in fig. 4, and P-InP layer 13 and N-InP layer 12 are sequentially grown by mocvd using amorphous semiconductor material 5 as a mask layer, and the structure is shown in fig. 7.
Example two:
growing an active layer 10 on the substrate 3 by using a metal organic chemical vapor deposition method;
utilizing a holographic and etching process or an electron beam and etching process to manufacture a grating layer 8 on the surface of the epitaxial layer, then utilizing metal organic chemical vapor deposition to grow an InP cover layer 7, and filling grooves on the surface of the grating layer 8 to level the surface; then, a sacrificial layer 6 and a crystalline semiconductor material layer 5 made of AlGaInAs material, InAlAs, InGaAs or InP and the like are sequentially grown;
exposing the AlGaInAs material or InAlAs or InGaAs or InP or other crystalline semiconductor material 5 on the sacrificial layer 6 to an oxygen-containing environment for oxidation, and finally forming an amorphous semiconductor material layer 5;
growing SiO2/SiNx A mask layer 1, transferring the pattern to the mask layer 1 by using a photoetching process, and forming a traditional platform shape by using an etching process combining a dry method and a wet methodStructure;
SiO removal2/SiNxThe mask layer 1 is shown in fig. 4, and the growth of the P-InP layer 13 and the N-InP layer 12 is sequentially performed by using the amorphous semiconductor material 5 as a mask layer by using a metal organic chemical vapor deposition method, and the structure is shown in fig. 7.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (10)

1. A method of fabricating a buried heterojunction, comprising the steps of:
s1, manufacturing a grating layer on the surface of the epitaxial layer;
s2, growing an InP cover layer on the grating layer to fill and level the groove on the surface of the grating layer to obtain a flat surface;
s3, growing a sacrificial layer and an amorphous semiconductor material layer on the InP cover layer to obtain a transition structure;
s4, continuing to grow SiO on the transition structure2/SiNxA mask layer, and then etching the transition structure to form a platform-shaped structure;
s5, removing the SiO after the platform-shaped structure is formed2/SiNxAnd continuing to sequentially grow a P-InP layer and an N-InP layer on the mesa structure by taking the amorphous semiconductor material layer as the current mask layer to obtain a current limiting layer, wherein the amorphous semiconductor material layer is made of AlGaInAs material, InAlAs material, InGaAs material or InP material after oxidation.
2. A method of fabricating a buried heterojunction as claimed in claim 1 wherein: the amorphous semiconductor material layer is formed by adding oxygen-containing atmosphere into AlGaInAs material, InAlAs material, InGaAs material or InP material.
3. A method of fabricating a buried heterojunction as claimed in claim 1 wherein: the amorphous semiconductor material layer is formed by oxidizing AlGaInAs material, InAlAs material, InGaAs material or InP material exposed in an oxygen-containing environment.
4. A method of fabricating a buried heterojunction as claimed in claim 1 wherein: the epitaxial layer comprises a substrate and an InP buffer layer manufactured on the substrate, and the grating layer grows above the InP buffer layer.
5. A method of fabricating a buried heterojunction as claimed in claim 4 wherein: an active layer and an InP layer are grown between the InP buffer layer and the grating layer.
6. A method of fabricating a buried heterojunction as claimed in claim 4 wherein: and sequentially growing an InP layer and an active layer on the grating layer.
7. A method of fabricating a buried heterojunction as claimed in claim 5 or 6 wherein: the growth methods of the active layer, the InP layer, the sacrificial layer and the amorphous semiconductor material layer all adopt a metal organic chemical vapor deposition method.
8. A method of fabricating a buried heterojunction as claimed in claim 1 wherein: in the step S1, a grating layer is formed on the surface of the epitaxial layer by a holographic and etching process or an electron beam and etching process.
9. A method of fabricating a buried heterojunction as claimed in claim 1 wherein: in the step S2 and the step S5, the grown InP cap layer, the P-InP layer, and the N-InP layer are grown using metal organic chemical vapor deposition.
10. The buried insert of claim 1The preparation method of the texture knot is characterized by comprising the following steps: in the step S4, a pattern is transferred to the SiO by using a photolithography process2/SiNxAnd then, forming the mesa structure by adopting a dry method and wet method combined etching process.
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