CN112864238B - 一种接触孔自对准低压场效应晶体管的制作方法 - Google Patents
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Abstract
本发明提出一种接触孔自对准低压场效应晶体管的制作方法,本发明减少了栅结晶间的距离,传统的器件,两个栅结晶间需要有接触孔,接触孔到trenchgate间需要一定的距离,本发明接触孔和gate trench自对准,上下隔离,有效减少了栅结晶间的距离;本发明沟槽尺寸固定,减少刻蚀负载效应影响,提高击穿电压及导通电阻性能;利用poly recess形成的接触孔,以及刻蚀对Si3N4和BPSG ILD不同的选择比来实现接触孔自对准从而实现trench MOS pitch缩小1/2~1/3,提高产品Ron性能。
Description
技术领域
本发明涉及晶体管制备技术领域,尤其涉及一种接触孔自对准低压场效应晶体管的制作方法。
背景技术
常规的沟槽式金属氧化物半导体场效应管,如图1所示,Gate trench(栅沟槽)因需要引线,导致引线区域的gate trench(栅多晶)较大,不同的trench(沟槽)尺寸,刻蚀时loading效应影响,导致引线区域trench深度较深,降低器件击穿电压,为了达到需要的击穿电压,要牺牲导通电阻。Source区域需要引线,受接触孔到gate trench间距影响,导致晶体管的尺寸受限。
发明内容
本发明的目的在于提出一种实现接触孔和栅多晶自对准,上下隔离,有效减少栅多晶间间距的晶体管制作方法。
为达到上述目的,本发明提出一种接触孔自对准低压场效应晶体管的制作方法,包括以下步骤:
步骤1:选取衬底;
步骤2:在所述衬底表面刻蚀沟槽;
步骤3:在所述衬底以及沟槽的表面生成氧化层;
步骤4:在所述沟槽以及衬底内填充多晶硅;
步骤5:对所述衬底元胞区的多晶硅进行刻蚀;
步骤6:在所述多晶硅表面生成氧化层,向所述衬底内注入体阱后退火;
步骤7:对衬底内Source源区光刻;
步骤8:低压化学气相淀积生长,在步骤6的氧化层表面生成Si3N4层;
步骤9:BPSG ILD层生长,回流;
步骤10:刻蚀掉所述衬底表面接触孔位置的BPSG ILD,保留沟槽内部分BPSG ILD;
步骤11:刻蚀掉所述接触孔表面的Si3N4层,保留所述沟槽内BPSG ILD层以下的Si3N4层;
步骤12:向所述接触孔内注入杂质,再退火激活注入的杂质;
步骤13:对接触孔内部的氧化层进行湿法腐蚀;
步骤14:向所述接触孔内布置金属连线。
进一步的,所述衬底为N-型磷掺杂衬底,电阻率范围:0~1.5mohm.cm;N-型磷外延层生长,电阻率范围:60mohm.cm~250mohm.cm,厚度:2um~4um。
进一步的,所述氧化层为二氧化硅层,所述二氧化硅层的厚度为1500-2000埃;
所述沟槽的的宽度为0.2-0.3um,相邻沟槽之间的间距为0.2-0.3um,深度为1-1.2um。
进一步的,在步骤5中,所述沟槽内多晶硅刻蚀后,沟槽内多晶硅表面相比于衬底表面凹陷2000-3000埃。
进一步的,在步骤10中,采用等离子体干法刻蚀对所述BPSG ILD进行刻蚀。
进一步的,在步骤11中,采用磷酸湿法腐蚀刻蚀所述Si3N4层。
与现有技术相比,本发明的优势之处在于:本发明减少了栅结晶间的距离,传统的器件,两个栅结晶间需要有接触孔,接触孔到trench gate间需要一定的距离,本发明接触孔和gate trench自对准,上下隔离,有效减少了栅结晶间的距离。
本发明沟槽尺寸固定,减少刻蚀负载效应影响,提高击穿电压及导通电阻性能;利用poly recess形成的接触孔,以及刻蚀对Si3N4和BPSG ILD不同的选择比来实现接触孔自对准从而实现trench MOS pitch缩小1/2~1/3,提高产品Ron性能。
附图说明
图1为本发明实施例中步骤1中衬底的结构示意图;
图2为本发明实施例中经过步骤2处理的衬底的结构示意图;
图3为本发明实施例中经过步骤4处理的衬底的结构示意图;
图4为本发明实施例中经过步骤5处理的衬底的结构示意图;
图5为本发明实施例中经过步骤6处理的衬底的结构示意图;
图6为本发明是实力中Source源区的结构示意图;
图7为本发明实施例中经过步骤8处理的衬底的结构示意图;
图8为本发明实施例中经过步骤9处理的晶体管的结构示意图;
图9为本发明实施例中经过步骤10处理的衬底的结构示意图;
图10为本发明实施例中经过步骤11处理的衬底的结构示意图;
图11为本发明实施例中经过步骤12处理的衬底的结构示意图;
图12为本发明实施例中经过步骤13处理的衬底的结构示意图;
图13为本发明实施例中经过步骤14处理的晶体管结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面将对本发明的技术方案作进一步地说明。
本发明提出一种接触孔自对准低压场效应晶体管的制作方法,包括以下步骤:
步骤1:选取衬底1;如图1所示,衬底1为N-型磷掺杂衬底1,电阻率范围:0~1.5mohm.cm;N-型磷外延层生长,电阻率范围:60mohm.cm~250mohm.cm,厚度:2um~4um。
步骤2:在衬底1表面刻蚀沟槽2;如图2所示,沟槽2的的宽度为0.2-0.3um,相邻沟槽2之间的间距为0.2-0.3um,深度为1-1.2um。
步骤3:如图3所示,在衬底1以及沟槽2的表面生成氧化层3,氧化层3为二氧化硅层,二氧化硅层的厚度为1500-2000埃。
步骤4:如图3所示,在沟槽2以及衬底1内填充多晶硅4;
步骤5:如图4所示,对衬底1元胞区的多晶硅4进行刻蚀;沟槽2内多晶硅4表面相比于衬底1表面凹陷2000-3000埃。
步骤6:如图5所示,在多晶硅4表面生成氧化层3,向衬底1内注入体阱5后退火;
步骤7:如图6所示,对衬底1内source源区6光刻;
步骤8:如图7所示,低压化学气相淀积生长,在步骤6的氧化层3表面生成Si3N4层7;
步骤9:如图8所示,BPSG ILD层8(BPSG为内部介质层,ILD为inter layerdielectric layer内部介质层)生长,回流;
步骤10:如图9所示,采用等离子体干法刻蚀,刻蚀掉衬底1表面接触孔9位置的BPSG ILD,保留沟槽2内部分BPSG ILD;
步骤11:如图10所示,采用磷酸湿法腐蚀刻蚀掉接触孔9表面的Si3N4层7,保留沟槽2内BPSG ILD层8以下的Si3N4层;
步骤12:如图11所示,向接触孔9内注入杂质,再退火激活注入的杂质;降低Sourcemask阻挡且接触孔9打开区域电阻Rb,削弱寄生NPN管效应,提高器件雪崩能力。
步骤13:如图12所示,对接触孔9内部的氧化层3进行湿法腐蚀;
步骤14:如图13所示,向接触孔9内布置金属连线。
在本实施例中,本发明减少了栅结晶间的距离,传统的器件,两个栅结晶间需要有接触孔9,接触孔9到trench gate间需要一定的距离,本发明接触孔9和gate trench自对准,上下隔离,有效减少了栅结晶间的距离。
本发明沟槽尺寸固定,减少刻蚀负载效应影响,提高击穿电压及导通电阻性能;利用poly recess形成的接触孔,以及刻蚀对Si3N4和BPSG ILD不同的选择比来实现接触孔9自对准从而实现trenchMOS pitch缩小1/2~1/3,提高产品Ron性能。
上述仅为本发明的优选实施例而已,并不对本发明起到任何限制作用。任何所属技术领域的技术人员,在不脱离本发明的技术方案的范围内,对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动,均属未脱离本发明的技术方案的内容,仍属于本发明的保护范围之内。
Claims (6)
1.一种接触孔自对准低压场效应晶体管的制作方法,其特征在于,包括以下步骤:
步骤1:选取衬底;
步骤2:在所述衬底表面刻蚀沟槽;
步骤3:在所述衬底以及沟槽的表面生成氧化层;
步骤4:在所述沟槽以及衬底内填充多晶硅;
步骤5:对所述衬底元胞区的多晶硅进行刻蚀;
步骤6:在所述多晶硅表面生成氧化层,向所述衬底内注入体阱后退火;
步骤7:对衬底内Source源区光刻;
步骤8:低压化学气相淀积生长,在步骤6的氧化层表面生成Si3N4层;
步骤9:BPSGILD层生长,回流;
步骤10:刻蚀掉所述衬底表面接触孔位置的BPSGILD,保留沟槽内部分BPSGILD;
步骤11:刻蚀掉所述接触孔表面的Si3N4层,保留所述沟槽内BPSGILD层以下的Si3N4层;
步骤12:向所述接触孔内注入杂质,再退火激活注入的杂质;
步骤13:对接触孔内部的氧化层进行湿法腐蚀;
步骤14:向所述接触孔内布置金属连线。
2.根据权利要求1所述的接触孔自对准低压场效应晶体管的制作方法,其特征在于,所述衬底为N-型磷掺杂衬底,电阻率范围:0~1.5mohm.cm;N-型磷外延层生长,电阻率范围:60mohm.cm~250mohm.cm,厚度:2um~4um。
3.根据权利要求1所述的接触孔自对准低压场效应晶体管的制作方法,其特征在于,所述氧化层为二氧化硅层,所述二氧化硅层的厚度为1500-2000埃;所述沟槽的的宽度为0.2-0.3um,相邻沟槽之间的间距为0.2-0.3um,深度为1-1.2um。
4.根据权利要求1所述的接触孔自对准低压场效应晶体管的制作方法,其特征在于,在步骤5中,所述沟槽内多晶硅刻蚀后,沟槽内多晶硅表面相比于衬底表面凹陷2000-3000埃。
5.根据权利要求1所述的接触孔自对准低压场效应晶体管的制作方法,其特征在于,在步骤10中,采用等离子体干法刻蚀对所述BPSGILD进行刻蚀。
6.根据权利要求1所述的接触孔自对准低压场效应晶体管的制作方法,其特征在于,在步骤11中,采用磷酸湿法腐蚀刻蚀所述Si3N4层。
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