CN112864176A - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The array substrate comprises an array area and an outer circuit area surrounding the array area, the array substrate comprises a substrate layer, a binding pad and a fan-shaped wiring layer, and the substrate layer comprises a first surface and a second surface arranged opposite to the first surface; the outer circuit area, the substrate layer is provided with prefabricated hole, prefabricated hole runs through the substrate layer, the binding pad set up in the prefabricated hole, fan-shaped routing layer set up in the second surface of substrate layer, just, fan-shaped routing layer with the binding pad electricity is connected. Through set up prefabricated hole on the substrate layer set up the binding pad in the prefabricated hole, and then will fan-shaped routing layer sets up array substrate's the back, and then reduced array substrate's frame, and then realized narrow frame design.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel.
Background
With the development of commercial oversized display application such as outdoor movie and television, the oversized display is realized by splicing the relatively small-sized ultra-narrow frame screens, so that the technology has a wide development prospect.
In order to realize the narrow frame technology, two modes are usually adopted at present, namely, one mode adopts a side binding technology, but is limited by the height of a fan-shaped routing layer, so that the frame cannot be further reduced; in the other method, a double substrate of glass and a polyimide film layer is cut off, glass in a non-display area at the edge is cut off, and the polyimide film layer with the circuit pattern is bent to the back side for binding.
Disclosure of Invention
The embodiment of the application provides an array substrate, a preparation method thereof and a display panel, so as to reduce the frame of the array substrate.
An embodiment of the present application provides an array substrate, the array substrate including an array region and an outer circuit region surrounding the array region, including:
a substrate layer comprising a first surface and a second surface disposed opposite the first surface; in the external circuit area, the substrate layer is provided with prefabricated holes, and the prefabricated holes penetrate through the substrate layer;
a binding pad disposed in the preformed hole; and
the fan-shaped wiring layer is arranged on the second surface of the substrate layer, and the fan-shaped wiring layer is electrically connected with the binding pad.
Optionally, in some embodiments of the present application, the array substrate further includes a chip on film, where the chip on film is disposed on a side of the fan-shaped routing layer away from the substrate layer.
Optionally, in some embodiments of the present application, the array substrate further includes a light-shielding layer, and in the array region, the light-shielding layer is disposed on the first surface of the substrate layer.
Optionally, in some embodiments of the present application, the array substrate further includes a buffer layer, and the buffer layer covers the substrate layer, the bonding pad, and the light shielding layer.
Accordingly, an embodiment of the present invention further provides a method for manufacturing an array substrate, the array substrate including an array region and an outer circuit region surrounding the array region, the method including:
providing a sacrificial layer;
arranging a substrate layer on the sacrificial layer, wherein the substrate layer comprises a first surface and a second surface arranged opposite to the first surface, and the second surface of the substrate layer is positioned at one side close to the sacrificial layer; in the external circuit area, the substrate layer is provided with a prefabricated hole which penetrates through the substrate layer to expose the sacrificial layer;
arranging a binding pad in the prefabricated hole;
stripping the sacrificial layer from the substrate layer, and turning over the substrate layer;
and in the external circuit area, a fan-shaped wiring layer is arranged on the second surface of the substrate layer and is electrically connected with the binding pad.
Optionally, in some embodiments of the present application, after the step of disposing the bonding pad in the preformed hole, before the step of peeling the sacrificial layer from the substrate layer and turning the substrate layer over, the method further includes:
arranging an adhesive layer on the substrate layer and the binding pad;
and a cover plate is arranged on the adhesive layer.
Optionally, in some embodiments of the present application, in the external circuit area, a fan-shaped routing layer is disposed on the second surface of the substrate layer, and after the step of electrically connecting the fan-shaped routing layer to a bonding pad, the method further includes:
and a chip on film is arranged on the fan-shaped wiring layer.
Optionally, in some embodiments of the present application, after the step of disposing a flip chip on the fan-shaped routing layer, the method further includes:
and carrying out heat treatment on the glue layer and the cover plate, and removing the glue layer and the cover plate.
Optionally, in some embodiments of the present application, the step of disposing a binding pad in the preformed hole includes:
and arranging a metal layer material on the first surface of the substrate layer, and etching to form a light shielding layer and a binding pad, wherein the light shielding layer is positioned in the array area, and the binding pad is positioned in the prefabricated hole of the external circuit area.
Correspondingly, an embodiment of the present application further provides a display panel, including the array substrate as set forth in any of the above.
The array substrate comprises an array area and an outer circuit area surrounding the array area, the array substrate comprises a substrate layer, a binding pad and a fan-shaped wiring layer, and the substrate layer comprises a first surface and a second surface arranged opposite to the first surface; the outer circuit area, the substrate layer is provided with prefabricated hole, prefabricated hole runs through the substrate layer, the binding pad set up in the prefabricated hole, fan-shaped routing layer set up in the second surface of substrate layer, just, fan-shaped routing layer with the binding pad electricity is connected. Through set up prefabricated hole on the substrate layer set up the binding pad in the prefabricated hole, and then will fan-shaped routing layer sets up array substrate's the back, and then reduced array substrate's frame, and then realized narrow frame design.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure.
Fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
Fig. 3 to 11 are cross-sectional views illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view illustrating an array substrate according to an embodiment of the present disclosure. The present application provides an array substrate 10. The array substrate 10 includes an array region 11 and an outer circuit region 12 surrounding the array region 11. The array region 11 is used for arranging a driving circuit structure including a thin film transistor. The external circuit area 12 is used for disposing an external circuit structure so that the driving circuit structure of the array area 11 is electrically connected with an external circuit. The array substrate 10 includes a substrate layer 100, a bonding pad 200, and a fan-shaped routing layer 300. The specific description is as follows:
the substrate layer 100 comprises a first surface 110 and a second surface 120 arranged opposite to the first surface 110. In the external circuit area 12, the substrate layer 100 is provided with a preformed hole 101. The pre-fabricated holes 101 extend through the substrate layer 100. The vertical cross-sectional shape of the preformed hole 101 may be isosceles trapezoid, rectangle, circle, irregular shape, or the like. The material of the substrate layer 100 includes polyimide, but is not limited thereto.
The binding pad 200 is disposed in the prefabricated hole 101. The material of the bonding pad 200 includes one or a combination of Mo, Cu, Al, Ti, and Indium Tin Oxide (ITO). The bonding pad 200 is electrically connected to a driving circuit of the thin film transistor.
The fan-shaped wiring layer 300 is disposed on the second surface 120 of the substrate layer 100, and the fan-shaped wiring layer 300 is electrically connected to the bonding pad 200. The material of the fan-shaped routing layer 300 comprises one or a combination of more of Mo, Cu, Al, Ti and ITO. The fan-shaped wiring layer 300 is used for connecting data lines and a chip on film. The fan-shaped wiring layer 300 is called a fan-shaped wiring layer 300 because the shape of the whole wiring layer is similar to a fan.
The array substrate further includes a chip on film 400. The flip chip package 400 is disposed on a side of the fan-shaped wiring layer 300 away from the substrate layer 100. The chip on film 400 is electrically connected to the fan-shaped wiring layer 300.
In this application, through will binding the pad and set up in prefabricated hole, and then switch on the second surface to the substrate layer at the positive fan-shaped routing layer of array substrate with setting up among the prior art, and then saved the positive line space of walking of array substrate, and, when need carry out the second surface of lateral bending to the substrate layer because of the substrate layer among the avoiding prior art, lead to the laminating to appear peeling off or the cracked problem of laminating, and then improved array substrate's yield, and then improved array substrate's performance, and reduced array substrate's frame, and then realize the design of narrow frame.
In an embodiment, the array substrate 10 further includes a light-shielding layer 500. The light-shielding layer 500 and the bonding pad 200 are disposed on the first surface 110 of the substrate layer 100 in the same layer. The light-shielding layer 500 is located in the array region 11. The material of the light shielding layer 500 includes one or a combination of Mo, Cu, Al, Ti, and ITO.
The light shielding layer 500 is used for shielding external light entering the array substrate 10, and the active layer 500 is prevented from being adversely affected by the external light, so that the performance of the array substrate 10 is improved.
In an embodiment, a reflective surface 501 is disposed on a surface of the light shielding layer 500 close to the substrate layer 100. The reflecting surface 501 is used for reflecting external light entering the array substrate 10, so that the light shielding effect of the light shielding layer 500 is further improved, and the performance of the array substrate 10 is further improved.
In an embodiment, the reflecting surface 501 is a concave-convex microstructure.
In an embodiment, the array substrate 10 further includes a buffer layer 600. The buffer layer 600 covers the substrate layer 100, the bonding pad 200, and the light shielding layer 500. The material of the buffer layer 600 includes SixOyAnd SixNyOne or a combination of several of them.
In one embodiment, the array substrate 10 further includes an active layer 700. The active layer 700 is disposed on the buffer layer 600, and the active layer 700 is located on the light-shielding layer 500. The material of the active layer 700 includes indium gallium zinc oxide.
In one embodiment, the array substrate 10 further includes a gate insulating layer 800 and a gate 900. The gate insulating layer 800 and the gate electrode 900 are sequentially stacked on the active layer 700. The material of the gate insulating layer 800 includes SixOyAnd SixNyOne or a combination of several of them. The material of the gate 900 includes one or a combination of Ag, Fe, Mo, Cu, Al, Ti, and ITO.
In one embodiment, the array substrate 10 further includes an interlayer insulating layer 1000. The interlayer insulating layer 1000 covers the buffer layer 600, the active layer 700, the gate insulating layer 800, and the gate electrode 900. The interlayer insulating layer 1000 includes a first via 1001, a second via 1002, and a third via 1003. The first via hole 1001 penetrates the interlayer insulating layer 1000 and the buffer layer 600 to expose the light shielding layer 500. The second via hole 1002 penetrates the interlayer insulating layer 1000 to expose one side of the active layer 700. The first via 1001 and the second via 1002 are located on the same side of the active layer 700. The third through hole 1003 penetrates the interlayer insulating layer 1000 to expose the other side of the active layer 700. The material of the interlayer insulating layer 1000 includes SixOyAnd SixNyOne or a combination of several of them.
In one embodiment, the array substrate 10 further includes a source 1100 and a drain 1200. The source 1100 is disposed on the interlayer insulating layer 1000, and extends into the first through hole 1001 to be electrically connected to the light shielding layer 500 and extends into the second through hole 1002 to be electrically connected to the active layer 700. The drain electrode 1200 is disposed on the interlayer insulating layer 1000, and extends into the third through hole 1003 to be electrically connected to the active layer 700. The source 1100 and the drain 1200 are made of one or a combination of Ag, Fe, Mo, Cu, Al, Ti and ITO.
In one embodiment, the array substrate 10 further includes a planarization layer 1300. The planarization layer 1300 covers the interlayer insulating layer 1000, the source electrode 1100, and the drain electrode 1200. The planarization layer 1300 is used to planarize the structure of the array substrate 10, thereby preventing damage during subsequent processes or use, and further improving the performance of the array substrate 10.
The application provides an array substrate through will bind the pad set up in the prefabricated hole, and then switch on the fan-shaped routing layer of the first surface among the prior art to the second surface of substrate layer, and then saved the positive line space of walking of array substrate, and, the substrate layer need not carry out the second surface of lateral bending to the substrate layer, and then has reduced array substrate's frame, and then has realized the design of narrow frame to array substrate's performance has been improved.
Referring to fig. 2 and fig. 3 to fig. 11, fig. 2 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure. Fig. 3 to 11 are cross-sectional views illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure. The application also provides a preparation method of the array substrate. The array substrate 10 includes an array region 11 and an outer circuit region 12 surrounding the array region 11. The array region 11 is used for arranging a driving circuit structure including a thin film transistor. The external circuit area 12 is used for disposing an external circuit structure so that the driving circuit structure of the array area 11 is electrically connected with an external circuit. The preparation method of the array substrate 10 comprises the following specific preparation steps:
and step B21, providing a sacrificial layer.
Referring to fig. 3, specifically, the sacrificial layer 1400 is a glass substrate.
Step B22, arranging a substrate layer on the sacrificial layer, wherein the substrate layer comprises a display surface and a second surface arranged opposite to the display surface, and the second surface of the substrate layer is positioned at one side close to the sacrificial layer; in the external circuit area, the substrate layer is provided with a preformed hole, and the preformed hole penetrates through the substrate layer to expose the sacrificial layer.
Referring to fig. 3 to fig. 5, specifically, a substrate layer 100 material is coated on the sacrificial layer 1400, then a mask 1500 is provided, the mask 1500 is located on a side of the substrate layer 100 away from the sacrificial layer 1400, then the substrate layer 100 material is exposed by extreme ultraviolet, and then the substrate layer 100 material is developed to form the substrate layer 100. The substrate layer 100 is provided with preformed holes 101. The pre-fabricated holes 101 extend through the substrate layer 100 to expose the sacrificial layer 1400. The vertical cross-sectional shape of the preformed hole 101 may be isosceles trapezoid, rectangle, circle, irregular shape, or the like. The material of the substrate layer 100 includes polyimide, polyphthalate, cyclic olefin polymer, and polyethylene terephthalate.
In the application, the substrate layer 100 is formed by polyimide, and the prefabricated holes 101 can be formed in the substrate layer 100 without coating photoresist, so that the preparation process of the array substrate is simplified, and the production cost is reduced.
The term "extreme ultraviolet" means that ultraviolet rays are emitted after exciting the negative electrode of the ultraviolet tube by energization.
And B23, arranging a binding pad in the prefabricated hole.
Referring to fig. 6, specifically, a binding pad 200 material is disposed on the first surface 110 of the substrate layer 100, and the binding pad 200 material is etched to form the binding pad 200 disposed in the preformed hole 101. The material of the bonding pad 200 includes one or a combination of Mo, Cu, Al, Ti, and ITO. The bonding pad 200 is used to electrically connect with a driving circuit structure of a thin film transistor.
In an embodiment, after the step of disposing the bonding pad 200 on the first surface 110 of the substrate layer 100, the method further includes:
in the array region 11, a light shielding layer 500 material is disposed on the first surface 100 of the substrate layer 100, and the light shielding layer 500 is formed by etching. The material of the light shielding layer 500 includes one or a combination of Mo, Cu, Al, Ti, and ITO.
In the present application, the bonding pad 200 and the light shielding layer 500 are formed by two manufacturing processes, respectively, so that the accuracy of manufacturing the array substrate 10 is improved.
In another embodiment, a bonding pad 200 material and a light shielding layer 500 material are disposed on the first surface 110 of the substrate layer 100, and the bonding pad 200 material and the light shielding layer 500 material are etched to form the bonding pad 200 and the light shielding layer 500. The binding pad 200 is disposed in the prefabricated hole 101. The light-shielding layer 500 is located in the array region 11.
The light shielding layer 500 is used for shielding external light entering the array substrate 10, and the active layer 500 is prevented from being adversely affected by the external light, so that the performance of the array substrate 10 is improved.
In the present application, the bonding pad 200 and the light shielding layer 500 are formed by the same process, which reduces the cost of the array substrate 10 and shortens the manufacturing period.
In an embodiment, after step B23, the method further includes:
a buffer layer 600 is disposed on the substrate layer 100, the bonding pad 200, and the light-shielding layer 500. The material of the buffer layer 600 includes SixOyAnd SixNyOne or a combination of several of them.
In an embodiment, after the step of disposing the buffer layer 600 on the substrate layer 100, the bonding pad 200, and the light shielding layer 500, the method further includes:
an active layer 700 material is disposed on the buffer layer 600, and the active layer 700 is etched. The active layer 700 is positioned on the light-shielding layer 500. The material of the active layer 700 includes indium gallium zinc oxide.
In an embodiment, after the step of forming the active layer 700 on the buffer layer 600, the method further includes:
a gate insulating layer 800 and the gate electrode 900 are sequentially stacked on the active layer 700. The material of the gate insulating layer 800 includes SixOyAnd SixNyOne or a combination of several of them. The material of the gate 900 includes one or a combination of Ag, Fe, Mo, Cu, Al, Ti, and ITO.
In an embodiment, after the step of sequentially stacking and disposing the gate insulating layer 800 and the gate electrode 900 on the active layer 700, the method further includes:
an interlayer insulating layer 1000 material is disposed on the buffer layer 600, the active layer 700, the gate insulating layer 800, and the gate electrode 900, and the interlayer insulating layer 1000 is formed by etching. The interlayer insulating layer 1000 includes a first via 1001, a second via 1002, and a third via 1003. The first via hole 1001 penetrates the interlayer insulating layer 1000 and the buffer layer 600 to expose the light shielding layer 500. The second via hole 1002 penetrates the interlayer insulating layer 1000 to expose one side of the active layer 700. The first via 1001 and the second via 1002 are located on the same side of the active layer 700. The third through hole 1003 penetrates the interlayer insulating layer 1000 to expose the other side of the active layer 700. The material of the interlayer insulating layer 1000 includes SixOyAnd SixNyOne or a combination of several of them.
In an embodiment, after the step of forming the interlayer insulating layer 1000 on the buffer layer 600, the active layer 700, the gate insulating layer 800, and the gate electrode 900, the method further includes:
and disposing a source 1100 material and a drain 1200 material on the interlayer insulating layer 1000, etching to form a source 1100 and a drain 1200, wherein the source 1100 extends into the first through hole 1001 to be electrically connected with the light shielding layer 500 and extends into the second through hole 1002 to be electrically connected with the active layer 700, and the drain 1200 extends into the third through hole 1003 to be electrically connected with the active layer 700. The source 1100 and the drain 1200 are made of one or a combination of Ag, Fe, Mo, Cu, Al, Ti and ITO.
In an embodiment, after the step of forming the source 1100 material and the drain 1200 on the interlayer insulating layer 1000, the method further includes:
a planarization layer 1300 is formed on the interlayer insulating layer 1000, the source electrode 1100, and the drain electrode 1200. The planarization layer 1300 is used to planarize the structure of the array substrate 10, thereby preventing damage during subsequent processes or use, and further improving the performance of the array substrate 10.
In an embodiment, after the step of forming the planarization layer 1300 on the interlayer insulating layer 1000, the source electrode 1100 and the drain electrode 1200, the method further includes:
referring to fig. 7, an adhesive layer 1600 is disposed on the substrate layer 100 and the bonding pads 200, and then a cover plate 1700 is disposed on the adhesive layer 1600.
Specifically, a glue layer 1600 and a cover plate 1700 are sequentially stacked on the planarization layer 1300. The adhesive layer 1600 is a heat-sensitive adhesive. The cover plate 1700 is a glass cover plate.
In the present application, the adhesive layer 1600 is disposed on the flat layer 1300 first, so as to ensure the attachment precision of the cover plate 1700 in the subsequent attachment process, and further ensure the stable performance of the subsequent process; the cover plate 1700 is arranged on the adhesive layer 1600, so that the substrate layer 100 is in a soft state and cannot be subjected to subsequent processing after being processed by a laser lift-off technology in the subsequent processing, that is, the deformation of the substrate layer 100 is controlled by the cover plate 1700, and the subsequent processing is ensured; the cover plate 1700 is arranged on the adhesive layer 1600 to protect other structures in the array substrate 10, so that the yield of the array substrate 10 is improved, and the performance of the array substrate 10 is improved.
And B24, peeling the sacrificial layer from the substrate layer, and turning the substrate layer.
Referring to fig. 8 and 9, specifically, the sacrificial layer 1400 is stripped from the substrate layer 100 by using a laser stripping technique, and then the semi-finished product is turned over. The semi-finished product comprises the substrate layer 100, the bonding pad 200, the fan-shaped wiring layer 300, the chip on film 400, the light shielding layer 500, the buffer layer 600, the active layer 700, the gate insulating layer 800, the gate 900, the interlayer insulating layer 1000, the source 1100, the drain 1200, the flat layer 1300, the glue layer 1600 and the cover plate 1700.
And step B25, arranging a fan-shaped wiring layer on the second surface of the substrate layer in the external circuit area, wherein the fan-shaped wiring layer is electrically connected with the binding pad.
Referring to fig. 9, specifically, a fan-shaped wiring layer 300 material is disposed on the second surface 120 of the substrate layer 100, and the fan-shaped wiring layer 300 material is processed by a photolithography process and an etching process to form the fan-shaped wiring layer 300. The fan-shaped wiring layer 300 is electrically connected to the bonding pad 200. The material of the fan-shaped routing layer 300 comprises one or a combination of more of Mo, Cu, Al, Ti and ITO.
In an embodiment, after the step of disposing the fan-shaped wiring layer 300 on the second surface 120 of the substrate layer 100, the method further includes:
referring to fig. 10, a flip chip film 400 is disposed on the fan-shaped wiring layer 300. The chip on film 400 is electrically connected to the fan-shaped wiring layer 300.
In an embodiment, after the step of disposing the flip chip package 400 on the fan-shaped wiring layer 300, the method further includes:
referring to fig. 11, the adhesive layer 1600 and the cover plate 1700 are thermally processed, and the adhesive layer 1600, the cover plate 1700 and the planarization layer 1300 are peeled off to obtain the array substrate 10 of the present application. The temperature of the heat treatment is 40-200 ℃.
The application provides a preparation method of an array substrate, wherein a prefabricated hole 101 is arranged in advance in a substrate layer 100, so that a metal pad 200 is arranged in the prefabricated hole 101, subsequent processes are continuously carried out on a first surface 110 of the substrate layer 100, the first surface 110 of the substrate layer 100 is turned over after the processes are completed, and a fan-shaped wiring layer 300 is formed on a second surface 120 of the substrate layer 100, so that the fan-shaped wiring layer 300 is conducted to the second surface 120 of the substrate layer 100, the wiring space of the array substrate 10 is saved, the frame of the array substrate 10 is reduced, and the narrow-frame design is realized; the array substrate 10 prepared by the preparation method provided by the application has the advantages of simple preparation process, high yield and reduced production cost.
The present application also provides a display panel including the array substrate 10 provided in the present application. The display panel of the present application may be a top-emitting organic light emitting diode display panel, a top-emitting micro light emitting diode display panel, or a top-emitting mini light emitting diode display panel.
The application provides a display panel will array substrate 10 is applied to among the display panel, wherein, first surface 110 is towards display panel's display surface, second surface 120 is towards display panel's non-display surface, and then has reduced display panel's frame, and then has improved display panel's screen and has accounted for the ratio.
The array substrate comprises a display area and an outer circuit area surrounding the display area, the array substrate comprises a substrate layer, a binding pad and a fan-shaped wiring layer, and the substrate layer comprises a first surface and a second surface arranged opposite to the first surface; the outer circuit area, the substrate layer is provided with prefabricated hole, prefabricated hole runs through the substrate layer, the binding pad set up in the prefabricated hole, fan-shaped routing layer set up in the second surface of substrate layer, just, fan-shaped routing layer with the binding pad electricity is connected. Through set up prefabricated hole on the substrate layer set up the binding pad in the prefabricated hole, and then the back of array substrate sets up fan-shaped routing layer, and then has reduced array substrate's frame, and then realize narrow frame design.
The array substrate, the manufacturing method thereof, and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An array substrate, wherein the array substrate comprises an array region and an outer circuit region surrounding the array region, comprising:
a substrate layer comprising a first surface and a second surface disposed opposite the first surface; in the external circuit area, the substrate layer is provided with prefabricated holes, and the prefabricated holes penetrate through the substrate layer;
a binding pad disposed in the preformed hole; and
the fan-shaped wiring layer is arranged on the second surface of the substrate layer, and the fan-shaped wiring layer is electrically connected with the binding pad.
2. The array substrate of claim 1, further comprising a chip on film disposed on a side of the fan-shaped routing layer away from the substrate layer.
3. The array substrate of claim 1, further comprising a light shielding layer disposed on the first surface of the substrate layer in the array region.
4. The array substrate of claim 3, further comprising a buffer layer covering the substrate layer, the bonding pads, and the light-shielding layer.
5. A method for preparing an array substrate, wherein the array substrate comprises an array area and an outer circuit area surrounding the array area, comprising:
providing a sacrificial layer;
arranging a substrate layer on the sacrificial layer, wherein the substrate layer comprises a first surface and a second surface arranged opposite to the first surface, and the second surface of the substrate layer is positioned at one side close to the sacrificial layer; in the external circuit area, the substrate layer is provided with a prefabricated hole which penetrates through the substrate layer to expose the sacrificial layer;
arranging a binding pad in the prefabricated hole;
stripping the sacrificial layer from the substrate layer, and turning over the substrate layer;
and in the external circuit area, a fan-shaped wiring layer is arranged on the second surface of the substrate layer and is electrically connected with the binding pad.
6. The method for manufacturing an array substrate according to claim 5, wherein after the step of disposing the bonding pads in the preformed holes, and before the step of peeling the sacrificial layer from the substrate layer and turning the substrate layer over, the method further comprises:
arranging an adhesive layer on the substrate layer and the binding pad;
and a cover plate is arranged on the adhesive layer.
7. The method for manufacturing an array substrate according to claim 6, wherein a fan-shaped wiring layer is disposed on the second surface of the substrate layer in the external circuit area, and the step of electrically connecting the fan-shaped wiring layer to a bonding pad is further followed by:
and a chip on film is arranged on the fan-shaped wiring layer.
8. The method for manufacturing an array substrate according to claim 7, wherein after the step of disposing a flip chip on the fan-shaped routing layer, the method further comprises:
and carrying out heat treatment on the glue layer and the cover plate, and removing the glue layer and the cover plate.
9. The method for manufacturing an array substrate according to claim 5, wherein the step of disposing the bonding pads in the preformed holes comprises:
and arranging a metal layer material on the first surface of the substrate layer, and etching to form a light shielding layer and a binding pad, wherein the light shielding layer is positioned in the array area, and the binding pad is positioned in the prefabricated hole of the external circuit area.
10. A display panel comprising the array substrate according to any one of claims 1 to 4.
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| CN202110112916.6A CN112864176A (en) | 2021-01-27 | 2021-01-27 | Array substrate, preparation method thereof and display panel |
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| CN114035387A (en) * | 2021-11-30 | 2022-02-11 | 绵阳惠科光电科技有限公司 | Array substrate and display panel |
| CN114299828A (en) * | 2022-02-14 | 2022-04-08 | 惠州华星光电显示有限公司 | Display unit, spliced screen and display device |
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