CN112864162A - Page buffer, field effect transistor and three-dimensional memory - Google Patents

Page buffer, field effect transistor and three-dimensional memory Download PDF

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CN112864162A
CN112864162A CN202110231575.4A CN202110231575A CN112864162A CN 112864162 A CN112864162 A CN 112864162A CN 202110231575 A CN202110231575 A CN 202110231575A CN 112864162 A CN112864162 A CN 112864162A
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region
field effect
page buffer
length
transistor
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CN112864162B (en
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陈亮
甘程
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

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Abstract

The embodiment of the application provides a page buffer, a field effect transistor and a three-dimensional memory, wherein the page buffer is applied to the three-dimensional memory and comprises: at least one transistor cell; each of the transistor units includes at least one field effect transistor, and each of the field effect transistors includes at least: a channel region and a gate overlying the channel region; the first end of the grid electrode is provided with an epitaxial region, the size of the epitaxial region is larger than that of an extension region corresponding to the second end of the grid electrode, wherein the first end and the second end are two opposite ends of the grid electrode respectively; the epitaxial region is used for being connected with a contact hole, a metal wire is filled in the contact hole, and the metal wire is used for providing voltage for the grid so as to conduct the field effect transistor.

Description

Page buffer, field effect transistor and three-dimensional memory
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a page buffer, a field effect transistor, and a three-dimensional memory.
Background
In a three-dimensional flash memory (3D NAND), a Page Buffer (PB) occupies a large area of a chip, and thus, a reduction in PB size results in a reduction in the entire chip size. The Saddle-shaped fin field effect transistor (Saddle) is a Low Voltage transistor (Low Voltage Metal Oxide Semiconductor) with a special structure, and due to the special transistor structure, the Channel Length (Channel Length) can be greatly reduced under the condition that the Leakage Level (Leakage Level) is almost unchanged, so that the Saddle-shaped fin field effect transistor can be used for reducing the whole size of a PB (positive/negative) transistor.
However, as the channel length of the saddle finfet is reduced, Contact holes (CTs) cannot be formed on the gates above the channel region, and there is no extra space for receiving Contact holes on the gates extending beyond the ends of the channel region due to the PB pitch constraint.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a page buffer, a field effect transistor and a three-dimensional memory, which can receive a contact hole on a gate when a channel length of a saddle-shaped fin field effect transistor and a pitch of PB are sufficiently small.
The technical scheme of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a page buffer applied to a three-dimensional memory, where the page buffer includes: at least one transistor cell;
each transistor unit comprises at least one field effect transistor, and each field effect transistor at least comprises a channel region and a grid electrode covering the channel region;
the first end of the grid electrode is provided with an epitaxial region, the size of the epitaxial region is larger than that of an extension region corresponding to the second end of the grid electrode, wherein the first end and the second end are two opposite ends of the grid electrode respectively;
the epitaxial region is used for being connected with a contact hole, a metal wire is filled in the contact hole, and the metal wire is used for providing voltage for the grid so as to conduct the field effect transistor.
In some embodiments, two adjacent epitaxial regions in the same transistor cell are located on different sides of the gate in the transistor cell, and two adjacent epitaxial regions in different transistor cells are located at the same position relative to the gate in the transistor cell where each epitaxial region is located.
In some embodiments, the page buffer is located in peripheral circuitry of the three-dimensional memory, each of the transistor cells of the page buffer being coupled with a memory cell array of the three-dimensional memory by a bit line;
the page buffer is used for writing data into the memory cell array or reading data in the memory cell array through the bit line when the field effect transistor is conducted.
In some embodiments, the field effect transistor comprises a saddle-shaped fin field effect transistor.
In some embodiments, the extension region is a region where the second end of the gate extends out of the channel region, and the size of the extension region includes a first length of the extension region in a first direction and a second length of the extension region in a second direction;
the epitaxial region is a region in which the first end of the gate extends out of the channel region, and the size of the epitaxial region comprises a third length of the epitaxial region in the first direction and a fourth length of the epitaxial region in the second direction; the first direction is perpendicular to the second direction, and a plane formed by the first direction and the second direction is perpendicular to the extending direction of the contact hole;
wherein the third length is greater than the first length and the fourth length is greater than the second length.
In some embodiments, the overlapping region of the contact hole and the epitaxial region is located at the center of the epitaxial region.
In some embodiments, the contact hole comprises a circular hole; the diameter of the circular hole is smaller than the third length and smaller than the fourth length, and a difference between the diameter of the circular hole and the channel length is smaller than a first preset difference.
In some embodiments, the contact hole comprises a polygonal hole; the length of the polygonal hole in the first direction is less than the third length, and the length of the polygonal hole in the second direction is less than the fourth length;
the difference between the length of the polygonal hole in the second direction and the channel length is less than a second preset difference.
In some embodiments, each of the field effect transistors further comprises a source region and a drain region located on both sides of the channel region; the source region and the drain region are respectively connected with one contact hole;
wherein the contact holes on the source region, the drain region and the epitaxial region are staggered.
In some embodiments, two adjacent contact holes in the same field effect transistor have a first preset distance or a second preset distance therebetween;
wherein the first preset distance comprises a distance between two contact holes in the first direction and a distance between two contact holes in the second direction;
the second preset distance includes a distance between the two contact holes in the first direction and a distance between the two contact holes in the second direction.
In some embodiments, the distance between the gates of any two adjacent field effect transistors in different transistor cells is greater than the third preset distance.
In a second aspect, an embodiment of the present application provides a field effect transistor, including at least: a channel region and a gate overlying the channel region;
the first end of the grid electrode is provided with an epitaxial region, the size of the epitaxial region is larger than that of an extension region corresponding to the second end of the grid electrode, wherein the first end and the second end are two opposite ends of the grid electrode respectively;
the epitaxial region is used for being connected with a contact hole, a metal wire is filled in the contact hole, and the metal wire is used for providing voltage for the grid so as to conduct the field effect transistor.
In a third aspect, an embodiment of the present application provides a three-dimensional memory, including at least: the memory cell array and the page buffer provided in the above embodiments;
the page buffer is coupled with the memory cell array through a bit line, and the page buffer is used for transmitting data to the memory cell array or reading data from the memory cell array.
The page buffer, the field effect transistor and the three-dimensional memory provided by the embodiment of the application are characterized in that the page buffer comprises at least one transistor unit, each transistor unit comprises at least one field effect transistor, each field effect transistor at least comprises a channel region and a grid covering the channel region, an extension region is arranged at the first end of the grid and can be used for being connected with a contact hole, and a metal wire in the contact hole can provide voltage for the grid to conduct the field effect transistor, so that the contact hole can be received through the extension region when the distance between the channel length of the field effect transistor and each transistor unit is small enough.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
FIG. 1A is a schematic diagram illustrating an alternative planar structure of a page register of the related art;
FIG. 1B is a schematic diagram of a saddle-shaped FinFET in accordance with the related art;
FIG. 1C is a cross-sectional view of a saddle shaped FinFET in a first direction according to the related art;
FIG. 1D is a cross-sectional view of a saddle shaped FinFET in a second orientation in accordance with the related art;
FIG. 1E is a schematic diagram illustrating an alternative planar structure of a page register formed by planar transistors in the related art;
FIG. 1F is a schematic diagram of an alternative layout of a page register formed by saddle-shaped FinFETs in the prior art;
fig. 2A is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 2B is a schematic diagram illustrating an alternative structure of a page buffer according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an alternative structure of a page buffer according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a field effect transistor according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, specific technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
In the following description, suffixes such as "module" or "unit" used to denote elements are used only for facilitating the explanation of the present application, and have no specific meaning in themselves. Thus, "module" or "unit" may be used mixedly.
In 3D NAND technology, as the number of stacked layers increases, the size of array wafers on the same volume of chips decreases, and thus the size of driver (CMOS) wafers is also required to decrease. PB occupies a large area of the chip in the entire chip, and therefore, reduction in the PB size greatly contributes to reduction in the entire chip size.
The PB circuit in the related art is composed of an array structure of a plurality of planar low voltage N-type field effect transistors (LVNMO) or low voltage P-type field effect transistors (LVPMO). As shown in fig. 1A, which is an alternative plan view of a page buffer in the related art, it can be seen that each field effect transistor in PB includes an Active Area 101 (AA), a channel Area, a gate 102, and a contact hole 103. The parameters in fig. 1A represent the following meanings, respectively: the parameter a represents the spacing of the active regions of the two field effect transistors; the parameter d represents the spacing between the gates of two field effect transistors; the parameter c represents the distance between the gate and the overlap region of the gate and the active region; the parameter p represents the width of one transistor cell; the parameter L represents the channel length of the field effect transistor; the parameter W represents the channel width of the field effect transistor; the parameters e1 and e2 represent the distance between the contact hole and the gate, and e1 is equal to e 2; the parameter f represents the size of the contact hole; the parameter m represents the distance between the overlapping region of the active region and the contact hole of the field effect transistor and the active region.
Due to the special device structure of the saddle-shaped fin field effect transistor, the channel length can be greatly reduced under the condition that the leakage level is almost unchanged, and therefore the saddle-shaped fin field effect transistor can be used for reducing the whole size of PB. Referring to fig. 1B, which is a schematic diagram of a saddle-shaped finfet in the related art, it can be seen that the saddle-shaped finfet includes: Source/Drain 101'(Source/Drain, S/D), Gate (Gate, G)102', silicon substrate 104, Gate insulating layer 105, and side Gate 106. The gate of the saddle-shaped finfet in the related art is extended into the channel region, unlike the structure of a conventional planar fet. Fig. 1C is a cross-sectional view of a saddle-shaped finfet in the related art in a first direction, the saddle-shaped finfet having a channel length Lg, a junction depth of S/D Xj, and a gate with a localized doped region 107 in contact with the channel region, as shown in fig. 1C. FIG. 1D is a cross-sectional view of a saddle-shaped FinFET in a second direction, as shown in FIG. 1D, where Lov _ Xj is the depth of the gate and silicon substrate overlap, and Lov _ Xj is equal to the total channel depth Lc minus the junction depth of S/D, Xj.
As shown in fig. 1E, which is an alternative planar structure of the page buffer formed by the planar transistor in the related art, it can be seen that the planar field effect transistor may fall on the gate above the channel region due to the larger size of the channel length Lg. However, as the channel length of the saddle-shaped finfet is reduced, for example, to 0.1um, the contact hole cannot fall on the gate above the channel region. As shown in fig. 1F, which is an alternative plan view of a page register formed by saddle-shaped finfet in the related art, it can be seen that as the channel length Lg is continuously reduced to 0.1um, the contact hole 103 cannot fall on the gate above the channel region, and further, due to the PB pitch limitation, there is no extra space for receiving contact holes on the gates extending out of the two ends of the channel region, for example, the regions a and B in fig. 1F cannot be used for receiving contact holes.
In view of the above problems in the related art, embodiments of the present application provide a page buffer capable of receiving a contact hole on a gate electrode when a channel length of a saddle-shaped finfet and a pitch of PB are sufficiently small.
An embodiment of the present application provides a page buffer, where the page buffer is applied to a three-dimensional memory, and fig. 2A is a schematic structural diagram of the three-dimensional memory provided in the embodiment of the present application, and as shown in fig. 2A, the three-dimensional memory 200 includes: the memory device comprises a memory cell array 201, a controller 202 and a page buffer 203, wherein the controller 202 and the page buffer 203 are located in peripheral circuits of the three-dimensional memory, the page buffer 203 is coupled with the memory cell array 201 through bit lines, and the page buffer 203 is used for transmitting data to the memory cell array 201 or reading data from the memory cell array 201. Fig. 2B is an alternative structural diagram of a page buffer according to an embodiment of the present disclosure, and as shown in fig. 2B, the page buffer 203 includes at least one transistor unit, and each transistor unit in the page buffer 203 is coupled to a memory cell array 201 of a three-dimensional memory through a Bit Line (BL). During a write operation, the controller 202 transmits data, commands, and addresses to the memory cell array 201, and during a read operation, the controller 202 transmits commands and addresses to the memory cell array 201 and reads data from the memory cell array 201. In the embodiment of the present application, the page buffer 203 includes a transistor unit 2031, a transistor unit 2032, and a transistor unit 2033.
Each transistor unit comprises at least one field effect transistor, and each field effect transistor at least comprises a channel region 1 and a grid electrode covering the channel region.
Here, the field effect transistor may be an N-type field effect transistor or a P-type field effect transistor, and in the embodiment of the present application, the field effect transistor is a saddle-shaped fin-type field effect transistor.
In some embodiments, each of the field effect transistors further comprises an active region, i.e. a source region and a drain region.
The first end of the grid electrode is provided with an extension region 2-1, the size of the extension region 2-1 is larger than that of an extension region 2-2 corresponding to the second end of the grid electrode, and the first end and the second end are two opposite ends of the grid electrode respectively.
It should be noted that the extension region is a region where the second end of the gate extends out of the channel region, and the size of the extension region includes but is not limited to at least one of the following: a first length of the extension region in the first direction, a second length of the extension region in the second direction, and a first cross-sectional area of the extension region in a plane formed by the first direction and the second direction. The first direction is perpendicular to the second direction, and a plane formed by the first direction and the second direction is perpendicular to the extending direction of the contact hole. In an embodiment of the present application, the first direction is an X-axis direction, and the second direction is a Y-axis direction.
The epitaxial region is a region in which the first end of the grid electrode extends out of the channel region; the epitaxial region is formed by epitaxially growing the gate through an epitaxial process, and the region having the same crystal orientation as the gate is formed. The size of the epitaxial region includes, but is not limited to, one of: a third length of the epitaxial region in the first direction, a fourth length of the epitaxial region in the second direction, and a second cross-sectional area of the epitaxial region in a plane formed by the first direction and the second direction.
Here, the size of the epitaxial region is larger than the size of the extension region corresponding to the second end of the gate, which includes the following two cases: one, the third length is greater than the first length, and the fourth length is greater than the second length; secondly, the second cross-sectional area is larger than the first cross-sectional area.
The epitaxial region is used for being connected with a contact hole, a metal wire is filled in the contact hole, and the metal wire is used for providing voltage for the grid so as to conduct the field effect transistor. Here, the metal wire includes a metal tungsten wire.
It is noted that the overlapping region of the contact hole and the epitaxial region is located at the center of the epitaxial region, such as the contact hole 3-1 in fig. 2B is located at the center of the epitaxial region 2-1.
In the embodiment of the present application, two adjacent epitaxial regions in the same transistor unit are located on different sides of a gate in the transistor unit, and two adjacent epitaxial regions in different transistor units are located at the same position relative to the gate in the transistor unit where each epitaxial region is located. Here, the field effect transistors located adjacent to each other in different transistor units refer to adjacent field effect transistors located in the X-axis direction.
With continued reference to fig. 2B, it can be seen that the two adjacent epitaxial regions 2-1 and 2'-1 in transistor cell 2031 are on different sides of the gate in transistor cell 2031, and the two adjacent epitaxial regions 5-1 and 5' -1 in transistor cell 2032 are also on different sides of the gate in transistor cell 2032.
Two adjacent epitaxial regions 2-1 and 5-1 located in different transistor unit 2031 and transistor unit 2032, wherein the position of epitaxial region 2-1 relative to the gate in transistor unit 2031 is the same as the position of epitaxial region 5-1 relative to the gate in transistor unit 2032, and both are located on the right side of the gate as shown in fig. 2B; two adjacent epitaxial regions 2'-1 and 5' -1 located in different transistor unit 2031 and transistor unit 2032, wherein the position of the epitaxial region 2'-1 relative to the gate in the transistor unit 2031 is the same as the position of the epitaxial region 5' -1 relative to the gate in the transistor unit 2032, and both are located on the left side of the gate as shown in fig. 2B.
The page buffer provided by the embodiment of the application comprises at least one transistor unit, each transistor unit comprises at least one field effect transistor, each field effect transistor at least comprises a channel region and a grid electrode covering the channel region, and as the first end of the grid electrode is provided with an extension region which can be used for connection, a metal wire in a contact hole can supply voltage to the grid electrode to conduct the field effect transistor, so that the contact hole can be received through the extension region when the channel length of the field effect transistor and the distance between each transistor unit are small enough.
In some embodiments, since the overlapping region of the contact hole and the epitaxial region is located at the center of the epitaxial region, the size of the epitaxial region is larger than that of the contact hole.
In some embodiments, the contact holes may be circular holes; the diameter of the circular hole is smaller than the third length and smaller than the fourth length, and a difference between the diameter of the circular hole and the channel length is smaller than a first preset difference.
The first preset difference is a positive integer greater than or equal to 0, and here, the magnitude of the first preset difference is not limited. Since a difference between the diameter of the circular hole and the channel length is less than a first preset difference, the circular hole cannot be formed in the gate electrode located above the channel region.
In some embodiments, the contact holes comprise polygonal holes, such as quadrilateral holes or hexagonal holes. The length of the polygonal hole in the first direction is less than the third length, and the length of the polygonal hole in the second direction is less than the fourth length. The difference between the length of the polygonal hole in the second direction and the channel length is less than a second preset difference.
The second preset difference is a positive integer greater than or equal to 0, and here, the magnitude of the second preset difference is not limited. Since the difference between the diameter of the polygonal hole and the channel length is smaller than a second preset difference, the polygonal hole cannot be formed in the gate electrode located above the channel region.
In the embodiment of the application, the shapes of two adjacent contact holes in the same transistor unit are the same or different.
In some embodiments, each of the field effect transistors further includes a source region and a drain region located at two sides of the channel region, and the source region and the drain region are respectively connected to one of the contact holes; wherein the contact holes on the source region, the drain region and the epitaxial region are staggered.
With continued reference to fig. 2B, the field effect transistor 2031-1 further comprises a source region 4-1 and a drain region 4-2 located at two sides of the channel region, the contact hole 3-2 and the contact hole 3-3 are respectively connected to the source region 4-1 and the drain region 4-2, wherein the contact holes 3-1, the contact holes 3-2 and the contact holes 3-3 located on the source region, the drain region and the epitaxial region are arranged in a staggered manner.
In the embodiment of the application, a first preset distance or a second preset distance is arranged between two adjacent contact holes in the same field effect transistor.
Here, the first preset distance includes a distance of two contact holes in the first direction and a distance of two contact holes in the second direction; the second preset distance includes a distance between the two contact holes in the first direction and a distance between the two contact holes in the second direction.
With continued reference to fig. 2B, the adjacent contact holes 3-1 and 3-2 in the fet 2031-1 have a first predetermined distance therebetween, where the first predetermined distance includes the distance between the contact holes 3-1 and 3-2 in the X-axis direction and the distance between the contact holes 3-1 and 3-2 in the Y-axis direction. A second predetermined distance is provided between adjacent contact holes 3-1 and 3-3 in the field effect transistor 2031-1, and the second predetermined distance includes a distance between the contact hole 3-1 and 3-3 in the X-axis direction and a distance between the contact hole 3-1 and 3-3 in the Y-axis direction. In the embodiment of the present application, neither the relative size nor the absolute size of the first preset distance nor the second preset distance is limited.
In some embodiments, in different transistor units, the distance between the gates of two adjacent field effect transistors located on the same straight line is greater than the third preset distance.
The third predetermined distance represents a distance between adjacent transistor cells, and in some embodiments, the distance between adjacent transistor cells is a fixed value, and the size of the third predetermined distance is not limited herein.
According to the page buffer provided by the embodiment of the application, as the size of the epitaxial region of the first end of the grid electrode is larger than that of the contact hole, the contact hole can fall on the epitaxial region, and then voltage can be supplied to the grid electrode through the metal wire in the contact hole, so that the field effect transistor is turned on.
An embodiment of the present application provides a page buffer, as shown in fig. 3, which is an optional structural schematic diagram of the page buffer provided in the embodiment of the present application, where the page buffer 30 includes: two transistor units 301 and 302, wherein the transistor unit 301 comprises a field effect transistor 301-1 and a field effect transistor 301-2, and the transistor unit 302 comprises a field effect transistor 302-1 and a field effect transistor 302-2, and in the embodiment of the present application, the field effect transistor comprises a saddle-shaped fin field effect transistor.
Each of the field effect transistors includes: an active region, a channel region and a gate electrode covering the channel region, as shown in fig. 3, the field effect transistor 301-1 includes: an active region 5, a channel region 6 and a gate 7 covering the channel region.
Each transistor unit is provided with an epitaxial region and an extension region, wherein the extension region is a region of the second end of the grid electrode extending out of the channel region; the epitaxial region is a region in which a first end of the gate extends out of the channel region, and the first end and the second end are two opposite ends of the gate respectively.
With continued reference to fig. 3, the field effect transistor 301-1 includes an extension region a1 and an epitaxial region a2, and the field effect transistor 301-2 includes an extension region A3 and an epitaxial region a 4; the field effect transistor 302-1 includes an extension region B1 and an epitaxial region B2, and the field effect transistor 302-2 includes an extension region B3 and an epitaxial region B4.
The epitaxial region is used for being connected with a contact hole, a metal wire is filled in the contact hole, and the metal wire is used for supplying voltage to the grid so as to conduct the field effect transistor. Wherein two adjacent epitaxial regions in the same transistor cell are located on different sides of a gate in the transistor cell; two adjacent epitaxial regions in different transistor units have the same position relative to the gate of the transistor unit in which each epitaxial region is located.
With continued reference to FIG. 3, contact holes C1-1, C2-1, C3-1 and C4-1 are connected to the epitaxial region A2, the epitaxial region A4, the epitaxial region B2 and the epitaxial region B4, respectively. The two adjacent epitaxial regions a2 and a4 in the transistor cell 301 are located on different sides of the gate in the transistor cell 301, and the two adjacent epitaxial regions B2 and B4 in the transistor cell 302 are located on different sides of the gate in the transistor cell 302. Two epitaxial regions a2 and B2 located in different transistor cells 301 and 302 and adjacent to each other, wherein the position of the epitaxial region a2 relative to the gate in the transistor cell 301 is the same as the position of the epitaxial region B2 relative to the gate in the transistor cell 302; two epitaxial regions a4 and B4 located in different transistor cells 301 and 302 and adjacent to each other, wherein the position of epitaxial region a4 with respect to the gate in transistor cell 301 is the same as the position of epitaxial region B4 with respect to the gate in transistor cell 302.
In some embodiments, the active region includes a source region and a drain region on both sides of the channel region, and the source region and the drain region are respectively connected to one of the contact holes, such as contact hole C1-2 and contact hole C1-3 shown in fig. 3.
Some dimensional parameters in the page buffer are given below by way of example, as shown in fig. 3, the channel length Lg of the field effect transistor 301-1 is 0.1um, and the distance d1 between the active regions is 0.204 um; the d2 distance between the gates of different transistor cells is 0.1um (corresponding to the third predetermined distance in the above embodiment); the distance d3 between adjacent gates in the same transistor cell is 0.23 um; the dimension d4 of the extension area in the X-axis direction is 0.07 um; the dimension d5 of the extension area in the Y-axis direction is 0.32 um; the dimension d6 of the epitaxial region in the X-axis direction is 0.094 um; the dimension d7 of the epitaxial region in the Y-axis direction is 0.1 um; the distance d8 between the active regions of adjacent transistor cells is 0.264 um; the distance d9 between the same ends of the gates of the adjacent field effect transistors in the same transistor unit is 0.12 um; CT Critical Dimension (CD) 0.05 x 0.09 um; the size of the overlapping area of the epitaxial region and the contact hole C1-1 in the X-axis direction is 0.044 um; the size of the overlapping region of the epitaxial region and the contact hole C1-1 in the Y-axis direction is 0.115 um. Here, since the size of the overlapping region of the epitaxial region and the contact hole C1-1 in the Y-axis direction is larger than the channel length Lg, the contact hole cannot fall on the overlapping region of the gate and the channel region.
In the PB designed based on the saddle-shaped fin field effect transistor according to the embodiment of the present application, after the channel length is reduced to-0.1 um, asymmetric design is performed in the gate P2(Poly) epitaxial region (Extension), so that the gate has Extension regions with different sizes on both sides of the channel region. One end of the extension region with larger size of the grid is used for bearing CT, thereby realizing the pressurization of the grid. In the same transistor cell, the extension regions having a larger size are staggered so that the space between the page buffers is sufficient. At the same time, the CTs on AA and P2 are staggered to meet the CT pitch requirement.
The page buffer provided by the embodiment of the application can realize that CT falls in the saddle-shaped fin field effect transistor with the channel length of 0.1um, so that the saddle-shaped fin field effect transistor is really available, and the page buffer provided by the embodiment of the application can meet the requirement of process allowance.
In addition, an embodiment of the present application further provides a field effect transistor, and fig. 4 is a schematic structural diagram of the field effect transistor provided in the embodiment of the present application, and as shown in fig. 4, the field effect transistor at least includes a channel region 401 and a gate 402 covering the channel region.
The first end of the gate 402 has an extension region 402-1, and the extension region 402-1 has a size larger than that of an extension region 402-2 corresponding to the second end of the gate 402, where the first end and the second end are two opposite ends of the gate, respectively.
In some embodiments, the epitaxial region 402-1 is used to connect to a contact hole 403-1, and the contact hole 403-1 is filled with a metal line for providing a voltage to the gate 402 to turn on the fet 40. Here, the metal wire includes a metal tungsten wire.
In some embodiments, the field effect transistor further comprises: active regions, i.e., source region 404 and drain region 405, which connect contact holes 403-2 and 403-3, respectively. In the embodiment of the present application, the contact holes 403-2, the contact holes 403-3, and the contact holes 403-3 located on the source region 404, the drain region 405, and the epitaxial region 402-1 are staggered.
It should be noted that the field effect transistor provided in the embodiments of the present application has the same structure as the field effect transistor in each transistor unit in the page buffer in the above embodiments, and for technical features that are not disclosed in detail in the embodiments of the present application, please refer to the above embodiments for understanding.
According to the field effect transistor provided by the embodiment of the application, the grid electrode is provided with the epitaxial region, the epitaxial region can be used for being connected with the contact hole, and the metal wire in the contact hole can provide voltage for the grid electrode so as to conduct the field effect transistor, so that various functions of the field effect transistor can be realized when the channel length of the field effect transistor is small enough.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (13)

1. A page buffer applied to a three-dimensional memory, the page buffer comprising: at least one transistor cell;
each transistor unit comprises at least one field effect transistor, and each field effect transistor at least comprises a channel region and a grid electrode covering the channel region;
the first end of the grid electrode is provided with an epitaxial region, the size of the epitaxial region is larger than that of an extension region corresponding to the second end of the grid electrode, wherein the first end and the second end are two opposite ends of the grid electrode respectively;
the epitaxial region is used for being connected with a contact hole, a metal wire is filled in the contact hole, and the metal wire is used for providing voltage for the grid so as to conduct the field effect transistor.
2. The page buffer of claim 1, wherein two adjacent epitaxial regions in the same transistor cell are located on different sides of a gate in the transistor cell; two adjacent epitaxial regions in different transistor units have the same position relative to the gate of the transistor unit in which each epitaxial region is located.
3. The page buffer of claim 1, wherein the page buffer is located in a peripheral circuit of the three-dimensional memory, each of the transistor cells of the page buffer being coupled to a memory cell array of the three-dimensional memory by a bit line;
the page buffer is used for writing data into the memory cell array or reading data in the memory cell array through the bit line when the field effect transistor is conducted.
4. The page buffer of claim 1, wherein the field effect transistors comprise saddle shaped fin field effect transistors.
5. The page buffer of claim 1, wherein the extension region is a region where the second end of the gate electrode extends out of the channel region, and a size of the extension region includes a first length of the extension region in a first direction and a second length of the extension region in a second direction;
the epitaxial region is a region in which the first end of the gate extends out of the channel region, and the size of the epitaxial region comprises a third length of the epitaxial region in the first direction and a fourth length of the epitaxial region in the second direction; the first direction is perpendicular to the second direction, and a plane formed by the first direction and the second direction is perpendicular to the extending direction of the contact hole;
wherein the third length is greater than the first length and the fourth length is greater than the second length.
6. The page buffer of claim 1, wherein an overlapping region of the contact hole and the epitaxial region is located at a center of the epitaxial region.
7. The page buffer of claim 5, wherein the contact hole comprises a circular hole;
the diameter of the circular hole is smaller than the third length and smaller than the fourth length, and a difference between the diameter of the circular hole and the channel length is smaller than a first preset difference.
8. The page buffer of claim 5, wherein the contact hole comprises a polygonal hole;
the length of the polygonal hole in the first direction is less than the third length, and the length of the polygonal hole in the second direction is less than the fourth length;
the difference between the length of the polygonal hole in the second direction and the channel length is less than a second preset difference.
9. The page buffer of claim 1, wherein each of the field effect transistors further comprises a source region and a drain region located at both sides of the channel region; the source region and the drain region are respectively connected with one contact hole;
wherein the contact holes on the source region, the drain region and the epitaxial region are staggered.
10. The page buffer of claim 9, wherein a first predetermined distance or a second predetermined distance is provided between adjacent two of the contact holes in the same field effect transistor;
wherein the first preset distance comprises a distance between two contact holes in the first direction and a distance between two contact holes in the second direction;
the second preset distance includes a distance between the two contact holes in the first direction and a distance between the two contact holes in the second direction.
11. The page buffer of claim 1, wherein a distance between gates of any adjacent two field effect transistors in different transistor units is greater than a third preset distance.
12. A field effect transistor, comprising at least: a channel region and a gate overlying the channel region;
the first end of the grid electrode is provided with an epitaxial region, the size of the epitaxial region is larger than that of an extension region corresponding to the second end of the grid electrode, wherein the first end and the second end are two opposite ends of the grid electrode respectively;
the epitaxial region is used for being connected with a contact hole, a metal wire is filled in the contact hole, and the metal wire is used for providing voltage for the grid so as to conduct the field effect transistor.
13. A three-dimensional memory, comprising at least: a page buffer provided in any one of the above claims 1 to 11 and a memory cell array;
the page buffer is coupled with the memory cell array through a bit line, and the page buffer is used for transmitting data to the memory cell array or reading data from the memory cell array.
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