CN112864086A - Conductive interconnection structure and preparation method thereof - Google Patents
Conductive interconnection structure and preparation method thereof Download PDFInfo
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- CN112864086A CN112864086A CN201911190093.8A CN201911190093A CN112864086A CN 112864086 A CN112864086 A CN 112864086A CN 201911190093 A CN201911190093 A CN 201911190093A CN 112864086 A CN112864086 A CN 112864086A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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Abstract
The invention provides a conductive interconnection structure and a preparation method thereof, comprising the following steps: providing a substrate; covering a conductive layer on the substrate; the conductive layer is patterned to form a plurality of first conductive interconnection lines arranged at intervals, and isolation grooves are formed between every two adjacent first conductive interconnection lines; growing a low-K dielectric layer on the inner wall of the isolation groove, wherein the low-K dielectric layer extends along the inner wall of the isolation groove and forms a groove; and forming a sealing layer which covers the first conductive interconnection lines and closes the grooves to form closed air gaps between the first conductive interconnection lines. According to the invention, the low-K dielectric layer is grown between the first conductive interconnection lines, and the air gap is formed by the groove formed by the low-K dielectric layer and the sealing layer, so that the time constant RC of the first conductive interconnection lines is reduced, the interconnection speed is improved, the stability and reliability of the conductive interconnection structure are improved, and the preparation process is simplified.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a conductive interconnection structure and a preparation method thereof.
Background
With the increasing of the integrated circuit process, the critical dimension of the semiconductor process is continuously reduced, and the cross-sectional area and the inter-line distance of the conductive interconnection line on the chip are also continuously reduced, so that the resistance and the parasitic capacitance of the conductive interconnection line are increased, which leads to the great increase of the time constant RC of the conductive interconnection line. The time constant RC of conductive interconnect lines accounts for an increasing proportion of the total delay of an integrated circuit, becoming a major factor limiting the speed of the interconnect.
According to the calculation method of the time constant RC of the conductive interconnection line, besides the metal material with low resistivity and electric mobility is selected, the low dielectric constant (low K) insulating material can be used as an interlayer medium to effectively reduce the time constant RC, so that the parameters such as the response speed of a device are improved. This is because the low dielectric constant insulating material reduces the parasitic capacitance between the conductive layers, so that the transmission speed of signals between the semiconductor devices can be further increased.
However, the above improvements are not satisfactory.
Disclosure of Invention
The invention aims to solve the technical problem of providing a conductive interconnection structure and a preparation method thereof.
In order to solve the above problems, the present invention provides a method for manufacturing a conductive interconnection structure, comprising the steps of: providing a substrate; covering a conductive layer on the substrate; patterning the conductive layer to form a plurality of first conductive interconnection lines arranged at intervals, wherein an isolation groove is formed between every two adjacent first conductive interconnection lines; growing a low-K dielectric layer on the inner wall of the isolation groove, wherein the low-K dielectric layer extends along the inner wall of the isolation groove and forms a groove; and forming a sealing layer which covers the first conductive interconnection lines and closes the grooves to form a closed air gap between the first conductive interconnection lines.
Furthermore, second conductive interconnection lines are arranged in the substrate at intervals, the second conductive interconnection lines are isolated by insulating layers, the first conductive interconnection lines are arranged corresponding to the second conductive interconnection lines and are electrically connected with the second conductive interconnection lines, and after the step of patterning the conductive layers, the insulating layers are exposed in the isolation grooves.
Further, an orthographic projection of the first conductive interconnection line on the substrate covers an orthographic projection of the second conductive interconnection line on the substrate.
Further, the preparation method also comprises the following steps: after the step of patterning the conductive layer, removing the insulating layer exposed to the isolation trench, and forming an extension trench in the substrate; in the step of growing a low-K dielectric layer on the inner wall of the isolation trench, the low-K dielectric layer is grown on the inner walls of the isolation trench and the extension trench, and the low-K dielectric layer extends along the inner walls of the isolation trench and the extension trench and forms the groove.
Further, the side face of the insulating layer serves as an inner wall of the extension trench.
Further, the step of patterning the conductive layer further comprises the steps of: forming a blocking layer and a light resistance layer on the conducting layer; patterning the photoresist layer to form a pattern window; and etching the barrier layer and the conductive layer along the pattern window by taking the photoresist layer as a mask to form a patterned conductive layer.
Further, the barrier layer comprises a protective layer and an anti-reflection layer which are sequentially arranged, and the step of removing the light resistance layer and the anti-reflection layer is further included after the step of etching the barrier layer and the conductive layer.
Furthermore, the width range of the groove is 5-40 nanometers.
Further, the step of growing a low-K dielectric layer on the inner wall of the isolation trench further comprises: growing the low-K dielectric layer on the upper surface of the first conductive interconnection line and the inner wall of the isolation groove; before the step of forming the sealing layer, the method further comprises the following steps: and removing the surface of the first conductive interconnection line and the low-K dielectric layer at the bottom of the groove.
The invention also provides a conductive interconnection structure prepared by the preparation method, and the conductive interconnection structure comprises a substrate, a conductive interconnection layer and a sealing layer which are sequentially arranged, wherein the conductive interconnection layer is provided with a plurality of first conductive interconnection lines arranged at intervals, a low-K dielectric layer is arranged between the adjacent first conductive interconnection lines, the low-K dielectric layer extends along the side wall of the first conductive interconnection line and forms a groove, and the sealing layer covers the first conductive interconnection layer and seals the groove so as to form a closed air gap between the first conductive interconnection lines.
Further, the interval is provided with the electrically conductive interconnect of second in the base, be kept apart by the insulating layer between the electrically conductive interconnect of second, first electrically conductive interconnect corresponds the electrically conductive interconnect setting of second, and both electricity are connected, the insulating layer has the extension slot, the low K dielectric layer is followed first electrically conductive interconnect lateral wall and extend the slot lateral wall and extend, and form the recess.
The invention has the advantages that the low-K dielectric layer grows between the first conductive interconnection lines, the groove formed by the low-K dielectric layer and the sealing layer form the air gap together, the low-K dielectric layer and the air gap are used as the isolation structure of the first conductive interconnection lines together, the time constant RC of the first conductive interconnection lines is reduced, the interconnection speed is improved, the stability and the reliability of the conductive interconnection structure are improved, and the preparation process is simplified.
Drawings
FIG. 1 is a schematic step diagram of a first embodiment of a method of making a conductive interconnect structure of the present invention;
FIGS. 2A-2F are process flow diagrams of a first embodiment of a method of fabricating a conductive interconnect structure of the present invention;
FIGS. 3A-3D are process flow diagrams of one embodiment of patterning the conductive layer 210;
FIG. 4 is a schematic step diagram of a second embodiment of a method of fabricating a conductive interconnect structure of the present invention;
FIGS. 5A-5G are process flow diagrams of a second embodiment of a method of fabricating a conductive interconnect structure of the present invention;
FIG. 6 is a schematic structural diagram of a first embodiment of a conductive interconnect structure of the present invention;
fig. 7 is a schematic structural diagram of a second embodiment of the conductive interconnect structure of the present invention.
Detailed Description
The following describes in detail a specific embodiment of the conductive interconnect structure and the method for fabricating the same according to the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic step diagram of a first embodiment of a method of making a conductive interconnect structure of the present invention. Referring to fig. 1, the method for fabricating the conductive interconnect structure of the present invention includes the following steps: step S10, providing a substrate; step S11, covering a conductive layer on the substrate; step S12, the conducting layer is patterned to form a plurality of first conducting interconnecting lines arranged at intervals, and isolation grooves are formed between the adjacent first conducting interconnecting lines; step S13, growing a low-K dielectric layer on the inner wall of the isolation trench, wherein the low-K dielectric layer extends along the inner wall of the isolation trench and forms a groove; step S14, forming a sealing layer covering the first conductive interconnection lines and closing the grooves to form a closed air gap between the first conductive interconnection lines.
Fig. 2A to 2F are process flow diagrams of a first embodiment of a method for fabricating a conductive interconnect structure of the present invention.
In step S10 and fig. 2A, a substrate 200 is provided.
The substrate 200 includes, but is not limited to, a Silicon crystal or germanium crystal, a Silicon On Insulator (SOI) structure or an epitaxial layer On Silicon structure, a compound semiconductor (e.g., Silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof).
Referring to step S11 and fig. 2B, a conductive layer 210 is formed on the substrate 200.
The conductive layer 210 covers the upper surface of the substrate 200. The conductive layer 210 includes, but is not limited to, a metal layer, such as metallic aluminum or metallic copper. In this step, the conductive layer 210 may be formed by a Chemical Vapor Deposition (CVD) method. In other embodiments of the present invention, the conductive layer 210 may be formed by other methods.
Referring to step S12 and fig. 2C, the conductive layer 210 is patterned to form a plurality of first conductive interconnection lines 211 arranged at intervals, and isolation trenches 212 are formed between adjacent first conductive interconnection lines 211.
In this step, the first conductive interconnection lines 211 are formed by patterning the conductive layer 210 such that the conductive layer 210 is spaced apart, the first conductive interconnection lines 211 not being connected to each other.
Fig. 3A-3D are process flow diagrams of one embodiment of patterning the conductive layer 210. In this embodiment, the method for patterning the conductive layer 210 includes the following steps:
referring to fig. 3A, a barrier layer 300 and a photoresist layer 310 are formed on the conductive layer 210 based on the structure shown in fig. 2B. In the present embodiment, the barrier layer 300 includes a protective layer 301 and an anti-reflective layer 302. The protective layer 301 covers the upper surface of the conductive layer 210, and the anti-reflection layer 302 covers the upper surface of the protective layer 301. The anti-reflective layer 302 may be used as a bottom anti-reflective layer for a subsequent photolithography process. Wherein the protection layer 301 includes, but is not limited to, a titanium nitride layer.
Referring to fig. 3B, the photoresist layer 310 is patterned to form a pattern window 311. The pattern window 311 exposes the anti-reflection layer 302. In this step, the photoresist layer 310 may be patterned by photolithography and etching.
Referring to fig. 3C, the photoresist layer 310 is used as a mask to etch the barrier layer 300 and the conductive layer 210 along the pattern window 311, so as to form a patterned conductive layer. In this step, the antireflection layer 302, the protection layer 301, and the conductive layer 210 are sequentially etched along the pattern window 311 by a dry etching method.
Referring to fig. 3D, the photoresist layer 300 and the anti-reflective layer 302 are removed to expose the passivation layer 301. After the step is completed, referring to fig. 3D and fig. 2C, the conductive layer 210 is covered with the protection layer 301.
While the above is described in terms of one embodiment of a patterned conductive layer, it is to be understood that other methods of patterning the conductive layer may be used.
Referring to step S13, fig. 2D and fig. 2E, a low-K dielectric layer 220 is grown on the inner wall of the isolation trench 212. The low-K dielectric layer 220 extends along the inner wall of the isolation trench 212 and forms a recess 221.
The low-K dielectric layer 220 is a low-K dielectric layer, for example, the material of the low-K dielectric layer 220 is selected from one or more of SiCOH, porous material, SiCO, and SiFO. In this embodiment, the low-K dielectric layer 220 is grown on the inner wall of the isolation trench 212 by chemical vapor deposition. The reaction time of the chemical vapor deposition can be controlled such that the low-K dielectric layer 220 grows along the sidewall of the isolation trench 212 but does not fill the isolation trench 212, and the region of the isolation trench 212 not filled by the low-K dielectric layer 220 is the recess 221. In addition, the thickness of the low-K dielectric layer 220 can be controlled by controlling the reaction time of the chemical vapor deposition so as to control the size of the groove 221, and the RC is effectively reduced and the response speed of the device is improved by matching the sizes of the low-K dielectric layer 220 and the groove 221.
Further, the width of the groove 221 is 5 to 40 nanometers. For example, the width of the groove 221 is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, and the like. Too large or too small a width of the groove 221 may affect the stability of the conductive interconnect structure.
In this step, the sidewall of the first conductive interconnection line 211 serves as an inner wall of the isolation trench 212, and the low-K dielectric layer 220 is grown along the sidewall of the first conductive interconnection line 211. That is, other materials are not additionally arranged between the first conductive interconnection lines 211, but only the low-K dielectric layer 220 is grown, so that the dielectric constant of the dielectric layer between the first conductive interconnection lines 211 is small, the time constant RC is effectively reduced, and the parameters such as the response speed of the device are improved.
When the low-K dielectric layer 220 is grown, the low-K dielectric layer 220 may not only grow on the inner wall of the isolation trench 212, but also grow on the upper surface of the first conductive interconnection line 211, as shown in fig. 2D, before performing step S14, a step of removing the low-K dielectric layer 220 on the surface of the first conductive interconnection line 211 is further included, as shown in fig. 2E, and the low-K dielectric layer 220 on the surface of the first conductive interconnection line 211 is removed. When the low-K dielectric layer 220 on the surface of the conductive interconnection line 211 is removed, the low-K dielectric layer 220 at the bottom of the groove 221 is also removed at the same time.
Further, in order to effectively control the width of the groove 221, in the step of removing the low-K dielectric layer 220 on the surface of the first conductive interconnection line 211, a portion of the low-K dielectric layer 220 grown on the inner wall of the isolation trench 212 may be simultaneously removed to obtain a suitable width of the groove 221.
Further, the groove 221 may be naturally formed by controlling the growth parameters of the low-K dielectric layer 220. The method has the advantages that the groove 221 is not manufactured by adopting the processes of etching and the like, the influence on the low-K dielectric layer 220 is small, the damage to the low-K dielectric layer 220 can be greatly reduced, and the stability and the reliability of the conductive interconnection structure are improved.
Referring to step S14 and fig. 2F, a sealing layer 230 is formed, wherein the sealing layer 230 covers the first conductive interconnection lines 211 and closes the grooves 221, so as to form a closed air gap 222 between the first conductive interconnection lines 211. Specifically, in the present embodiment, the sealing layer 230 covers the protective layer 301 and closes the groove 221.
The sealing layer 230 may be formed by chemical vapor deposition. The material of the sealing layer 230 includes but is not limited to SiC and SiO2SiON, SiCN. In the present embodiment, the sealing layer 230 can be formed rapidly by controlling the reaction parameters of the chemical vapor deposition, so that the sealing layer 230 is formed only above the groove 221 and does not extend into the groove 221, thereby preventing the sealing layer 230 from affecting the parameters such as the response speed of the device.
According to the preparation method of the conductive interconnection structure, the low-K dielectric layer 220 grows between the first conductive interconnection lines 211, the grooves 221 formed by the low-K dielectric layer 220 and the sealing layer 230 are utilized to form the air gaps together, the low-K dielectric layer 220 and the air gaps 222 are used as the isolation structure of the first conductive interconnection lines 211 together, the time constant RC of the first conductive interconnection lines is reduced, the interconnection speed is improved, meanwhile, the damage of the low-K dielectric layer 220 is greatly reduced, the stability and the reliability of the conductive interconnection structure are improved, and the preparation process is simplified.
The method for fabricating a conductive interconnect structure of the present invention also provides a second embodiment.
Fig. 4 is a schematic step diagram of a method for manufacturing a conductive interconnect structure according to a second embodiment of the present invention, referring to fig. 4, the method for manufacturing a conductive interconnect structure includes the following steps: step S40, providing a substrate, wherein second conductive interconnection lines are arranged at intervals in the substrate, and the second conductive interconnection lines are isolated by an insulating layer; step S41, covering a conductive layer on the substrate; step S42, patterning the conductive layer to form a plurality of first conductive interconnection lines arranged at intervals, wherein an isolation trench is formed between adjacent first conductive interconnection lines, the first conductive interconnection lines are arranged corresponding to the second conductive interconnection lines and electrically connected to the second conductive interconnection lines, and the insulating layer is exposed to the isolation trench; step S43, removing the insulation layer exposed to the isolation trench, and forming an extension trench in the substrate; step S44, growing a low-K dielectric layer on the inner walls of the isolation trench and the extension trench, wherein the low-K dielectric layer extends along the inner walls of the isolation trench and the extension trench and forms a groove; step S45, forming a sealing layer covering the first conductive interconnection lines and closing the grooves to form a closed air gap between the first conductive interconnection lines.
Fig. 5A-5G are process flow diagrams of a second embodiment of a method of fabricating a conductive interconnect structure of the present invention.
Referring to step S40 and fig. 5A, in step S40, a substrate 500 is provided, second conductive interconnection lines 501 are spaced in the substrate 500, and the second conductive interconnection lines 501 are isolated by an insulating layer 502.
In this step, the second conductive interconnection lines 501 are insulated from each other by the insulating layer 502. The upper surface of the second conductive interconnect 504 is exposed to the upper surface of the insulating layer 502. Further, in this embodiment, the upper surface of the second conductive interconnection line 501 is flush with the upper surface of the insulating layer 502.
In this embodiment, the substrate 500 further includes a supporting layer 503, and the second conductive interconnection line 501 and the insulating layer 502 are disposed on the supporting layer 503. The support layer 503 includes, but is not limited to, a semiconductor substrate layer, and the insulating layer 502 includes, but is not limited to, a silicon dioxide layer. The second conductive interconnect line 501 may be a metal line, for example, metal tungsten.
Referring to step S41 and fig. 5B, a conductive layer 510 is covered on the substrate 500.
In this embodiment, the conductive layer 510 covers the insulating layer 502 and the upper surface of the second conductive interconnection 501, and the conductive layer 510 is electrically connected to the second conductive interconnection 504. The conductive layer 510 includes, but is not limited to, a metal layer, such as metallic aluminum or metallic copper. In this step, the conductive layer 510 may be formed by Chemical Vapor Deposition (CVD). In other embodiments of the present invention, other methods may be used to form the conductive layer 510.
Referring to step S42 and fig. 5C, the conductive layer 510 is patterned to form a plurality of first conductive interconnection lines 511 disposed at intervals, an isolation trench 512 is disposed between adjacent first conductive interconnection lines 511, the first conductive interconnection lines 511 are disposed corresponding to the second conductive interconnection lines 501 and electrically connected to the second conductive interconnection lines, and the insulating layer 502 is exposed to the isolation trench 512.
In this embodiment, the method for patterning the conductive layer 510 is the same as the method for patterning the conductive layer 210 in the first embodiment, and is not repeated. It is noted that in the present embodiment, the protection layer 301, the anti-reflection layer 302 and the photoresist layer 310 are not removed, but remain to be used as a mask for the subsequent etching process.
Further, an orthographic projection a of the first conductive interconnection line 511 on the substrate 500 covers an orthographic projection B of the second conductive interconnection line 501 on the substrate 500. For example, an orthogonal projection a of the first conductive interconnection line 511 on the substrate 500 overlaps an orthogonal projection B of the second conductive interconnection line 501 on the substrate 500, i.e., the two areas are the same and completely correspond to each other; the orthographic projection B of the second conductive interconnection line 501 on the substrate 500 is positioned in the area of the orthographic projection A of the first conductive interconnection line 511 on the substrate 500, and the area of the orthographic projection A of the first conductive interconnection line 511 on the substrate 500 is larger than that of the orthographic projection B of the second conductive interconnection line 501 on the substrate 500. Fig. 5C shows that the orthographic projection B of the second conductive interconnection 501 on the substrate 500 is located in the region of the orthographic projection a of the first conductive interconnection 511 on the substrate 500.
Referring to step S43 and fig. 5D, the insulating layer 502 exposed to the isolation trench 512 is removed, and an extension trench 504 is formed in the substrate 500.
In this step, the insulating layer 502 is removed by a dry etching process using the photoresist layer 310 as a mask, so as to form the extension trench 504. In this embodiment, the extension trench 504 penetrates the insulating layer 502 and extends to the upper surface of the support layer 503. In other embodiments of the present invention, the extension trench 504 may not penetrate through the insulating layer 502, or the extension trench 504 may not penetrate through the insulating layer 502 but may extend into the supporting layer 503.
In this embodiment, the side surface of the insulating layer 502 serves as an inner wall of the extension trench 504. That is, the extension trench 504 does not expose the second conductive interconnection line 501.
After step S43, the method further includes the following steps: referring to fig. 5E, the photoresist layer 310 and the anti-reflection layer 302 are removed, and the protection layer 301 is remained on the surface of the first conductive interconnection lines 511.
Referring to step S44 and fig. 5F, a low-K dielectric layer 520 is grown on the inner walls of the isolation trench 512 and the extension trench 504, and the low-K dielectric layer 520 extends along the inner walls of the isolation trench 512 and the extension trench 504 to form a recess 521. In this embodiment, the forming method of the low-K dielectric layer 520 is the same as the forming method of the low-K dielectric layer 220 in the first embodiment, and is not described again.
In this step, the sidewall of the first conductive interconnection line 211 serves as the inner wall of the isolation trench 212, the sidewall of the insulating layer 502 serves as the inner wall of the extension trench 504, and the low-K dielectric layer 220 is grown along the sidewall of the first conductive interconnection line 211 and the sidewall of the insulating layer 502.
Referring to step S45 and fig. 5G, a sealing layer 530 is formed, and the sealing layer 530 covers the first conductive interconnection lines 511 and closes the recess 521, so as to form a closed air gap 522 between the first conductive interconnection lines 511.
Specifically, in the present embodiment, the sealing layer 530 covers the protective layer 301 and closes the groove 521. The formation method of the sealing layer 530 is the same as that of the sealing layer 230 in the first embodiment, and is not described again.
In the embodiment, in the method for manufacturing the conductive interconnection structure, the low-K dielectric layers 520 are grown between the first conductive interconnection lines 211 and between the second conductive interconnection lines 501, the air gaps 522 are formed by the grooves 521 formed by the low-K dielectric layers 520 and the sealing layer 530, and the low-K dielectric layers 520 and the air gaps 522 are used as the isolation structures of the first conductive interconnection lines 211 and the second conductive interconnection lines 501, so that the time constant RC of the first conductive interconnection lines is reduced, the interconnection speed is increased, the stability and reliability of the conductive interconnection structure are improved, and the manufacturing process is simplified.
The invention also provides a specific implementation mode of the conductive interconnection structure prepared by the preparation method.
Fig. 6 is a schematic structural diagram of a first embodiment of the conductive interconnect structure of the present invention. Referring to fig. 6, the conductive interconnection structure includes a substrate 600, a conductive interconnection layer 610 and a sealing layer 630 sequentially disposed.
The conductive interconnection layer 610 has a plurality of first conductive interconnection lines 611 arranged at intervals. A low-K dielectric layer 620 is provided between adjacent first conductive interconnect lines 611. The low-K dielectric layer 620 extends along the sidewalls of the first conductive interconnection lines 611 and forms a recess 621, and the sealing layer 630 covers the first conductive interconnection layers 611 and seals the recess 621, so as to form a closed air gap between the first conductive interconnection lines 611. The first conductive interconnection lines 611 are insulated and isolated by the low-K dielectric layer 620 and the air gap.
Fig. 7 is a schematic structural diagram of a second embodiment of the conductive interconnect structure of the present invention. Referring to fig. 7, in the present embodiment, the conductive interconnection structure includes a substrate 700, a conductive interconnection layer 710 and a sealing layer 730 sequentially disposed.
The substrate 700 includes a supporting layer 703, a second conductive interconnection line 701 and an insulating layer 702, the second conductive interconnection line 701 and the insulating layer 702 are disposed on the supporting layer 703, and the second conductive interconnection lines 701 are isolated by the insulating layer 702.
The conductive interconnect layer 710 covers the insulating layer 702 and the second conductive interconnect lines 701. The conductive interconnection layer 710 has a plurality of first conductive interconnection lines 711 disposed at intervals. Two such first conductive interconnect lines 711 are schematically depicted in the drawing. A low-K dielectric layer 720 is provided between adjacent first conductive interconnect lines 711 and between adjacent second conductive interconnect lines 701. The low-K dielectric layer 720 extends along the sidewalls of the first conductive interconnection lines 711 and the sidewalls of the insulating layer 702 to form a groove, and the sealing layer 730 covers the first conductive interconnection layers 711 and seals the groove 721 to form a closed air gap between the first conductive interconnection lines 711. The first conductive interconnection lines 711 and the second conductive interconnection lines 701 are insulated and isolated by the low-K dielectric layer 720 and the air gaps.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (11)
1. A method for preparing a conductive interconnection structure is characterized by comprising the following steps:
providing a substrate;
covering a conductive layer on the substrate;
patterning the conductive layer to form a plurality of first conductive interconnection lines arranged at intervals, wherein an isolation groove is formed between every two adjacent first conductive interconnection lines;
growing a low-K dielectric layer on the inner wall of the isolation groove, wherein the low-K dielectric layer extends along the inner wall of the isolation groove and forms a groove;
and forming a sealing layer which covers the first conductive interconnection lines and closes the grooves to form a closed air gap between the first conductive interconnection lines.
2. The method of claim 1, wherein second conductive interconnection lines are spaced apart from each other in the substrate, the second conductive interconnection lines are isolated by an insulating layer, the first conductive interconnection lines are disposed corresponding to the second conductive interconnection lines and electrically connected to each other, and the insulating layer is exposed to the isolation trench after the step of patterning the conductive layer.
3. The method of claim 2, wherein an orthographic projection of the first conductive interconnect line on the substrate covers an orthographic projection of the second conductive interconnect line on the substrate.
4. The method of manufacturing a conductive interconnect structure of claim 2, further comprising the steps of:
after the step of patterning the conductive layer, removing the insulating layer exposed to the isolation trench, and forming an extension trench in the substrate;
in the step of growing a low-K dielectric layer on the inner wall of the isolation trench, the low-K dielectric layer is grown on the inner walls of the isolation trench and the extension trench, and the low-K dielectric layer extends along the inner walls of the isolation trench and the extension trench and forms the groove.
5. The method of claim 4, wherein a side surface of the insulating layer serves as an inner wall of the extension trench.
6. The method of claim 1, wherein the step of patterning the conductive layer further comprises the steps of:
forming a blocking layer and a light resistance layer on the conducting layer;
patterning the photoresist layer to form a pattern window;
and etching the barrier layer and the conductive layer along the pattern window by taking the photoresist layer as a mask to form a patterned conductive layer.
7. The method as claimed in claim 6, wherein the barrier layer comprises a protective layer and an anti-reflection layer sequentially disposed, and further comprising removing the photoresist layer and the anti-reflection layer after the step of etching the barrier layer and the conductive layer.
8. The method of claim 1, wherein the width of the groove is in the range of 5-40 nm.
9. The method of claim 1, wherein the step of growing a low-K dielectric layer on the inner wall of the isolation trench further comprises:
growing the low-K dielectric layer on the upper surface of the first conductive interconnection line and the inner wall of the isolation groove;
before the step of forming the sealing layer, the method further comprises the following steps: and removing the surface of the first conductive interconnection line and the low-K dielectric layer at the bottom of the groove.
10. A conductive interconnection structure prepared by the preparation method according to any one of claims 1 to 9, wherein the conductive interconnection structure comprises a substrate, a conductive interconnection layer and a sealing layer which are sequentially arranged, the conductive interconnection layer is provided with a plurality of first conductive interconnection lines arranged at intervals, a low-K dielectric layer is arranged between adjacent first conductive interconnection lines, the low-K dielectric layer extends along the side walls of the first conductive interconnection lines and forms a groove, and the sealing layer covers the first conductive interconnection layer and closes the groove to form a closed air gap between the first conductive interconnection lines.
11. The conductive interconnect structure of claim 10, wherein second conductive interconnects are spaced apart from each other in the substrate, the second conductive interconnects are separated by an insulating layer, the first conductive interconnects are disposed corresponding to the second conductive interconnects and electrically connected to the second conductive interconnects, the insulating layer has an extended trench, and the low-K dielectric layer extends along sidewalls of the first conductive interconnects and sidewalls of the extended trench and forms the recess.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040094821A1 (en) * | 2002-11-15 | 2004-05-20 | Water Lur | Air gap for dual damascene applications |
| US20060051969A1 (en) * | 2004-08-10 | 2006-03-09 | Takahito Nakajima | Semiconductor device fabrication method |
| CN103151301A (en) * | 2013-02-25 | 2013-06-12 | 上海宏力半导体制造有限公司 | Semiconductor device forming method |
| CN208655631U (en) * | 2018-09-05 | 2019-03-26 | 长鑫存储技术有限公司 | Interconnection structure and semiconductor devices |
| CN208938968U (en) * | 2018-11-14 | 2019-06-04 | 长鑫存储技术有限公司 | A kind of semiconductor structure |
-
2019
- 2019-11-28 CN CN201911190093.8A patent/CN112864086A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040094821A1 (en) * | 2002-11-15 | 2004-05-20 | Water Lur | Air gap for dual damascene applications |
| US20060051969A1 (en) * | 2004-08-10 | 2006-03-09 | Takahito Nakajima | Semiconductor device fabrication method |
| CN103151301A (en) * | 2013-02-25 | 2013-06-12 | 上海宏力半导体制造有限公司 | Semiconductor device forming method |
| CN208655631U (en) * | 2018-09-05 | 2019-03-26 | 长鑫存储技术有限公司 | Interconnection structure and semiconductor devices |
| CN208938968U (en) * | 2018-11-14 | 2019-06-04 | 长鑫存储技术有限公司 | A kind of semiconductor structure |
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