CN112863574B

CN112863574B - Electronic device and operation method thereof

Info

Publication number: CN112863574B
Application number: CN202110175058.XA
Authority: CN
Inventors: 吴华强; 林博瀚; 高滨; 唐建石; 钱鹤
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2021-02-09
Filing date: 2021-02-09
Publication date: 2023-05-12
Anticipated expiration: 2041-02-09
Also published as: CN112863574A

Abstract

The present disclosure provides an electronic device and a method of operating the same, the device including a plurality of first resistive memory cells and a first control circuit configured to: performing a first initialization operation on each first resistance change memory unit according to the first set initialization value to obtain a first initialization resistance value; comparing each first initializing resistance value with a selected reference resistance value; and if the first initializing resistance value of the first resistive random access memory unit which is currently compared is smaller than or equal to the reference resistance value, performing second initializing operation on the first resistive random access memory unit according to the second set initializing value to reduce the first resistive random access memory unit to the second initializing resistance value, otherwise, not performing the second initializing operation on the first resistive random access memory unit to form physical unclonable function data, wherein the first set initializing value is larger than the second set initializing value. The device can effectively form physical unclonable function data by utilizing different initialization operations, and is also beneficial to the realization of effective hiding and recovery of subsequent data.

Description

Electronic device and operation method thereof

Technical Field

Embodiments of the present disclosure relate to an electronic device and a method of operating the same.

Background

The physical unclonable function (Physically Unclonable Function, PUF) is an emerging chip fingerprinting technique, e.g. capable of generating random 0/1 sequences as unique identifications of chip identities. Data in PUFs are often stored directly in non-volatile memory or CMOS (Complementary Metal-Oxide-Semiconductor) circuits, with the risk of being directly stolen by hackers using physical attack means or system security holes.

Disclosure of Invention

At least one embodiment of the present disclosure provides an electronic device, including: a resistive memory array including a plurality of first resistive memory cells; a first control circuit, wherein the first control circuit is configured to: according to a first set initialization value, performing a first initialization operation on each of the plurality of first resistive random access memory units to obtain a first initialization resistance value, so as to initialize each of the plurality of first resistive random access memory units to have a first resistance value change interval; comparing a first initialization resistance value of each of the plurality of first resistive memory cells with a selected reference resistance value; and in response to a first initialization resistance value of a currently compared first resistive random access memory cell of the plurality of first resistive random access memory cells being less than or equal to the reference resistance value, performing a second initialization operation on the currently compared first resistive random access memory cell according to a second set initialization value, so that the currently compared first resistive random access memory cell is reduced from the first initialization resistance value to a second initialization resistance value to initialize a resistance value change interval of the currently compared first resistive random access memory cell from the first resistance value change interval to a second resistance value change interval, and in response to the first initialization resistance value of the currently compared first resistive random access memory cell of the plurality of first resistive random access memory cells being greater than the reference resistance value, performing no second initialization operation on the currently compared first resistive random access memory cell and the currently compared first resistive random access memory cell still having the first resistance value change interval for forming a physical unclonable function, wherein the first initialization value is greater than the first set value.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the reference resistance is a preset first resistance.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the preset first resistance value is greater than the second initialization resistance value.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the resistive memory array further includes a second resistive memory cell, and the first control circuit is further configured to: according to the first set initialization value, performing the first initialization operation on the second resistance change memory unit to obtain a third initialization resistance value; and selecting the third initialization resistance value as the reference resistance value.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the first control circuit is further configured to: and resetting each of the plurality of first resistive random access memory cells to place each of the plurality of first resistive random access memory cells in a first resistance state having a resistance value greater than the first initialization resistance value for hiding the physical unclonable function data.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the resistive memory array further includes a plurality of second resistive memory cells, each of the plurality of first resistive memory cells having a corresponding one of the second resistive memory cells, the first control circuit is further configured to: according to the first set initialization value, performing the first initialization operation on each of the plurality of second resistive random access memory units to obtain a fourth initialization resistance value; for each of the plurality of first resistive memory cells, a fourth initialization resistance value of the corresponding second resistive memory cell is selected as the reference resistance value.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the plurality of first resistive random access memory units are in one-to-one correspondence with the plurality of second resistive random access memory units.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the first control circuit is further configured to: and performing a reset operation on each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells to place each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells in a first resistance state having a resistance value greater than the first initialization resistance value and the fourth initialization resistance value for hiding the physical unclonable function data.

At least one embodiment of the present disclosure provides an electronic device, including: a resistive random access memory array and a second control circuit, wherein the resistive random access memory array comprises a plurality of first resistive random access memory units, each of the plurality of first resistive random access memory units is initialized to a first initialization resistance value according to a first set initialization value and has a first resistance value change interval, in the case that the first initialization resistance value of a first resistive random access memory unit currently being compared among the plurality of first resistive random access memory units is smaller than or equal to a selected reference resistance value, the first resistive random access memory unit currently being compared also has undergone a second initialization operation according to a second set initialization value to be reduced to a second initialization resistance value and changed to have a second resistance value change interval, in the case that the first initialization resistance value of the first resistive random access memory unit currently being compared among the plurality of first resistive random access memory units is larger than the selected reference resistance value, the first resistive random access memory unit currently being compared does not undergo a second initialization operation and has a first resistance value change interval so as to store a physical function-unclonable function, in which the first data is not set, and the first physical function-hidden data is not stored; the second control circuit is configured to: and performing a recovery operation on each of the plurality of first resistive random access memory cells on which the hiding operation has been performed for recovering the physical unclonable function data.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the hiding operation includes a reset operation, and each of the plurality of first resistive memory cells has performed the reset operation to be in a first resistance state having a resistance value greater than the first initialization resistance value.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the recovery operation includes a set operation, and the second control circuit is configured to: and performing the set operation on each first resistive memory cell in the first resistive state according to a second resistance value to reduce each first resistive memory cell from the first resistive state to a second resistive state for recovering the physical unclonable function data, wherein the second resistance value is greater than or equal to the second set initialization value and less than the first set initialization value.

For example, at least one embodiment of the present disclosure provides an electronic device further comprising a readout circuit configured to: acquiring the second resistance value; and comparing the resistance value of each first resistance change memory unit in the second resistance state with the second resistance value, and determining and outputting the physical unclonable function data based on the comparison result.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the resistive memory array further includes a plurality of second resistive memory cells, each of the plurality of first resistive memory cells has a corresponding second resistive memory cell, each of the plurality of second resistive memory cells has been initialized to a third initialization resistance value according to the first set initialization value, the reference resistance value is the third initialization resistance value of the corresponding second resistive memory cell for each of the plurality of first resistive memory cells, the hiding operation includes a reset operation, and each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells has undergone the reset operation to be in a first resistance state having a resistance value greater than the first initialization resistance value and the third initialization resistance value.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the recovery operation includes a set operation, and the second control circuit is configured to: and respectively performing setting operation on each first resistance change memory unit and each second resistance change memory unit in the first resistance state according to a third resistance value so as to respectively reduce each first resistance change memory unit and each second resistance change memory unit from the first resistance state to the second resistance state for recovering the physical unclonable function data, wherein the third resistance value is larger than or equal to the second set initialization value and smaller than the first set initialization value.

For example, at least one embodiment of the present disclosure provides an electronic device further comprising a readout circuit configured to: and comparing the resistance value of the first resistance change memory unit in the second resistance state with the corresponding resistance value of the second resistance change memory unit in the second resistance state, and determining and outputting the physical unclonable function data based on a comparison result.

At least one embodiment of the present disclosure provides a method of operating an electronic device, including: according to a first set initialization value, performing a first initialization operation on each of a plurality of first resistance change memory units included in a resistance change memory array to obtain a first initialization resistance value, so as to initialize each of the plurality of first resistance change memory units to have a first resistance change interval; comparing a first initialization resistance value of each of the plurality of first resistive memory cells with a selected reference resistance value; and in response to a first initialization resistance value of a currently compared first resistive random access memory cell of the plurality of first resistive random access memory cells being less than or equal to the reference resistance value, performing a second initialization operation on the currently compared first resistive random access memory cell according to a second set initialization value, so that the currently compared first resistive random access memory cell is reduced from the first initialization resistance value to a second initialization resistance value to initialize a resistance value change interval of the currently compared first resistive random access memory cell from the first resistance value change interval to a second resistance value change interval, and in response to the first initialization resistance value of the currently compared first resistive random access memory cell of the plurality of first resistive random access memory cells being greater than the reference resistance value, performing no second initialization operation on the currently compared first resistive random access memory cell and the currently compared first resistive random access memory cell still having the first resistance value change interval for forming a physical unclonable function, wherein the first initialization value is greater than the first set value.

For example, in an operation method provided in at least one embodiment of the present disclosure, the reference resistance value is a preset first resistance value.

For example, in one method of operation provided by at least one embodiment of the present disclosure, the preset first resistance value is greater than the second initialization resistance value.

For example, one method of operation provided by at least one embodiment of the present disclosure further includes: and resetting each of the plurality of first resistive random access memory cells to place each of the plurality of first resistive random access memory cells in a first resistance state having a resistance value greater than the first initialization resistance value for hiding the physical unclonable function data.

For example, in one method of operation provided in at least one embodiment of the present disclosure, in response to the resistive memory array further comprising a plurality of second resistive memory cells and each of the plurality of first resistive memory cells having a corresponding one of the second resistive memory cells, further comprising: performing the first initializing operation on each of the plurality of second resistive random access memory units according to the first set initializing value to obtain a third initializing resistance value; for each of the plurality of first resistive memory cells, selecting a third initialization resistance value of the corresponding second resistive memory cell as the reference resistance value.

For example, in one method of operation provided by at least one embodiment of the present disclosure, the plurality of first resistive memory cells are in one-to-one correspondence with the plurality of second resistive memory cells.

For example, one method of operation provided by at least one embodiment of the present disclosure further includes: and performing a reset operation on each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells to place each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells in a first resistance state having a resistance value greater than the first initialization resistance value and the fourth initialization resistance value for hiding the physical unclonable function data.

At least one embodiment of the present disclosure provides a method of operating an electronic device, including: selecting a plurality of first resistive random access memory cells included in a resistive random access memory array, wherein each of the plurality of first resistive random access memory cells has been initialized to a first initialization resistance value according to a first set initialization value and has a first resistance change interval, and in the case where the first initialization resistance value of a first resistive random access memory cell currently being compared among the plurality of first resistive random access memory cells is less than or equal to a selected reference resistance value, the first resistive random access memory cell currently being compared has also been subjected to a second initialization operation according to a second set initialization value to be reduced to a second initialization resistance value and changed to have a second resistance change interval, and in the case where the first initialization resistance value of the first resistive random access memory cell currently being compared among the plurality of first resistive random access memory cells is greater than the selected reference resistance value, the first resistive random access memory cell currently being compared does not undergo a second initialization operation and still has the first resistance change interval to store physical unclonable function data, wherein the first initialization value is greater than the first initialization value and the first resistance change interval is hidden per the first set variable memory cell; and performing a recovery operation on each of the plurality of first resistive random access memory cells on which the hiding operation has been performed for recovering the physical unclonable function data.

For example, in one method of operation provided by at least one embodiment of the present disclosure, the hiding operation includes a reset operation, each of the plurality of first resistive memory cells having undergone the reset operation to be in a first resistance state having a resistance value greater than the first initialization resistance value.

For example, in one method of operation provided by at least one embodiment of the present disclosure, performing a recovery operation on each of the plurality of first resistive random access memory cells on which the hiding operation has been performed for recovering the physical unclonable function data, includes: and performing a set operation on each first resistive memory cell in the first resistive state according to a second resistance value to reduce each first resistive memory cell from the first resistive state to a second resistive state for recovering the physical unclonable function data, wherein the second resistance value is greater than or equal to the second set initialization value and less than the first set initialization value.

For example, one method of operation provided by at least one embodiment of the present disclosure further includes: reading the recovered physical unclonable function data, wherein reading the recovered physical unclonable function data comprises: acquiring the second resistance value; and comparing the resistance value of each first resistance change memory unit in the second resistance state with the second resistance value, and determining and outputting the physical unclonable function data based on the comparison result.

For example, in one method of operation provided in at least one embodiment of the present disclosure, the resistive memory array further includes a plurality of second resistive memory cells, each of the plurality of first resistive memory cells has a corresponding second resistive memory cell, each of the plurality of second resistive memory cells has been initialized to a third initialization resistance value according to the first set initialization value, the reference resistance value is the third initialization resistance value of the corresponding second resistive memory cell for each of the plurality of first resistive memory cells, the hiding operation includes a reset operation, and each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells has undergone the reset operation to be in a first resistance state having a resistance value greater than the first initialization resistance value and the third initialization resistance value, respectively.

For example, in one method of operation provided by at least one embodiment of the present disclosure, performing a recovery operation on each of the plurality of first resistive random access memory cells on which the hiding operation has been performed for recovering the physical unclonable function data, includes: and respectively performing setting operation on each first resistance change memory unit in the first resistance state and each second resistance change memory unit in the first resistance state according to a third resistance value so as to respectively reduce each first resistance change memory unit and each second resistance change memory unit from the first resistance state to a second resistance state for recovering the physical unclonable function data, wherein the third resistance value is larger than or equal to the second set initialization value and smaller than the first set initialization value.

For example, one method of operation provided by at least one embodiment of the present disclosure further includes: reading the recovered physical unclonable function data, wherein reading the recovered physical unclonable function data comprises: and comparing the resistance value of the first resistance change memory unit in the second resistance state with the corresponding resistance value of the second resistance change memory unit in the second resistance state, and determining and outputting the physical unclonable function data based on a comparison result.

For example, one method of operation provided by at least one embodiment of the present disclosure further includes: after the recovered physical unclonable function data is read, performing a reset operation on each resistive random access memory unit included in the resistive random access memory array again so as to place each resistive random access memory unit in the resistive random access memory array in the first resistive state for hiding the physical unclonable function data.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

Fig. 1 is a schematic block diagram of an electronic device 100 provided in some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of a resistive random access memory cell provided in some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of an initialization operation for a resistive random access memory cell according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of a set operation performed on a resistive random access memory cell according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of a resistive random access memory cell performing a reset operation according to some embodiments of the present disclosure;

FIG. 6 is a schematic diagram of an electronic device for generating PUF data based on self resistance and reference resistance values of each resistive memory cell in a resistive memory array according to some embodiments of the present disclosure;

FIG. 7 is a schematic block diagram of an electronic device provided by other embodiments of the present disclosure;

FIG. 8 is a schematic diagram of pseudocode for an initialization operation process provided by some embodiments of the present disclosure;

fig. 9 is a flow chart of a PUF data hiding method provided by some embodiments of the present disclosure;

FIG. 10 is a schematic block diagram of an electronic device 200 provided in some embodiments of the present disclosure;

fig. 11 is a flow chart of a PUF data recovery method provided by some embodiments of the present disclosure;

FIG. 12 is a schematic block diagram of an electronic device 300 provided in some embodiments of the present disclosure;

FIG. 13 is a schematic block diagram of an electronic device 300 provided in accordance with further embodiments of the present disclosure;

fig. 14 is a flowchart of a method of operation of an electronic device 300 provided in some embodiments of the present disclosure;

FIG. 15 is a flowchart of a method of operation of an electronic device 300 provided in further embodiments of the present disclosure;

fig. 16 is a schematic diagram of PUF data read out after an initialization operation provided by some embodiments of the present disclosure;

fig. 17 is a schematic diagram of PUF data read out after a concealment operation provided by some embodiments of the present disclosure;

fig. 18 is a schematic diagram of PUF data read out after a recovery operation provided by some embodiments of the present disclosure;

fig. 19 is a schematic diagram showing a comparison of PUF data hiding rate and PUF data hiding rate of other solutions provided by some embodiments of the present disclosure; and

fig. 20 is a schematic diagram illustrating a comparison of data error rates provided by some embodiments of the present disclosure and data error rates of other schemes.

Detailed Description

The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

Unless defined otherwise, all terms (including technical and scientific terms) used in the embodiments of the disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined by the presently disclosed embodiments.

The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Nor does the terms "a," "an," or "the" or similar terms mean a limitation of quantity, but rather that at least one is present. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. A flowchart is used in the embodiments of the present disclosure to illustrate the steps of a method according to embodiments of the present disclosure. It should be understood that the steps that follow or before do not have to be performed in exact order. Rather, the various steps may be processed in reverse order or simultaneously. Also, other operations may be added to or removed from these processes.

For the problem that data in the PUF is at risk of being directly stolen by a hacker by utilizing a physical attack means or a system security hole, the hidden PUF can be utilized to further improve the security of the system. For example, a concealable PUF means that data in the PUF can be concealed when not called and recovered when called, so a hacker can only steal invalid, concealed PUF data by the above mentioned means of attack.

In addition, hiding and recovering of PUF data can be achieved by applying set voltage and reset voltage to the resistive random access memory array, and therefore the hidden PUF design based on the resistive random access memory is achieved. However, the current method is very dependent on the magnitude of the set voltage and the reset voltage, and for PUFs in different chips, the magnitude of the set voltage and the reset voltage need to be determined by performing multiple operations on the resistive random access memory array, which results in high design cost of the chip. In addition, the error rate of the hidden PUF technology proposed by the method is very high, for example, 10%, when PUF data is recovered, so that the reliability problem exists in practical application.

At least one embodiment of the present disclosure provides an electronic device, including: a resistive memory array including a plurality of first resistive memory cells; a first control circuit, wherein the first control circuit is configured to:

According to the first set initialization value, performing a first initialization operation on each of the plurality of first resistance change memory units to obtain a first initialization resistance value, so as to initialize each of the plurality of first resistance change memory units to have a first resistance change interval;

comparing a first initialization resistance value of each of the plurality of first resistive memory cells with a selected reference resistance value;

and in response to the first initialization resistance value of the currently compared first resistive random access memory cell of the plurality of first resistive random access memory cells being smaller than or equal to the reference resistance value, performing a second initialization operation on the currently compared first resistive random access memory cell according to a second set initialization value, so that the currently compared first resistive random access memory cell is reduced from the first initialization resistance value to the second initialization resistance value, a resistance change interval of the currently compared first resistive random access memory cell is initialized from the first resistance change interval to the second resistance change interval, and in response to the first initialization resistance value of the currently compared first resistive random access memory cell of the plurality of first resistive random access memory cells being greater than the reference resistance value, the second initialization operation is not performed on the currently compared first resistive random access memory cell and the currently compared first resistive random access memory cell still has the first resistance change interval for forming PUF data, wherein the first set initialization value is greater than the second set initialization value.

At least one embodiment of the present disclosure further provides an operation method corresponding to the above electronic device.

According to the electronic device or the operation method of the embodiment of the disclosure, different initialization (FORM) operations are performed on corresponding Resistive Random-Access Memory cells (RRAM) in the Resistive Memory array according to two set different target initialization values, so that PUF data can be effectively formed, and different initialization operations can be utilized to affect the lowest resistance states of the Resistive Memory cells of the Resistive Memory array differently, thereby facilitating realization of effective hiding and recovery of subsequent PUF data.

Some embodiments of the present disclosure describe in detail the electronic device 100 and its method of operation in terms of hiding PUF data, with reference to fig. 1-9.

Fig. 1 is a schematic block diagram of an electronic device 100 provided in some embodiments of the present disclosure.

As shown in fig. 1, the electronic device 100 includes a resistive memory array 110 and a first control circuit 120. The resistive memory array 110 includes a plurality of first resistive memory cells. For example, for any one of the resistive memory cells of the resistive memory array 110, the resistance value of the resistive memory cell can be artificially controlled by applying different pulses.

Fig. 2 is a schematic diagram of a resistive random access memory cell according to some embodiments of the present disclosure. Fig. 3 is a schematic diagram of an initializing operation of a resistive random access memory cell according to some embodiments of the present disclosure. Fig. 4 is a schematic diagram of a SET operation performed on a resistive random access memory cell according to some embodiments of the present disclosure. Fig. 5 is a schematic diagram of a one-time RESET (RESET) operation for a resistive random access memory cell according to some embodiments of the present disclosure.

For example, as shown in fig. 2, the resistive memory cell may have a 1T1R structure, i.e., include one transistor and one resistive element, and the resistive memory cell includes three ports: word line (BL), source Line (SL) and Word Line (WL), although other configurations of resistive memory cells may be used, as embodiments of the present disclosure are not limited in this respect.

For example, as shown in fig. 3, if an initializing operation is performed on the resistive memory cell, at this time, SL is grounded, WL and BL are pulsed, and the resistance value of the resistive memory cell is lowered.

For example, as shown in fig. 4, if a set operation is performed on the resistive memory cell, at this time, SL is grounded, WL and BL are pulsed, and the resistance value of the resistive memory cell is lowered. The initialization operation is different from the set operation in that the voltage used in the initialization operation is larger and the pulse width is wider, for example, the voltage used in the initialization operation is 4V, the pulse width is 100ms, and the voltage used in the set operation is 2V, and the pulse width is 100ns.

For example, as shown in fig. 5, when a reset operation is performed on the resistive memory cell, BL is grounded, WL and SL are pulsed, and the resistance value of the resistive memory cell increases.

It should be noted that, in the embodiment of the present disclosure, the initialization operation uses a very high voltage and a very wide pulse, which often causes a significant change in the resistance value of the resistive memory cell. Different initialization conditions can also have a significant impact on the characteristics of the resistive memory cell, one of which is affecting the lowest resistance state of the resistive memory cell. For example, for a resistive memory cell having a resistance value of about 150kΩ after an initializing operation, the lowest resistance state that can be achieved by a set operation is also about 150kΩ; for another example, for a resistive memory cell having a resistance value of about 25kΩ after an initialization operation, the lowest resistance state that can be achieved by a set operation is 25kΩ.

It should also be noted that in the embodiments of the present disclosure, different initialization conditions have no effect on the highest resistance state of the resistive memory cell, for example, the resistance value of the resistive memory cell can be raised to be above 1.5mΩ by a reset operation, whether it is a resistive memory cell having a resistance value of 150kΩ or 25kΩ after an initialization operation.

For example, in some examples, the first control circuit 120 is configured to:

(1) According to the first set initialization value P1, performing a first initialization operation on each of the plurality of first resistive random access memory units to obtain a first initialization resistance value R1 so as to initialize each of the plurality of first resistive random access memory units to have a first resistance value change interval;

(2) Comparing the first initialization resistance value R1 of each of the plurality of first resistive random access memory cells with a selected reference resistance value Ref 1;

(3) When a first initializing resistance value R1 of a first resistance change memory unit which is currently compared in the plurality of first resistance change memory units is smaller than or equal to a reference resistance value Ref1, performing second initializing operation on the first resistance change memory unit which is currently compared according to a second set initializing value P2, so that the first resistance change memory unit which is currently compared is reduced from the first initializing resistance value R1 to the second initializing resistance value R2, and initializing a resistance change interval of the first resistance change memory unit which is currently compared from the first resistance change interval to the second resistance change interval, wherein the first set initializing value P1 is larger than the second set initializing value P2; when the first initializing resistance value R1 of the currently compared first resistive random access memory cell of the plurality of first resistive random access memory cells is larger than the reference resistance value Ref1, the second initializing operation is not performed on the currently compared first resistive random access memory cell, and the currently compared first resistive random access memory cell still has a first resistance value variation interval for forming PUF data.

For example, in some examples, the PUF data formed includes two value states, respectively denoted as a first value and a second value, e.g., a 0 state and a 1 state, and the following description will take the example of 0/1 sequence to form PUF data, and of course, the examples herein are equally applicable to use of other value states to form PUF data, which is not limited by the disclosure and not repeated herein.

It should be noted that, the first resistive memory cell of the resistive memory array of any embodiment of the present disclosure may be at least a portion of the resistive memory cells selected in the resistive memory array, or may be all of the resistive memory cells included in the resistive memory array, which is not limited in this aspect of the embodiments of the present disclosure, and the "first resistive memory cell" of the resistive memory array of the foregoing embodiments is intended to be convenient for language description, so as to distinguish between the resistive memory cells of other portions that are different or associated with them when they appear hereinafter, which does not affect understanding of the embodiments of the present disclosure by those skilled in the art, or does not limit the embodiments of the present disclosure.

Fig. 6 is a schematic diagram of an electronic device for generating PUF data based on self resistance and reference resistance values of each resistive memory cell in a resistive memory array according to some embodiments of the present disclosure.

For example, as shown in fig. 6, the self resistance state and the reference resistance value Ref1 of each resistive memory cell (e.g., the first resistive memory cell 110 a) in the resistive memory array 110 after undergoing the first initialization operation are utilized to generate PUF data; for convenience of description, this will be referred to as the case of the first type of initialization operation, simply referred to as case one.

For case one, for example, in some examples, the reference resistance value Ref1 is a first resistance value Q1 set in advance. For example, the preset first resistance value Q1 is larger than the second initialization resistance value R2.

For case one, for example, in some examples, the method of forming PUF data by an initialization operation is as follows:

(a) A first resistance value Q1 is preset, and one resistive memory cell located at the coordinate (i, j) in the resistive memory array 110 is selected and denoted as RRAMa;

(b) Performing a first initializing operation on the RRAMa, modulating the resistance value of the RRAMa to a first initializing resistance value, and recording Ra as about 150kΩ, wherein the RRAMa is initialized to have a first resistance value change interval (for example, the lowest resistance state is about 150kΩ), for example, the first resistance value Q1 as the reference resistance value Ref1 is 140kΩ;

(c) If Ra is less than or equal to Q1, performing a second initialization operation on the RRAMa, and modulating the resistance value of the RRAMa to a second initialization resistance value R2, such as about 25kΩ, then initializing the resistance value variation section of the RRAMa from the first resistance value variation section to a second resistance value variation section (for example, the lowest resistance state is about 25kΩ); if Ra > Q1, do not do any operation to RRAMa, then RRAMa still has the first resistance change interval;

(d) And then moving to the next coordinate of the resistive random access memory array 110, and repeating the above steps until all the resistive random access memory cells in the resistive random access memory array 110 are traversed.

It should be noted that, the resistance value of each resistive memory cell is changed by random movement of atoms in the resistive memory cell, so that the obtained resistance value of the resistive memory cell after the initializing operation, the resetting operation or the setting operation is randomly distributed and cannot be accurately determined in advance.

In an embodiment of the disclosure, whether the resistive memory cell performs the second initialization operation is determined based on a resistance value obtained after the resistive memory cell performs the first initialization operation, for example, whether the resistive memory cell performs the second initialization operation is determined by comparing the resistance value obtained after the resistive memory cell performs the first initialization operation with a preset resistance value, one PUF data state (for example, 0 state) is formed when the resistive memory cell performs only the first initialization operation, and the other PUF data state (for example, 1 state) is formed after the resistive memory cell performs the first initialization operation and the second initialization operation.

In the embodiment of the disclosure, according to the set two different target initialization values, only one stage or two stages of initialization operations are performed on the corresponding resistive random access memory unit, so that the lowest resistance states of the different resistive random access memory units are different, and subsequent PUF data hiding and further PUF data recovery are facilitated.

In some embodiments of the present disclosure, the lowest resistance state of the resistive random access memory cell is utilized to distinguish between different PUF data states, and the resistive random access memory cell is brought to the lowest resistance state through a set operation, so that the set voltage level during the set operation can be flexibly selected, the dependency of the set voltage level is low, and a great amount of training on the set voltage is not required. In addition, in the embodiment of the disclosure, since different initialization operations have no influence on the highest resistance state of the resistive random access memory unit, the randomness of the resistance value obtained after the resistive random access memory unit performs the reset operation can be used to realize the hiding of the PUF data, the reset voltage in the reset operation process can be flexibly selected, the dependency on the reset voltage is low, and a great amount of training on the reset voltage is not needed.

For example, after the initialization operation is completed (e.g., after the resistive memory cell only needs to undergo the first initialization operation or after the resistive memory cell also needs to undergo the second initialization operation after the first initialization operation), if the entire resistive memory array is sequentially read by the readout circuit, the obtained PUF data is defined as the original PUF data, e.g., the original PUF data corresponding to a specific coordinate (x, y) in the resistive memory array is recorded as P _x,y 。

For case one, for example, in some examples, the resistive memory array 110 further includes a second resistive memory cell, the first control circuit 120 further configured to: according to the first set initialization value P1, performing a first initialization operation on the second resistive random access memory unit to obtain a corresponding initialization resistance value R3, and then selecting the initialization resistance value R3 of the second resistive random access memory unit as the reference resistance value Ref1. For example, the second resistive memory cell may be one of the plurality of first resistive memory cells described above, or may be a single resistive memory cell, which is not limited in the embodiments of the present disclosure.

For case one, for example, in some examples, the first control circuit 120 is further configured to: a reset operation is performed on each of the plurality of first resistive memory cells 110a to place each of the plurality of first resistive memory cells 110a in a first resistance state (which may also be referred to as a high resistance state H1) having a resistance value greater than the first initialization resistance value R1 for hiding the PUF data formed. For example, the first initializing resistance value R1 is about 150kΩ, and the resistance value of the high-resistance state H1 is 1.5mΩ or more, which is, of course, merely exemplary and not a limitation of the present disclosure.

Notably, based on case one, the result of PUF data hiding is: the read result of the whole resistive random access memory array after the reset operation is all 0 (not shown), because the resistance value of the resistive random access memory unit in the high resistance state H1 is too large (for example, more than 1.5mΩ) and is far greater than the first resistance value Q1 or the first initialization resistance value R1, so that the original PUF data is effectively hidden.

For example, in some examples, the resistance states of each two resistive memory cells after undergoing an initialization operation are compared to produce PUF data; for convenience of description, this will be referred to as the case of the second type of initialization operation, simply referred to as the case two.

For case two, for example, in some examples, the resistive memory array 110 includes not only the plurality of first resistive memory cells described above, but also a plurality of second resistive memory cells, where each of the plurality of first resistive memory cells has a corresponding second resistive memory cell, and the first control circuit 120 is further configured to: according to the first set initialization value P1, performing a first initialization operation on each of the plurality of second resistive random access memory cells to obtain a first initialization resistance value R1', and selecting the first initialization resistance value R1' of the corresponding second resistive random access memory cell as a reference resistance value Ref1 for each of the plurality of first resistive random access memory cells.

In other words, for the second case, when the first initialization resistance value R1 of the currently selected first resistive random access memory cell is less than or equal to the first initialization resistance value R1' of the corresponding second resistive random access memory cell, performing the second initialization operation on the first resistive random access memory cell, so that the first resistive random access memory cell is reduced from the first initialization resistance value R1 to the second initialization resistance value R2; when the first initializing resistance value R1 of the first resistive random access memory unit is greater than the first initializing resistance value R1 'of the second resistive random access memory unit, the second initializing operation is not performed on the first resistive random access memory unit, but the second initializing operation is performed on the second resistive random access memory unit, so that the second resistive random access memory unit is reduced from the first initializing resistance value R1' to the corresponding second initializing resistance value R2.

For example, in some examples, the plurality of first resistive memory cells corresponds one-to-one with the plurality of second resistive memory cells.

Fig. 7 is a schematic block diagram of an electronic device provided in other embodiments of the present disclosure.

For example, as shown in fig. 7, the resistive memory array 110 includes a first sub resistive memory array (denoted as sub-array a) and a second sub resistive memory array (denoted as sub-array B), and the plurality of resistive memory cells in the resistive memory array 110 are divided into a first group of resistive memory cells (for example, the first resistive memory cell in case two) constituting the sub-array a, and a second group of resistive memory cells (for example, the second resistive memory cell in case two) constituting the sub-array B.

For example, in some examples, the number of resistive memory cells in the first set of resistive memory cells is the same as the number of resistive memory cells in the second set of resistive memory cells, the resistive memory cells in the first set of resistive memory cells being arranged in N rows and M columns, the resistive memory cells in the second set of resistive memory cells being arranged in N rows and M columns (e.g., n=64, m=8). For example, a first resistive random access memory cell is located in an ith row and a jth column in a first sub resistive random access memory array, and a second resistive random access memory cell is located in an ith row and a jth column in a second sub resistive random access memory array, where N and M are positive integers, 1.ltoreq.i.ltoreq.N, 1.ltoreq.j.ltoreq.M. For another example, a first resistive memory cell is located in row i1, column j1 in a first sub-resistive memory array, and a second resistive memory cell is located in row i2, column j2 in a second sub-resistive memory array, i1 and i2 being different and/or j1 and j2 being different.

It should be noted that, in the above embodiments of the present disclosure, the "first sub-resistive memory array" and the "second sub-resistive memory array" are intended to distinguish two sub-resistive memory arrays, but not limit the two sub-resistive memory arrays, and the first sub-resistive memory array and the second sub-resistive memory array may be integrated into one resistive memory array, that is, the first sub-resistive memory array and the second sub-resistive memory array are different portions in the same resistive memory array; the first and second sub-resistive memory arrays may also be two different resistive memory arrays arranged separately; likewise, "first resistive memory cell" and "second resistive memory cell" are also intended to distinguish between two resistive memory cells, rather than to limit two resistive memory cells. For example, the first resistive memory cell may also be located in the ith row, and the second resistive memory cell may also be located in the ith row, and the first resistive memory cell may also be located in the ith column, of the first resistive memory array, which embodiments of the present disclosure are not limited in this respect.

For case one or case two, for example, in some examples, the condition of the first initialization operation may be: pulse width 800ms, BL voltage of 4V, WL voltage of 1.2V, and first set initialization value P1 is 150kΩ; the conditions for the second initialization operation may be: the pulse width 800ms, the bl voltage level 4V, the wl voltage level 1.6V, and the second set initialization value P2 of 25kΩ are, of course, merely exemplary, not limiting the present disclosure, and other voltage conditions may be used, and embodiments of the present disclosure are not further described herein.

Fig. 8 is a schematic diagram of pseudocode for an initialization operation process provided by some embodiments of the present disclosure.

For case two, for example, in some examples, the function of the first control circuit 120 is to perform a series of initialization operations on the resistive memory array 110 to generate PUF data, implementing pseudocode as shown in fig. 8.

For example, in some examples, a description corresponding to that shown in fig. 8 is as follows:

(a) Selecting two resistive random access memory cells A (i, j) and B (i, j) of subarray A and subarray B at coordinates (i, j), respectively denoted as RRAMa and RRAMb;

(b) Performing a first initializing operation form_1st on the RRAMa and the RRAMb respectively according to a first set initializing value P1, for example, 150kΩ, modulating the resistance values of the RRAMa and the RRAMb to, for example, about 150kΩ, and respectively denoted as Ra and Rb, that is, the RRAMa and the RRAMb are respectively initialized to have a first resistance change section (for example, the lowest resistance state is about 150kΩ);

(c) If Ra is less than or equal to Rb, performing a second initialization operation FORM_2nd on the RRAMa, modulating the resistance value of the RRAMa to about 25kΩ, namely initializing the resistance value variation section of the RRAMa from a first resistance value variation section to a second resistance value variation section (for example, the lowest resistance state is about 25kΩ), and performing no operation on RRAMb, namely, the RRAMb still has the first resistance value variation section; if Ra > Rb, performing a second initializing operation FORM_2nd on the RRAMb, modulating the resistance value of the RRAMb to about 25kΩ, i.e. initializing the resistance value variation section of the RRAMb from a first resistance value variation section to a second resistance value variation section (e.g. the lowest resistance state is about 25kΩ), and performing no operation on RRAMa, i.e. the RRAMa still has the first resistance value variation section;

(d) And then moving to the next coordinates of the subarrays respectively, and repeating the steps until all RRAMs in the complete subarray are traversed.

In the embodiments of the present disclosure, it is determined which of the two resistive memory cells is subjected to the second initialization operation based on the resistance values obtained after the two resistive memory cells are subjected to the first initialization operation, for example, the resistance values obtained after the two resistive memory cells are subjected to the first initialization operation are compared in size to determine which resistive memory cell is subjected to the second initialization operation (for example, the resistive memory cell with the smaller resistance value is taken), only the first initialization operation is performed on the two resistive memory cells to form one PUF data state (for example, the 0 state), and the other PUF data state (for example, the 1 state) is formed after the first initialization operation and the second initialization operation are performed on one of the two resistive memory cells.

In some embodiments of the present disclosure, the lowest resistance states of two resistive random access memory cells are utilized to distinguish between different PUF data states, and the resistive random access memory cells are brought to the lowest resistance states through a set operation, so that the set voltage level during the set operation can be flexibly selected, the dependency of the set voltage level is low, and a great deal of training of the set voltage is not required. In addition, in the embodiment of the disclosure, since different initialization operations have no influence on the highest resistance state of the resistive random access memory unit, the randomness of the resistance value obtained after the resistive random access memory unit performs the reset operation can be used to realize the hiding of the PUF data, the reset voltage in the reset operation process can be flexibly selected, the dependency on the reset voltage is low, and a great amount of training on the reset voltage is not needed.

For example, after the initialization operation is completed (e.g., one of the two resistive random access memory cells is subjected to the second initialization operation), if the entire resistive random access memory array is sequentially read by the readout circuit, the obtained PUF data is defined as the original PUF data, e.g., the original PUF data corresponding to a specific coordinate (x, y) in the resistive random access memory array is denoted as P _x,y 。

Furthermore, it is worth noting that some embodiments of the present disclosure can also enhance the resistance difference between two resistive memory cells through a two-stage initialization operation to effectively form PUF data.

For case two, for example, in some examples, the first control circuit 120 is further configured to: and resetting each of the plurality of first resistive random access memory cells and each of the plurality of second resistive random access memory cells to place each of the plurality of first resistive random access memory cells and each of the plurality of second resistive random access memory cells in a first resistive state (also referred to as a high resistive state H1 ') for hiding PUF data, wherein the resistance value of the high resistive state H1' is greater than the initialization resistance value R1 of the first resistive random access memory cells subjected to the first initialization operation and the first initialization resistance value R1' of the second resistive random access memory cells subjected to the first initialization operation. For example, the initializing resistances R1 and R1 'are around 150kΩ and the high resistance H1' is 1.5mΩ or more, although this is merely exemplary and not limiting of the present disclosure.

Fig. 9 is a flow chart of a PUF data hiding method provided in some embodiments of the present disclosure.

For the second case, for example, as shown in fig. 9, in order to convert the original PUF data P corresponding to a specific coordinate (x, y) in the resistive random access memory array _x,y The method by which the first control circuit 120 performs the PUF hiding operation is as follows: the resistive memory cells in the sub-arrays a and B located at the coordinates (x, y) are selected and respectively denoted as RRAMa and RRAMb, and then the RRAMa and RRAMb are subjected to the operations shown in fig. 9, i.e. the reset operation is performed at most N1 (for example, count=100), in an attempt to modulate the resistance values of RRAMa and RRAMb to be above 1.5mΩ, and put in a high resistance state, wherein 1.5mΩ is only exemplary, not limiting the disclosure, but may be other resistance values, of course, 100 times are only one example, and the embodiments of the disclosure are not limited thereto, and may be correspondingly adjusted according to practical situations.

In case two, the resistance value of the resistive memory cell initialized to 25kΩ or 150kΩ can be reset to 1.5mΩ or more according to the setting. Since the resistance value of the resistive random access memory unit after the reset operation is random, after the reset operation, if PUF data obtained by sequentially reading the whole resistive random access memory array by using the readout circuit is significantly different from the original PUF data, namely, the PUF data is hidden.

For the second case, for example, for a specific coordinate (x, y), after undergoing an initialization operation, if RRAMa is about 25kΩ and RRAMb is about 150kΩ after undergoing a second initialization operation, the readout circuit of the electronic device reads a second value (e.g. 1); it should be noted that, if the resistance value of the high resistance state is set to be 1.5mΩ or more, after the hiding operation (i.e. the setting operation), the resistance value of RRAMa may be 1.6mΩ and the resistance value of RRAMb may be 1.5mΩ due to the randomness of the resistance values, and the result obtained by the readout circuit becomes the first value (e.g. 0). For example, according to the experimental results, after the hiding operation, about 40% of the PUF data is inconsistent with the original PUF data, i.e. the hiding of the PUF data is achieved (see fig. 16 and 17 below).

At least one embodiment of the present disclosure provides an electronic device, including: the first resistance change memory unit is subjected to a second initialization operation according to a second set initialization value to be reduced to a second initialization resistance value and changed to have a second resistance value change section, and the first resistance change memory unit which is currently compared does not perform a second initialization operation and still has a first resistance value change section to store data when the first initialization resistance value of the first resistance change memory unit which is currently compared is smaller than or equal to a selected reference resistance value in the plurality of first resistance change memory units, wherein the first initialization resistance value is larger than the second set initialization value, and the PUF data is stored in each of the plurality of first resistance change memory units; the second control circuit is configured to: a recovery operation is performed on each of the plurality of first resistive random access memory cells on which the hiding operation has been performed for recovering the PUF data.

The electronic device or the operation method of the embodiment of the disclosure performs different initialization operations on the corresponding resistive random access memory cells in the resistive random access memory array to effectively form PUF data and performs recovery operations after effectively hiding the PUF data through hiding operations, and distinguishes different PUF data states by using the lowest resistance states of the resistive random access memory cells, thereby realizing PUF data recovery with low error rate and reducing dependence on magnitude of set and reset voltages. Therefore, at least one embodiment of the present disclosure proposes a scheme for implementing the hidden PUF data with low error rate based on the resistive random access memory, so that not only the design cost of the chip can be effectively reduced, but also the reliability of the hidden PUF can be significantly improved.

Some embodiments of the present disclosure are described in detail with reference to fig. 10-11 for an electronic device 200 and a method of operation thereof in terms of recovering PUF data.

Fig. 10 is a schematic block diagram of an electronic device 200 provided in some embodiments of the present disclosure.

As shown in fig. 10, the electronic device 200 includes a resistive memory array 210 and a second control circuit 220. The resistive memory array 210 includes a plurality of first resistive memory cells. For example, for any one of the resistive memory cells of the resistive memory array 210, the resistance value of the resistive memory cell can be artificially controlled by applying different pulses.

It should be noted that, in the embodiment of the disclosure, the specific composition and functions of the resistive memory array 210 of the electronic device 200 may refer to the resistive memory array 110 of the electronic device 100, which is not described herein for clarity and brevity.

It should be further noted that, the resistive random access memory array 210 and the resistive random access memory array 110 may refer to the same array in the same application scenario, for example, after performing an initialization operation and a reset operation based on the array, a set operation described below is continuously performed on the array to implement hiding and recovering of PUF data, which may, of course, be different arrays in different application scenarios, and embodiments of the present disclosure are not limited thereto.

For example, in some examples, the second control circuit 220 is configured to: a recovery operation is performed on each of the plurality of first resistive random access memory cells that have been subjected to the hiding operation to recover the original PUF data that has been hidden, i.e., to recover the original PUF data that was previously formed.

For example, in some examples, before PUF data is recovered, each of the plurality of first resistive memory cells of the resistive memory array 210 has been initialized to a first initialized resistance value R1 according to a first set initialized value P1 (e.g., 150kΩ) and has a first resistance change interval (e.g., the lowest resistance state is around 150kΩ), and in the case where the first initialized resistance value R1 of a first resistive memory cell currently being compared among the plurality of first resistive memory cells is less than or equal to the selected reference resistance value Ref1, the first resistive memory cell currently being compared has also been reduced to a second initialized resistance value R2 according to a second set initialized value P2 (e.g., 25kΩ) and has been changed to have a second resistance change interval (e.g., the lowest resistance state is around 25kΩ); in the case that the first initialization resistance R1 of the first resistive random access memory cell currently being compared among the plurality of first resistive random access memory cells is greater than the selected reference resistance Ref1, the first resistive random access memory cell currently being compared does not perform the second initialization operation and still has the first resistance change interval to store PUF data, wherein the first set initialization value P2 is greater than the second set initialization value P1, and each of the plurality of first resistive random access memory cells has performed a hiding operation to hide the stored PUF data.

It should be noted that each of the plurality of first resistive memory cells of the resistive memory array 210 according to the embodiment of the present disclosure may be subjected to a hiding operation (e.g., a resetting operation) with reference to the electronic device 100 and the operation method thereof to hide PUF data, and may also be subjected to an initializing operation to store PUF data according to the electronic device 100 and the operation method thereof.

For example, in some examples, for case one (as described above), the hiding operation includes a reset operation, wherein each of the plurality of first resistive memory cells of the resistive memory array 210 has undergone a reset operation to be in a first resistive state (also referred to as a high resistive state H1) prior to recovering PUF data, wherein the resistance value of the high resistive state H1 is greater than the first initialization resistance value R1. For example, the first initializing resistance value R1 is about 150kΩ, and the resistance value of the high-resistance state H1 is 1.5mΩ or more, which is, of course, merely exemplary and not a limitation of the present disclosure.

For another example, in some examples, for case two (as described above), the hiding operation includes a reset operation, each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells having been reset to be in a first resistive state (also referred to as a high resistive state H1 '), wherein a resistance value of the high resistive state H1' is greater than an initialization resistance value of the first resistive memory cell through the first initialization operation (as described above for the first initialization resistance value R1) and an initialization resistance value of the second resistive memory cell through the first initialization operation (as described above for the first initialization resistance value R1 '). For example, the initializing resistances R1 and R1 'are around 150kΩ and the high resistance H1' is 1.5mΩ or more, although this is merely exemplary and not limiting of the present disclosure.

For case one or case two, for example, in some examples, the condition of the reset operation may be: pulse width 800ms, SL voltage level 2.5V, WL voltage level 5.0V, high impedance state target value 1.5MΩ. Of course, this is merely exemplary and is not limiting of the present disclosure, and other voltage conditions may be employed, and embodiments of the present disclosure are not intended to be exhaustive or redundant herein.

For case one, for example, in some examples, the resume operation includes a set operation, the second control circuit 220 configured to: each first resistive memory cell in the high resistance state H1 is set according to the second resistance value Q2 to reduce each first resistive memory cell from the high resistance state H1 to a second resistance state (also referred to as a low resistance state L1) for recovering PUF data, wherein the second resistance value Q2 is at least greater than or equal to the second set initialization value P2 and less than the first set initialization value P1.

For example, in some examples, the electronic device 200 further includes a readout circuit (not shown) for reading out PUF data that has undergone a recovery operation, where the PUF data readout method and the initialization operation method need to be consistent, that is, the initialization operation is performed by comparing resistance values of every two resistive random access memory cells, so that the PUF data readout also needs to be performed by comparing resistance values of two resistive random access memory cells, and similarly, if the initialization operation is performed by comparing self resistance states of one resistive random access memory cell with a preset resistance value, the PUF data readout also needs to be performed by comparing one resistive random access memory cell with a set resistance value.

For case one, for example, the readout circuit is configured to: the second resistance value Q2 is obtained, the resistance value of each first resistive random access memory cell in the high resistance state H1 is compared with the second resistance value Q2, and PUF data is determined and output based on the comparison result, that is, the readout circuit at this time realizes readout after PUF data recovery by comparing the self resistance state of the first resistive random access memory cell in the resistive random access memory array 120 with the set resistance value.

For example, in some examples, to read PUF data corresponding to a specific coordinate (x, y) in the resistive random access memory array 210 that has undergone a set operation using a read circuit, the method of operation is as follows: a set second resistance value Q2, for example 75kΩ; selecting a resistive random access memory cell located on coordinates (x, y) in the resistive random access memory array 210, recording as RRAMa, and comparing the resistance value RL1 of the RRAMa in the low resistance state L1 after undergoing a set operation with the second resistance value Q2; if RL1< Q2, sense circuit output 1; if RL1 > Q2, the sense circuit outputs 0.

It should be noted that, as is known from the foregoing, the lowest resistance states that can be achieved by the resistive random access memory cells having a resistance value of about 150kΩ or about 25kΩ after the initialization operation is completed, and then the lowest resistance states are also about 150kΩ or about 25kΩ, respectively, so that when PUF data is read after the set operation, the second resistance value Q2 (for example, 75kΩ) between the two lowest resistance states is selected such that the resistive random access memory cells in the first portion of the resistive random access memory array 210 (for example, the resistive random access memory cells having a resistance value of about 25kΩ after the initialization operation is completed) is smaller than or equal to the second resistance value Q2, the read circuit stably outputs 1, and the resistive random access memory cells in the second portion of the resistive random access memory array 210 (for example, the resistive random access memory cells having a resistance value of about 150kΩ after the initialization operation is completed) is larger than the second resistance value Q2, and the read circuit correspondingly outputs 0. The resistance change memory cell of the first portion after the second initializing operation has an initializing resistance value R2 (for example, about 25kΩ) smaller than a preset first resistance value Q1 (for example, 140kΩ), the output of the readout circuit is also 1, and the resistance change memory cell of the second portion after the first initializing operation has an initializing resistance value R1 (for example, about 150kΩ) larger than a preset first resistance value Q1, the output of the readout circuit is also 0. Finally, for case one, the PUF data read out by the read-out circuit after having undergone the hiding and restoring operation is consistent with the original PUF data formed, whereby embodiments of the present disclosure can accurately achieve PUF data restoration and reading.

It should be noted that, for the first case, the second resistance Q2 is not only required to be greater than or equal to the second set initialization value P2 and smaller than the first set initialization value P1, but is preferably also smaller than the first initialization resistance R1 of all the first resistive random access memory cells, which also means that the second resistance Q2 is smaller than the preset first resistance Q1 (as described above), and the second resistance Q2 is also pulled apart from the value of the first set initialization value P1 by a distance as much as possible, so as to more effectively achieve PUF data recovery with low error rate. For example, the first set initialization value P1 is 150kΩ, the preset first resistance value Q1 is 140kΩ, the second set initialization value P2 is 25kΩ, and the second resistance value Q2 is 75kΩ, which is, of course, merely exemplary and not limiting of the present disclosure.

For the first case, in some embodiments of the present disclosure, the lowest resistance state of the resistive random access memory cell is used to distinguish between different PUF data states, and the resistive random access memory cell is brought to the lowest resistance state through a set operation, so that the set voltage level during the set operation can be flexibly selected, the dependency of the set voltage level is low, and a great amount of training on the set voltage is not required.

For case two, for example, in some examples, the resume operation includes a set operation, the second control circuit 220 configured to: and respectively performing setting operation on each first resistance change memory cell and each second resistance change memory cell in the high resistance state H1' according to a third resistance value Q3 to reduce each first resistance change memory cell and each second resistance change memory cell from the high resistance state H1' to a second resistance state (also called as a low resistance state L1 ') respectively for recovering PUF data, wherein the third resistance value Q3 is at least larger than or equal to the second set initialization value P2 and smaller than the first set initialization value P1.

For case two, for example, in some examples, the readout circuitry is configured to: and comparing the resistance value of the first resistance change memory unit in the low resistance state L1 'with the resistance value of the corresponding second resistance change memory unit in the low resistance state L1', and determining and outputting PUF data based on the comparison result.

For the second case, for example, in some examples, in order to read out PUF data corresponding to a specific coordinate (x, y) in the resistive random access memory array 210 that has undergone a set operation with a read-out circuit, the operation method is as follows: selecting resistive random access memory units positioned on coordinates (x, y) of subarrays A and B, and respectively marking the resistive random access memory units as RRAMa and RRAMb; the resistance values of RRAMa in the low resistance state L1 'and RRAMb in the low resistance state L1' are respectively recorded as RLa and RLb, and RLa and RLb are compared; if RLa < RLb, the sense circuit outputs 1; if RLa > RLb, the sense circuit outputs 0.

It should be noted that, for the second case, the third resistance Q3 is not only greater than or equal to the second set initialization value P2 and smaller than the first set initialization value P1, but is preferably smaller than the first initialization resistance R1 of all the first resistive random access memory cells and the first initialization resistance R1' of all the second resistive random access memory cells (as described above), and the third resistance Q3 is further separated from the value of the first set initialization value P1 by a few differences and is closer to the second set initialization value P2, so as to more effectively achieve PUF data recovery with low error rate. For example, the first set initialization value P1 is 150kΩ, the second set initialization value P2 is 25kΩ, and the third resistance value Q3 is 37.5kΩ, which, of course, is merely exemplary and not limiting of the present disclosure.

For the second case, in some embodiments of the present disclosure, the lowest resistance states of two resistive random access memory cells are utilized to distinguish between different PUF data states, and the resistive random access memory cells are brought to the lowest resistance states through a set operation, so that the set voltage level during the set operation can be flexibly selected, the dependency of the set voltage level is low, and a great deal of training on the set voltage is not required.

Fig. 11 is a flowchart of a PUF data recovery method provided in some embodiments of the present disclosure.

For the second case, for example, as shown in fig. 11, in order to set PUF data P corresponding to a specific coordinate (x, y) in the resistive random access memory array _x,y The method for performing the recovery operation by the second control circuit 220 is as follows: the resistive memory cells in the sub-arrays a and B at the coordinates (x, y) are selected and respectively denoted as RRAMa and RRAMb, and then the RRAMa and RRAMb are respectively subjected to the operations shown in fig. 11, i.e. the setting operation is performed at most N2 (for example, count=100), in an attempt to modulate the resistance values of RRAMa and RRAMb to be below 37.5kΩ, and put in a low resistance state, wherein 37.5kΩ is merely exemplary, not limiting the disclosure, and may be other resistance values, of course, 100 times herein is merely an example, and the embodiments of the disclosure are not limited thereto, and may be correspondingly adjusted according to practical situations.

It should be noted that, in the second case, according to the description of the initialization operation, for any one of the groups of RRAMa and RRAMb, one of them is initialized to 25kΩ and the other is initialized to 150kΩ only, so that after the setting operation, the resistance value of the resistive random access memory cell that was initialized to 25kΩ can be set to be less than the third resistance value Q3 (for example, less than 37.5kΩ) according to the setting requirement, but the resistance value of the other resistive random access memory cell can only reach around 150kΩ, and cannot be set to be less than the third resistance value Q3 (for example, less than 37.5kΩ) according to the setting requirement.

As can be seen from this, RRAMa can be set to 37.5kΩ or less according to the setting requirement, and the resistance value after RRAMb is set can only reach around 150kΩ, that is, RLa <37.5kΩ and rlb≡150kΩ, so RLa < RLb, at this time, the readout circuit can stably output 1 st. Furthermore, the RRAMa is initialized to the initializing resistance R2, e.g. about 25kΩ, after the second initializing operation, and the RRAMb is initialized to the initializing resistance R1, e.g. about 150kΩ, after the first initializing operation, and the reading result of the readout circuit is also 1 (as described above). Finally, for case two, the PUF data read out by the readout circuit after undergoing the hiding and restoring operation is identical to the original PUF data, whereby embodiments of the present disclosure can accurately achieve PUF data restoration and reading.

For case one or case two, for example, in some examples, the condition of the set operation may be: pulse width 800ms, BL voltage size 2.2V, WL voltage size 1.8V. In case two, the target value of the low resistance state is 37.5kΩ, that is, the third resistance value Q3 is 37.5kΩ. Of course, this is merely exemplary and is not limiting of the present disclosure, and other voltage conditions may be employed, and embodiments of the present disclosure are not intended to be exhaustive or redundant herein.

Some embodiments of the present disclosure describe in detail an electronic device 300 and its method of operation in terms of hiding PUF data and recovering PUF data, with reference to fig. 12-20.

Fig. 12 is a schematic block diagram of an electronic device 300 provided in some embodiments of the present disclosure.

As shown in fig. 12, at least one embodiment of the present disclosure provides an electronic device 300 including a resistive memory array 310 and a third control circuit 320, the resistive memory array 310 including a plurality of first resistive memory cells. For example, for any one of the resistive memory cells of the resistive memory array 310, the resistance value of the resistive memory cell can be artificially controlled by applying different pulses. It should be noted that, for the specific composition and functions of the resistive memory array 310 of the electronic device 300 according to the embodiment of the disclosure, reference may be made to the resistive memory array 110 of the electronic device 100, which is not described herein for clarity and brevity.

For example, in some examples, the third control circuit 320 may implement the initialization operation of the first control circuit 120, the reset operation of the first control circuit 120, and the set operation of the second control circuit 220, which are specifically referred to above and will not be described herein. In other words, at least one embodiment of the present disclosure implements the initialization operation, the reset operation, and the set operation by transmitting different control signals to the resistive memory cells of the resistive memory array, for example, in an actual product, an initialization circuit (corresponding to the initialization operation), a hidden circuit (corresponding to the reset operation), and a recovery circuit (corresponding to the set operation) are generally integrated into one circuit to form the third control circuit 320 described above. Of course, the third control circuit 320 of the embodiment of the present disclosure may also be designed to include three independent circuits, i.e., an initialization circuit, a hiding circuit, and a restoring circuit, to implement an initialization operation, a reset operation, and a set operation, respectively, according to the actual situation, which is not limited by the embodiment of the present disclosure.

In addition, it is understood that the first control circuit 120 includes an initialization circuit and a hidden circuit, the second control circuit 220 includes a recovery circuit, where the initialization circuit, the hidden circuit, and the recovery circuit correspond to the initialization operation, the reset operation, and the set operation described above, respectively, and in view of the fact that the specific circuit forms adopted to implement the initialization operation, the reset operation, and the set operation are not the emphasis of the embodiments of the present disclosure, those skilled in the art can implement the technical solutions of each example according to the related descriptions herein, and in order to ensure the clarity and conciseness of the description of the embodiments of the present disclosure, the embodiments of the present disclosure are not repeated herein.

Fig. 13 is a schematic block diagram of an electronic device 300 provided in further embodiments of the present disclosure.

In the following, the initialization circuit, the hiding circuit, and the restoring circuit are described as being integrated into one control circuit, and for the convenience of understanding the embodiments of the present disclosure, fig. 13 illustrates each of the initialization circuit, the hiding circuit, and the restoring circuit as an example, but it should be understood that this is only one schematic way and does not limit the embodiments of the present disclosure.

For case two (as described above), for example, as shown in fig. 13, the electronic device 300 includes the resistive memory array 310, the initialization circuit 321, the hiding circuit 322, the recovery circuit 323, and the readout circuit 330, wherein the resistive memory array 310 includes the sub-array a and the sub-array B.

Fig. 14 is a flowchart of an operation method of the electronic device 300 according to some embodiments of the present disclosure. For example, as shown in fig. 14, the operation method of the electronic device 300 includes steps S1 to S5.

S1, initializing operation;

for step S1, for example, in some examples, the initialization operations include a first initialization operation and a second initialization operation to form the original PUF data P _x,y The specific implementation method can refer to the related description, and is not repeated here.

S2, hiding operation;

for step S2, for example, in some examples, the hiding operation includes a resetting operation, and a specific implementation method thereof may refer to the foregoing related description, which is not described herein.

Step S3, acquiring a data access request, wherein the data access request is the original PUF data P _x,y An access request;

s4, recovering operation;

for step S4, for example, in some examples, after receiving the data access request, the corresponding data needs to be recovered in sequence, where the recovering operation includes a set operation, and a specific implementation method of the recovering operation may refer to the foregoing related description and will not be repeated herein.

Step S5, reading operation.

For step S5, for example, in some examples, after recovering the corresponding data, the data needs to be read out, where the read-out operation is to determine and output PUF data through comparing the resistance values, and a specific implementation method thereof may refer to the related description above and will not be described herein.

Fig. 15 is a flowchart of an operation method of an electronic device 300 according to further embodiments of the present disclosure.

For example, as shown in fig. 15, the operation method includes step S6: the hiding operation, i.e. the step S6 is added after the above step S5. For step S6, for example, in some examples, after the step S4 and the step S5 are performed in sequence according to the received data access request, a hiding operation is performed again, for example, a resetting operation is performed again on each resistive random access memory unit included in the resistive random access memory array to place the resistive random access memory unit in a high-resistance state to hide PUF data again, and in addition, a specific implementation method of the hiding operation in step S6 may refer to the related description above and will not be repeated here.

Fig. 16 is a schematic diagram of PUF data read out after an initialization operation provided by some embodiments of the present disclosure. Fig. 17 is a schematic diagram of PUF data read out after a concealment operation provided by some embodiments of the present disclosure. Fig. 18 is a schematic diagram of PUF data read out after a recovery operation provided by some embodiments of the present disclosure.

For example, as shown in fig. 16 to 18, the case of the read-out of PUF data of 512 bits in length after the initialization operation, the concealment operation, and the recovery operation is shown, respectively. For example, in fig. 16 to 18, the black dot indicates that the value of PUF data is 0, and the white dot indicates that the value of PUF data is 1.

In comparison, the display results of the black and white points in fig. 17 are different from the display results of the black and white points in fig. 16, for example, about 40% of the PUF data in fig. 17 is inconsistent with the original PUF data in fig. 16, i.e. the original PUF data is well hidden.

In comparison, the display results of the black and white points in fig. 18 are the same as those of the black and white points in fig. 16, i.e., the original PUF data is accurately restored.

Note that fig. 17 is an example for the second case, and that in fig. 17, there are not only black dots but also white dots, which exactly coincides with the above-described resistance values of the resistance change memory cells after the reset operation. It is also noted that for the case one example, the graphical result of the PUF data hiding is that all are black dots (not shown).

Fig. 19 is a schematic diagram illustrating comparison of PUF data hiding rate and PUF data hiding rate according to some embodiments of the present disclosure, and fig. 20 is a schematic diagram illustrating comparison of data error rate according to some embodiments of the present disclosure and data error rate according to other embodiments of the present disclosure, where the cycle number of fig. 19 and 20 refers to the number of cycles from a hiding operation to a recovering operation, and the embodiments of the present disclosure do not limit the cycle number.

For example, other schemes shown in fig. 19 and 20 may implement hiding and recovering PUF data by applying a set voltage and a reset voltage to the resistive memory array, which are very dependent on the magnitudes of the set voltage and the reset voltage, and may result in high design cost of the chip.

For example, as shown in fig. 19, when comparing and comparing the embodiments of the present disclosure and other schemes to effectively implement PUF data hiding, the embodiments of the present disclosure can effectively hide PUF data without relying on a placement voltage and a reset voltage, and the design cost of the chip is reduced.

For example, as shown in fig. 20, which illustrates a comparison of the data error rate of the embodiment of the disclosure with other schemes after PUF data recovery, it is understood by comparison that the embodiment of the disclosure is significantly improved in error rate compared with other schemes, and the data error rate of the embodiment of the disclosure is significantly lower than that of other schemes, and even can achieve 0 error rate within 10 cycles of hiding operation-recovery operation.

It should be noted that, for clarity and brevity of illustration, not all of the constituent elements of the electronic devices 100, 200, and 300 are given in the embodiments of the present disclosure. To achieve the necessary functionality of the electronic device to hide and/or recover PUF data, a person skilled in the art may provide, arrange other not shown constituent elements according to specific needs, as embodiments of the present disclosure are not limited thereto. It should also be noted that, although the above describes the electronic device as being divided into modules for respectively executing the corresponding processes, it is clear to those skilled in the art that the processes executed by the respective modules may also be executed without any specific division of the modules or without explicit demarcation between the respective modules.

Technical effects of the operation method of the electronic device in the different embodiments may refer to technical effects of the electronic device provided in the embodiments of the present disclosure, and are not described herein.

The following points need to be described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. An electronic device, comprising:

a resistive memory array including a plurality of first resistive memory cells;

a first control circuit, wherein the first control circuit is configured to:

according to a first set initialization value, performing a first initialization operation on each of the plurality of first resistive random access memory units to obtain a first initialization resistance value, so as to initialize each of the plurality of first resistive random access memory units to have a first resistance value change interval;

In response to a first initialization resistance value of a currently compared first resistive random access memory cell of the plurality of first resistive random access memory cells being less than or equal to the reference resistance value, performing a second initialization operation on the currently compared first resistive random access memory cell according to a second set initialization value, such that the currently compared first resistive random access memory cell is reduced from the first initialization resistance value to a second initialization resistance value,

initializing a resistance change interval of the first resistance change memory unit which is currently compared from the first resistance change interval to a second resistance change interval, and responding to that a first initialization resistance value of the first resistance change memory unit which is currently compared in the plurality of first resistance change memory units is larger than the reference resistance value, not performing a second initialization operation on the first resistance change memory unit which is currently compared and still has the first resistance change interval for forming physical unclonable function data, wherein the first set initialization value is larger than the second set initialization value;

resetting each of the plurality of first resistive memory cells to place each of the plurality of first resistive memory cells in a first resistance state having a resistance value greater than the first initialization resistance value for hiding the physical unclonable function data;

A second control circuit, wherein the second control circuit is configured to:

performing a restore operation on each of the plurality of first resistive random access memory cells on which the reset operation has been performed, for restoring the physical unclonable function data,

wherein the recovery operation includes a set operation, the second control circuit configured to: and performing the set operation on each first resistive memory cell in the first resistive state according to a second resistance value to reduce each first resistive memory cell from the first resistive state to a second resistive state for recovering the physical unclonable function data, wherein the second resistance value is greater than or equal to the second set initialization value and less than the first set initialization value.

2. The electronic device of claim 1, wherein the reference resistance is a predetermined first resistance.

3. The electronic device of claim 2, wherein the predetermined first resistance value is greater than the second initialization resistance value.

4. The electronic device of claim 2, wherein the resistive memory array further comprises a second resistive memory cell,

The first control circuit is further configured to:

according to the first set initialization value, performing the first initialization operation on the second resistance change memory unit to obtain a third initialization resistance value;

and selecting the third initialization resistance value as the reference resistance value.

5. The electronic device of claim 1, further comprising a readout circuit, wherein the readout circuit is configured to:

acquiring the second resistance value;

and comparing the resistance value of each first resistance change memory unit in the second resistance state with the second resistance value, and determining and outputting the physical unclonable function data based on the comparison result.

6. An electronic device, comprising:

a resistive memory array including a plurality of first resistive memory cells;

a first control circuit, wherein the first control circuit is configured to:

wherein the resistive memory array further comprises a plurality of second resistive memory cells, each of the plurality of first resistive memory cells having a corresponding one of the second resistive memory cells, the first control circuit further configured to: according to the first set initialization value, performing the first initialization operation on each of the plurality of second resistive random access memory units to obtain a fourth initialization resistance value; for each of the plurality of first resistive random access memory cells, selecting a fourth initialization resistance value of the corresponding second resistive random access memory cell as the reference resistance value;

Wherein the first control circuit is further configured to: performing a reset operation on each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells to place each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells in a first resistance state having a resistance value greater than the first initialization resistance value and the fourth initialization resistance value for hiding the physical unclonable function data;

a second control circuit, wherein the second control circuit is configured to:

performing a restore operation to each of the plurality of first resistive switching memory cells to which the hiding operation has been performed,

for recovering the physical unclonable function data, the hiding operation comprising the resetting operation; wherein the recovery operation includes a set operation, the second control circuit configured to: and respectively performing setting operation on each first resistance change memory unit and each second resistance change memory unit in the first resistance state according to a third resistance value so as to respectively reduce each first resistance change memory unit and each second resistance change memory unit from the first resistance state to the second resistance state for recovering the physical unclonable function data, wherein the third resistance value is larger than or equal to the second set initialization value and smaller than the first set initialization value.

7. The electronic device of claim 6, wherein the plurality of first resistive memory cells are in one-to-one correspondence with the plurality of second resistive memory cells.

8. The electronic device of claim 6, further comprising a readout circuit, wherein,

the readout circuit is configured to:

and comparing the resistance value of the first resistance change memory unit in the second resistance state with the corresponding resistance value of the second resistance change memory unit in the second resistance state, and determining and outputting the physical unclonable function data based on a comparison result.

9. A method of operation of an electronic device, comprising:

according to a first set initialization value, performing a first initialization operation on each of a plurality of first resistance change memory units included in a resistance change memory array to obtain a first initialization resistance value, so as to initialize each of the plurality of first resistance change memory units to have a first resistance change interval;

in response to a first initialization resistance value of a currently compared first resistive memory cell of the plurality of first resistive memory cells being less than or equal to the reference resistance value, performing a second initialization operation on the currently compared first resistive memory cell according to a second set initialization value such that the currently compared first resistive memory cell decreases from the first initialization resistance value to a second initialization resistance value to initialize a resistance value change interval of the currently compared first resistive memory cell from the first resistance value change interval to a second resistance value change interval, and in response to a first initialization resistance value of the currently compared first resistive memory cell of the plurality of first resistive memory cells being greater than the reference resistance value, performing no second initialization operation on the currently compared first resistive memory cell and the currently compared first resistive memory cell still having the first resistance value change interval for forming a physical unclonable function, wherein the first initialization value is greater than the second set value;

performing a restore operation on each of the plurality of first resistive random access memory cells on which the reset operation has been performed for restoring the physical unclonable function data;

wherein performing a recovery operation on each of the plurality of first resistive random access memory cells on which the reset operation has been performed for recovering the physical unclonable function data, comprises:

and performing a set operation on each first resistive memory cell in the first resistive state according to a second resistance value to reduce each first resistive memory cell from the first resistive state to a second resistive state for recovering the physical unclonable function data, wherein the second resistance value is greater than or equal to the second set initialization value and less than the first set initialization value.

10. The method of claim 9, wherein the reference resistance is a predetermined first resistance.

11. The method of operation of claim 10, wherein the predetermined first resistance value is greater than the second initialization resistance value.

12. The method of operation of claim 9, further comprising: reading the recovered physical unclonable function data,

wherein reading the recovered physical unclonable function data comprises:

acquiring the second resistance value;

13. The method of operation of claim 12, further comprising: after the recovered physical unclonable function data is read, performing a reset operation on each resistive random access memory unit included in the resistive random access memory array again so as to place each resistive random access memory unit in the resistive random access memory array in the first resistive state for hiding the physical unclonable function data.

14. A method of operation of an electronic device, comprising:

Wherein in response to the resistive memory array further comprising a plurality of second resistive memory cells and each of the plurality of first resistive memory cells having a corresponding one of the second resistive memory cells, further comprising: performing the first initializing operation on each of the plurality of second resistive random access memory units according to the first set initializing value to obtain a fourth initializing resistance value; for each of the plurality of first resistive random access memory cells, selecting a fourth initialization resistance value of the corresponding second resistive random access memory cell as the reference resistance value;

the operation method further comprises the following steps: performing a reset operation on each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells to place each of the plurality of first resistive memory cells and each of the plurality of second resistive memory cells in a first resistance state having a resistance value greater than the first initialization resistance value and the fourth initialization resistance value for hiding the physical unclonable function data;

the operation method further comprises the following steps: performing a recovery operation on each of the plurality of first resistive switching memory cells on which a hiding operation has been performed for recovering the physical unclonable function data, the hiding operation including the reset operation;

Wherein performing a recovery operation on each of the plurality of first resistive random access memory cells on which the hiding operation has been performed for recovering the physical unclonable function data, comprises:

and respectively performing setting operation on each first resistance change memory unit in the first resistance state and each second resistance change memory unit in the first resistance state according to a third resistance value so as to respectively reduce each first resistance change memory unit and each second resistance change memory unit from the first resistance state to a second resistance state for recovering the physical unclonable function data, wherein the third resistance value is larger than or equal to the second set initialization value and smaller than the first set initialization value.

15. The method of operation of claim 14, wherein the first plurality of resistive memory cells is in one-to-one correspondence with the second plurality of resistive memory cells.

16. The method of operation of claim 14, further comprising: reading the recovered physical unclonable function data,

wherein reading the recovered physical unclonable function data comprises:

17. The method of operation of claim 16, further comprising: after the recovered physical unclonable function data is read, performing a reset operation on each resistive random access memory unit included in the resistive random access memory array again so as to place each resistive random access memory unit in the resistive random access memory array in the first resistive state for hiding the physical unclonable function data.