CN112838092A - Preparation method of three-dimensional memory - Google Patents
Preparation method of three-dimensional memory Download PDFInfo
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- CN112838092A CN112838092A CN202110300830.6A CN202110300830A CN112838092A CN 112838092 A CN112838092 A CN 112838092A CN 202110300830 A CN202110300830 A CN 202110300830A CN 112838092 A CN112838092 A CN 112838092A
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- 230000015654 memory Effects 0.000 title claims abstract description 109
- 238000002360 preparation method Methods 0.000 title abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 145
- 238000005530 etching Methods 0.000 claims abstract description 81
- 230000002093 peripheral effect Effects 0.000 claims abstract description 59
- 238000003860 storage Methods 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 238000001039 wet etching Methods 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims description 184
- 238000000034 method Methods 0.000 claims description 78
- 239000007788 liquid Substances 0.000 claims description 21
- 239000003054 catalyst Substances 0.000 claims description 20
- 230000000903 blocking effect Effects 0.000 claims description 15
- 229910052709 silver Inorganic materials 0.000 claims description 14
- 239000004332 silver Substances 0.000 claims description 14
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000004528 spin coating Methods 0.000 claims description 10
- 239000004793 Polystyrene Substances 0.000 claims description 8
- 229920002223 polystyrene Polymers 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 6
- 239000002346 layers by function Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000000354 decomposition reaction Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- -1 silver ions Chemical class 0.000 claims description 4
- 230000008569 process Effects 0.000 description 28
- 238000010586 diagram Methods 0.000 description 25
- 239000000243 solution Substances 0.000 description 10
- 238000000227 grinding Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 150000001298 alcohols Chemical class 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 239000004327 boric acid Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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Abstract
The application provides a preparation method of a three-dimensional memory, wherein the preparation method specifically comprises the following steps: an initial three-dimensional memory is provided and comprises a first substrate, an array storage layer, a peripheral circuit layer and a second substrate which are arranged in a stacking mode, wherein the array storage layer and the peripheral circuit layer are located between the first substrate and the second substrate. And forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory part, and exposing the surface of one side of the first substrate, which is far away from the array memory layer. At least a portion of the first substrate is removed by wet etching. According to the preparation method provided by the application, one surface of the first substrate to be removed subsequently is exposed, and the other surface is protected by the etching barrier layer. Therefore, at least part of the first substrate can be removed only by wet etching, so that the purpose of the application is achieved, the preparation difficulty is reduced, and the preparation cost is reduced.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a preparation method of a three-dimensional memory.
Background
The three-dimensional memory has low power consumption, light weight and belongs to a nonvolatile memory product with excellent performance, and the three-dimensional memory is more and more widely applied to electronic products. But at the same time, the expectation and the demand of users for three-dimensional memories are also higher and higher. For example, currently, a three-dimensional memory is usually manufactured by depositing an array memory layer on a first substrate, then depositing a peripheral circuit layer on a second substrate, then adhering the array memory layer and the peripheral circuit layer together, and finally removing the first substrate. However, the existing removal process is complicated and the removal cost is high.
Disclosure of Invention
In view of this, the present application provides a method for manufacturing a three-dimensional memory, which is characterized by comprising:
providing an initial three-dimensional memory, wherein the initial three-dimensional memory comprises a first substrate, an array storage layer, a peripheral circuit layer and a second substrate which are arranged in a stacking mode, and the array storage layer and the peripheral circuit layer are located between the first substrate and the second substrate;
forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory part, and exposing the surface of one side of the first substrate, which is far away from the array memory layer; and
and removing at least part of the first substrate by a wet etching method.
According to the preparation method provided by the application, after the surfaces of the array storage layer and the peripheral circuit layer are connected together, the etching barrier layer covering the peripheral side face of the initial three-dimensional storage part is formed, and one side surface of the first substrate, which is far away from the array storage layer, is exposed. It is also understood that one surface of the first substrate that is to be subsequently removed is exposed, while the other surface is protected by the etch stop layer. The etching barrier layer can prevent other layer structures of the initial three-dimensional memory from being corroded by subsequent etching liquid, and then at least part of the first substrate can be removed only through wet etching, so that the purpose of the application is achieved.
In summary, compared with the prior art in which grinding is performed first, in the preparation method of wet etching, the preparation method provided by the application can reduce the preparation difficulty and reduce the preparation cost.
Wherein the removing at least a part of the first substrate by a wet etching method comprises:
removing at least part of the first substrate by a wet etching method; wherein the etching liquid comprises hydrogen fluoride, hydrogen peroxide and water.
Wherein the removing at least a part of the first substrate by a wet etching method comprises:
removing at least part of the first substrate by a wet etching method; the etching liquid also comprises a catalyst, and the catalyst comprises silver.
Before removing at least part of the first substrate by a wet etching method, the method further comprises the following steps:
adding a solution containing silver ions into the etching solution; or forming a catalyst layer covering the surface of the first substrate on the side away from the array storage layer, wherein the material of the catalyst layer comprises silver.
The step of forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory part and exposing the surface of the first substrate, which is far away from the array memory layer, comprises the following steps:
providing a base platform, arranging the initial three-dimensional memory on the base platform, and enabling one side surface of the first substrate, which is far away from the array memory layer, to abut against the base platform;
and forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory part, and exposing the surface of one side of the first substrate, which is far away from the array memory layer.
Wherein forming an etch stop layer covering a peripheral side surface of the initial three-dimensional memory portion comprises:
and providing etching blocking liquid, and spin-coating the etching blocking liquid to the surface of one side of the second substrate, which is far away from the peripheral circuit layer, by adopting a spin-coating method so as to form an etching blocking layer covering the peripheral side of the initial three-dimensional memory part.
The step of forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory part and exposing the surface of the first substrate, which is far away from the array memory layer, comprises the following steps:
forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory;
and removing the etching barrier layer on the surface of one side of the first substrate, which is far away from the array storage layer, so as to expose the surface of one side of the first substrate, which is far away from the array storage layer.
Wherein forming an etch stop layer covering a peripheral side surface of the initial three-dimensional memory portion comprises:
forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory part; the material of the etching barrier layer comprises polystyrene.
Wherein, after removing at least part of the first substrate by wet etching, the method further comprises:
removing the etching barrier layer by adopting a high-temperature decomposition method; or removing the etching barrier layer by adopting a dry etching method.
When removing part of the first substrate, after removing the etching barrier layer, the method further comprises:
and flattening the surface of one side of the first substrate, which faces away from the array storage layer.
The array storage layer comprises a step structure arranged on one side of the first substrate; a flat layer covering the substrate and the step structure; a conductive member penetrating the flat layer and connecting the substrate and the stepped portion; when part of the first substrate is removed by a wet etching method, after the removing the etching barrier layer, the method further comprises:
forming a through hole penetrating through the first substrate to expose the conductive member;
forming an electric connecting piece covering the through hole, and connecting the electric connecting piece with the conductive piece; and
and forming a functional layer covering the first substrate and the electric connecting piece.
Drawings
In order to more clearly explain the technical solution in the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be described below.
Fig. 1 is a process flow diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 2-4 are schematic diagrams corresponding to S100, S200, and S300 in fig. 1, respectively.
Fig. 5 is a process flow diagram included in S300 according to an embodiment of the present disclosure.
Fig. 6 is a process flow diagram of S300 in another embodiment of the present application.
Fig. 7 is a process flow diagram included prior to S300 in an embodiment of the present application.
Fig. 8 is a schematic view of fig. 7 when a catalyst layer is formed.
Fig. 9 is a process flow diagram included in S200 according to an embodiment of the present disclosure.
Fig. 10-11 are schematic diagrams corresponding to S210 and S220 in fig. 9, respectively.
Fig. 12 is a flowchart of a process included in S220 according to an embodiment of the present disclosure.
Fig. 13 is a process flow diagram included in S200 according to another embodiment of the present disclosure.
Fig. 14-15 are schematic diagrams corresponding to S230 and S240 in fig. 13, respectively.
Fig. 16 is a process flow diagram included after S300 in an embodiment of the present application.
Fig. 17 is a process flow diagram included after S300 in another embodiment of the present application.
Fig. 18 is a process flow diagram included after S300 in yet another embodiment of the present application.
Fig. 19-21 are schematic diagrams corresponding to S350, S360, and S370 in fig. 18, respectively.
Description of reference numerals:
the memory comprises a three-dimensional memory-1, an initial three-dimensional memory-2, a first substrate-10, a second substrate-20, an array storage layer-30, a step structure-31, a NAND string-32, an array common source-33, a flat layer-34, a conductive piece-35, a peripheral circuit layer-40, an etching barrier layer-50, a base station-60, a catalyst layer-70, a through hole-80, an electric connector-90 and a functional layer-100.
Detailed Description
The following is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications are also considered as the protection scope of the present application.
Before the technical solutions of the present application are introduced, the technical problems in the related art will be described in detail.
The three-dimensional memory has low power consumption, light weight and belongs to a nonvolatile memory product with excellent performance, and the three-dimensional memory is more and more widely applied to electronic products. But at the same time, the expectation and the demand of users for three-dimensional memories are also higher and higher. As the number of layers of the three-dimensional memory is gradually increased, the manufacturing method of the three-dimensional memory is also greatly changed. For example, at present, a three-dimensional memory is generally manufactured by depositing an array memory layer on a first substrate, then depositing a peripheral circuit layer on a second substrate, and then bonding the surface of the array memory layer and the surface of the peripheral circuit layer together, rather than sequentially depositing each layer structure on one substrate. Finally, at least part of the first substrate is removed. The currently employed removal processes generally involve grinding to achieve rapid removal; wet etching to achieve the purpose of fine removal, and chemical mechanical polishing to achieve the purpose of planarization. However, the above-mentioned removal process has many steps and the cost of the grinding process is high, so that the whole removal process is complicated and the cost is high.
In view of the above, in order to solve the above problems, the present application provides a method for manufacturing a three-dimensional memory. Referring to fig. 1 to 4 together, fig. 1 is a process flow diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. Fig. 2-4 are schematic diagrams corresponding to S100, S200, and S300 in fig. 1, respectively. The present embodiment provides a method for manufacturing a three-dimensional memory 1, including S100, S200, and S300. The details of S100, S200, and S300 are as follows.
Referring to fig. 2 and S100, an initial three-dimensional memory 2 is provided, where the initial three-dimensional memory 2 includes a first substrate 10, an array memory layer 30, a peripheral circuit layer 40, and a second substrate 20, which are stacked, and the array memory layer 30 and the peripheral circuit layer 40 are located between the first substrate 10 and the second substrate 20.
The present embodiment may first provide an initial three-dimensional memory 2. Here, the initial three-dimensional memory 2 refers to a partial structure of the three-dimensional memory 1. After the preparation method provided by the embodiment, other subsequent preparation processes can be provided, and the embodiment only provides preparation process steps related to the application. Specifically, the initial three-dimensional memory 2 includes a first substrate 10, a second substrate 20, an array storage layer 30, and a peripheral circuit layer 40. Wherein the array memory layer 30 and the peripheral circuit layer 40 are initially separately disposed on the first substrate 10 and the second substrate 20. For example, the array memory layer 30 is disposed on one side of the first substrate 10, and the peripheral circuit layer 40 is disposed on one side of the second substrate 20, so as to facilitate preparation of the array memory layer 30 and the peripheral circuit layer 40. In addition, the array storage layer 30 and the peripheral circuit layer 40 are only a general term, and the array storage layer 30 and the peripheral circuit layer 40 further include a plurality of complex layer structures, taking the array storage layer 30 as an example, the array storage layer 30 includes a step structure 31 disposed on the first substrate 10, NAND strings 32 penetrating the step structure 31, an array common source 33, a flat layer 34, a conductive member 35, and the like.
After the array memory layer 30 and the peripheral circuit layer 40 are finally prepared, the array memory layer 30 and the peripheral circuit layer 40 may be bonded together in a face-to-face manner, and the specific bonding method is not limited in this embodiment.
Alternatively, the first substrate 10 and the second substrate 20 may include a Silicon substrate, a Germanium substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like.
Referring to fig. 3, S200, an etching stop layer 50 is formed to cover a peripheral side surface of a portion of the initial three-dimensional memory 2 and expose a side surface of the first substrate 10 facing away from the array memory layer 30.
As can be seen from the above, since subsequent components are required to be further prepared on the array storage layer 30, at least a portion of the first substrate 10 on the array storage layer 30 needs to be thinned and removed. The related art generally needs to grind before wet method, which is not only long but also high in cost. For this purpose, the present embodiment may form an etching barrier layer 50 covering a partial circumferential side surface of the initial three-dimensional memory 2, and expose a side surface of the first substrate 10 facing away from the array memory layer 30.
The etching barrier layer 50 can effectively protect each structure on the peripheral side of the initial three-dimensional memory 2, and prevent other layer structures of the initial three-dimensional memory 2 from being corroded by subsequent etching liquid. In addition, the etching stop layer 50 does not cover the entire peripheral side of the three-dimensional memory 1, and since the first substrate 10 needs to be removed later, the surface of the first substrate 10 facing away from the array storage layer 30 does not need to be covered with the etching stop layer 50. As to how to form the etching stop layer 50 on the peripheral side of the initial three-dimensional memory 2 and expose the surface of the first substrate 10 facing away from the array memory layer 30, the present application will be described in detail later.
Referring to fig. 4, S300, at least a portion of the first substrate 10 is removed by wet etching.
After the etching stop layer 50 for protecting the initial three-dimensional memory 2 is prepared, the present embodiment may further remove at least a portion of the first substrate 10 by etching, so as to achieve the purpose of the present application. It can be understood that the wet etching method is adopted in the embodiment to replace the grinding and wet etching method in the related art, so that the time is reduced, the cost is reduced, and the damage to the initial three-dimensional memory 2 caused by the acting force during grinding can be removed. In addition, this embodiment mode is illustrated in which a portion of the first substrate 10 is removed by wet etching.
In summary, compared with the prior art in which grinding is performed first, in the preparation method of wet etching, the preparation method provided by the application can reduce the preparation difficulty and reduce the preparation cost.
Referring to fig. 5, fig. 5 is a process flow diagram included in S300 according to an embodiment of the present disclosure. In this embodiment, the step S300 "of removing at least a portion of the first substrate 10" by wet etching includes the step S310. The details of S310 are as follows.
S310, removing at least part of the first substrate 10 by a wet etching method; wherein the etching liquid comprises hydrogen fluoride, hydrogen peroxide and water.
In this embodiment, the etching solution may include hydrogen fluoride, hydrogen peroxide, and water. The first substrate 10 can be effectively removed using hydrogen fluoride, hydrogen peroxide, and water, and the silicon substrate can be more effectively prevented from reacting with hydrogen fluoride, which is a product of the etching liquid, by using the etching stopper layer 50.
Referring to fig. 6, fig. 6 is a process flow diagram included in S300 according to another embodiment of the present disclosure. In this embodiment, the step S300 "of removing at least a portion of the first substrate 10" by wet etching includes the step S320. The details of S320 are as follows.
S320, removing at least part of the first substrate 10 by a wet etching method; the etching liquid also comprises a catalyst, and the catalyst comprises silver.
The embodiment can also add silver catalyst into the etching liquid, the silver is added to etch the whole body along the (100) crystal orientation of silicon, and the etching speed of the silicon is increased, so that the etching speed is increased, and the removal effect is improved.
Optionally, the material of the etching barrier layer includes polystyrene. In this embodiment, polystyrene can be used as the material of the etching stopper layer. Wherein the characteristic temperature of the polystyrene is as follows: the brittle temperature is about-30 ℃, the glass transition temperature is 80-105 ℃, the melting temperature is 140-180 ℃, and the decomposition temperature is more than 300 ℃. Because the mechanical property of the polystyrene is obviously reduced along with the rise of the temperature and the heat resistance is poor, the continuous use temperature is about 60 ℃, and the maximum temperature is not more than 80 ℃. Polystyrene is resistant to various alkalis, salts and aqueous solutions, is stable to lower alcohols and certain acids (such as sulfuric acid, phosphoric acid, boric acid, hydrochloric acid with the mass fraction of 10-30%, acetic acid with the mass fraction of 1-25% and formic acid with the mass fraction of 1-90%), but can be damaged by concentrated nitric acid and other oxidants. Thus, the polystyrene may effectively comprise the initial three-dimensional memory 2.
Referring to fig. 7-8 together, fig. 7 is a process flow diagram included before S300 in an embodiment of the present application. Fig. 8 is a schematic view of fig. 7 when a catalyst layer is formed. In this embodiment, before the step S300 "removing at least a part of the first substrate 10" by wet etching, the method further includes a step S290. S290 is described in detail below.
S290, adding a solution containing silver ions into the etching solution; or forming a catalyst layer 70 covering the surface of the first substrate 10 on the side away from the array storage layer 30, wherein the material of the catalyst layer 70 comprises silver.
The above describes that silver catalyst can be added to the etching solution to improve the reaction efficiency. This embodiment describes two methods of adding the catalyst silver. In one implementation, a solution containing silver ions may be added directly to the etching solution. In a second implementation, a catalyst layer 70 may be formed covering a surface of the first substrate 10 facing away from the array storage layer 30, i.e. the catalyst layer 70 is formed directly on the surface of the first substrate 10 (as shown in fig. 8).
Referring to fig. 9-11 together, fig. 9 is a process flow diagram included in S200 according to an embodiment of the present disclosure. Fig. 10-11 are schematic diagrams corresponding to S210 and S220 in fig. 9, respectively. In this embodiment, S200 "forming the etching stop layer 50 covering a part of the peripheral side surface of the initial three-dimensional memory 2 and exposing a side surface of the first substrate 10 facing away from the array memory layer 30" includes S210 and S220. The details of S210 and S220 are as follows.
Referring to fig. 10, S210, a base stage 60 is provided, the initial three-dimensional memory 2 is disposed on the base stage 60, and a side surface of the first substrate 10 facing away from the array storage layer 30 abuts against the base stage 60.
Referring to fig. 11, S220, an etching stop layer 50 is formed to cover a peripheral side surface of a portion of the initial three-dimensional memory 2 and expose a side surface of the first substrate 10 facing away from the array memory layer 30.
As described above, the present application may form an etch stop layer 50 covering a portion of the peripheral side of the initial three-dimensional memory 2. Thus, two specific implementations are presented in this application. In the first implementation manner of the present application, the base stage 60 may be provided, and then a side surface of the first substrate 10 facing away from the array storage layer 30 in the initial three-dimensional memory 2 is abutted to the base stage 60, even if a side surface of the first substrate 10 facing away from the array storage layer 30 is tightly attached to the base stage 60. An etch stop layer 50 may then be formed covering a portion of the peripheral side of the initial three-dimensional memory 2. Because the surface of the first substrate 10 facing away from the array storage layer 30 is closely attached by the base 60, the surface of the first substrate 10 facing away from the array storage layer 30 does not form the etching barrier layer 50, and the surface of the first substrate 10 facing away from the array storage layer 30 can be exposed. Finally, the glass is turned over by 180 degrees from top to bottom.
Referring to fig. 12, fig. 12 is a flowchart illustrating a process included in S220 according to an embodiment of the present disclosure. In this embodiment, the step S220 "of forming the etching stopper layer 50" to cover a part of the peripheral surface of the initial three-dimensional memory 2 "includes a step S221. The details of S221 are as follows.
S221, providing an etching blocking liquid, and spin-coating the etching blocking liquid onto a surface of the second substrate 20 away from the peripheral circuit layer 40 by using a spin-coating method to form an etching blocking layer 50 covering a partial peripheral surface of the initial three-dimensional memory 2.
In a first implementation, the etch stop layer 50 is formed using a spin coating process. And etching blocking liquid can be utilized, and spin coating is carried out on the etching blocking liquid by adopting a spin coating method until the surface of one side of the second substrate 20, which is far away from the peripheral circuit layer 40, is coated, and in the continuous spin coating process, after the etching blocking liquid is filled in the surface of one side of the second substrate 20, which is far away from the peripheral circuit layer 40, the etching blocking liquid flows downwards from the periphery due to gravity, so that the etching blocking layer 50 covering the side edge is formed. And because the surface of one side of the first substrate 10 departing from the array storage layer 30 is tightly attached to the base 60, the etching blocking liquid flowing to the bottom cannot cover the surface of one side of the first substrate 10 departing from the array storage layer 30, so that the purpose of the application is achieved.
Referring to fig. 13-15 together, fig. 13 is a process flow diagram included in S200 according to another embodiment of the present disclosure. Fig. 14-15 are schematic diagrams corresponding to S230 and S240 in fig. 13, respectively. In this embodiment, S200 "forming the etching stop layer 50 covering a part of the peripheral side surface of the initial three-dimensional memory 2 and exposing a side surface of the first substrate 10 facing away from the array memory layer 30" includes S230 and S240. The details of S230 and S240 are as follows.
Referring to fig. 14, S230, an etching stop layer 50 is formed to cover the peripheral side of the initial three-dimensional memory 2.
Referring to fig. 15, in S240, the etch stop layer 50 on the surface of the first substrate 10 away from the array storage layer 30 is removed to expose the surface of the first substrate 10 away from the array storage layer 30.
In a second implementation manner provided by the present application, an etching stop layer 50 covering all peripheral sides of the initial three-dimensional memory 2 may be formed first, and then the etching stop layer 50 on a side surface of the first substrate 10 facing away from the array memory layer 30 is removed to expose a side surface of the first substrate 10 facing away from the array memory layer 30. This can reduce the process difficulty of forming the etch stop layer 50.
Referring to fig. 16, fig. 16 is a process flow diagram included after S300 according to an embodiment of the present disclosure. In this embodiment, after S300 "removing at least a part of the first substrate 10" by wet etching, S330 is further included. However, S330 is rarely detailed as follows.
S330, removing the etching barrier layer 50 by adopting a high-temperature decomposition method; or removing the etching barrier layer by adopting a dry etching method.
After removal of at least part of the first substrate 10, the fabrication of subsequent components can be continued, while the etch stop layer 50 is not yet functional and can therefore be removed. The present embodiment may employ a pyrolysis method at the time of removal; to decompose the etch stop layer 50. Alternatively, dry etching is used to etch away the etch-barrier layer 50.
Referring to fig. 17, fig. 17 is a flowchart of a process included after S300 according to another embodiment of the present disclosure. In this embodiment, when removing a portion of the first substrate 10, after removing the etch stop layer 50 "in S300", S340 is further included. However, S340 is very rarely detailed as follows.
And S340, flattening one side surface of the first substrate 10, which faces away from the array storage layer 30.
After the etching barrier layer 50 is removed and before the subsequent structural members are prepared, the surface of the first substrate 10 after the removal of a part of the first substrate 10 may be subjected to a planarization operation, so that the surface of the first substrate 10 on the side away from the array storage layer 30 is more flat, and favorable conditions are provided for the preparation of the subsequent structural members.
Referring to fig. 18-21 together, fig. 18 is a process flow diagram included after S300 in another embodiment of the present application. Fig. 19-21 are schematic diagrams corresponding to S350, S360, and S370 in fig. 18, respectively. In this embodiment, the array memory layer 30 includes a step structure 31 provided on the first substrate 10 side; a flat layer 34 covering the substrate and the step structure 31; a conductive member 35 penetrating the planarization layer 34 and connecting the substrate and the stepped portion; when a portion of the first substrate 10 is removed by wet etching, after "removing the etch stop layer 50", S350, S360, and S370 are further included. The details of S350, S360, and S370 are as follows.
Referring to fig. 19, S350, a through hole 80 is formed through the first substrate 10 to expose the conductive member 35.
Referring to fig. 20, in S360, an electrical connection member 90 covering the through hole 80 is formed, and the electrical connection member 90 is connected to the conductive member 35.
Referring to fig. 21, S370, a functional layer 100 is formed to cover the first substrate 10 and the electrical connector 90.
After removing the etch stop layer 50, the subsequent steps may be performed, and since this embodiment removes a portion of the first substrate 10, a portion of the array memory layer 30 may remain on the array memory layer 30, so that the array memory layer 30 may be connected to a structure subsequently fabricated on the first substrate 10. Therefore, the present embodiment may first form the via hole 80 penetrating the first substrate 10, thereby exposing the conductive member 35. An electrical connector 90 is then formed overlying the via 80 and the electrical connector 90 is connected to the conductive member 35. Finally, a functional layer 100 is formed covering the first substrate 10 and the electrical connector 90. This electrically connects the array storage layer 30 to the functional layer 100 via the electrical connector 90.
The foregoing detailed description has provided for the embodiments of the present application, and the principles and embodiments of the present application have been presented herein for purposes of illustration and description only and to facilitate understanding of the methods and their core concepts; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (11)
1. A method for preparing a three-dimensional memory, the method comprising:
providing an initial three-dimensional memory, wherein the initial three-dimensional memory comprises a first substrate, an array storage layer, a peripheral circuit layer and a second substrate which are arranged in a stacking mode, and the array storage layer and the peripheral circuit layer are located between the first substrate and the second substrate;
forming an etching barrier layer covering the initial three-dimensional memory, and exposing the surface of one side of the first substrate, which is far away from the array memory layer; and
and removing at least part of the first substrate by a wet etching method.
2. The method of claim 1, wherein removing at least a portion of the first substrate by wet etching comprises:
removing at least part of the first substrate by a wet etching method; wherein the etching liquid comprises hydrogen fluoride, hydrogen peroxide and water.
3. The manufacturing method according to claim 2, wherein "removing at least part of the first substrate by wet etching" includes:
removing at least part of the first substrate by a wet etching method; the etching liquid also comprises a catalyst, and the catalyst comprises silver.
4. The method of manufacturing according to claim 3, further comprising, before removing at least part of the first substrate by wet etching:
adding a solution containing silver ions into the etching solution; or forming a catalyst layer covering the surface of the first substrate on the side away from the array storage layer, wherein the material of the catalyst layer comprises silver.
5. The method of claim 1, wherein forming an etch stop layer covering a peripheral side of the initial three-dimensional memory portion and exposing a side surface of the first substrate facing away from the array storage layer comprises:
providing a base platform, arranging the initial three-dimensional memory on the base platform, and enabling one side surface of the first substrate, which is far away from the array memory layer, to abut against the base platform;
and forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory part, and exposing the surface of one side of the first substrate, which is far away from the array memory layer.
6. The method of claim 5, wherein forming an etch stop layer covering a peripheral side of the initial three-dimensional memory portion comprises:
and providing etching blocking liquid, and spin-coating the etching blocking liquid to the surface of one side of the second substrate, which is far away from the peripheral circuit layer, by adopting a spin-coating method so as to form an etching blocking layer covering the peripheral side of the initial three-dimensional memory part.
7. The method of claim 1, wherein forming an etch stop layer covering a peripheral side of the initial three-dimensional memory portion and exposing a side surface of the first substrate facing away from the array storage layer comprises:
forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory;
and removing the etching barrier layer on the surface of one side of the first substrate, which is far away from the array storage layer, so as to expose the surface of one side of the first substrate, which is far away from the array storage layer.
8. The method of claim 1, wherein forming an etch stop layer covering a peripheral side of the initial three-dimensional memory portion comprises:
forming an etching barrier layer covering the peripheral side face of the initial three-dimensional memory part; the material of the etching barrier layer comprises polystyrene.
9. The method of manufacturing according to claim 1, further comprising, after "removing at least part of the first substrate by wet etching":
removing the etching barrier layer by adopting a high-temperature decomposition method; or removing the etching barrier layer by adopting a dry etching method.
10. The method according to claim 9, further comprising, after "removing the etch stopper" when removing part of the first substrate:
and flattening the surface of one side of the first substrate, which faces away from the array storage layer.
11. The method according to claim 9, wherein the array memory layer includes a step structure provided on one side of the first substrate; a flat layer covering the substrate and the step structure; a conductive member penetrating the flat layer and connecting the substrate and the stepped portion; when part of the first substrate is removed by a wet etching method, after the removing the etching barrier layer, the method further comprises:
forming a through hole penetrating through the first substrate to expose the conductive member;
forming an electric connecting piece covering the through hole, and connecting the electric connecting piece with the conductive piece; and
and forming a functional layer covering the first substrate and the electric connecting piece.
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