CN112836812B - Neural network based on floating gate transistor - Google Patents
Neural network based on floating gate transistor Download PDFInfo
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- CN112836812B CN112836812B CN202011638469.XA CN202011638469A CN112836812B CN 112836812 B CN112836812 B CN 112836812B CN 202011638469 A CN202011638469 A CN 202011638469A CN 112836812 B CN112836812 B CN 112836812B
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- 238000013528 artificial neural network Methods 0.000 title claims abstract description 15
- 210000002569 neuron Anatomy 0.000 claims abstract description 12
- 239000011664 nicotinic acid Substances 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 2
- 239000002210 silicon-based material Substances 0.000 claims 1
- 210000005036 nerve Anatomy 0.000 abstract description 7
- 210000003766 afferent neuron Anatomy 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000001953 sensory effect Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000013527 convolutional neural network Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Abstract
The invention provides a neural network based on a floating gate transistor, which comprises a multi-node input unit: the multi-node input unit comprises a multi-input floating gate transistor, wherein a plurality of grid input ends of the multi-input floating gate transistor are respectively connected with a plurality of external bionic sensor input signals, a source electrode is grounded, and a drain electrode is used as an output end of the neuron network. The invention provides a brand-new electronic afferent neuron realization architecture. The architecture is applied to a hardware nerve form neural network, realizes the conversion from an analog signal to a neuron signal, has the advantages of simple structure, multiple functions, low power consumption and the like, and is more suitable for the neuron network.
Description
Technical Field
The invention relates to the field of a neural network, in particular to a neural network based on a floating gate transistor.
Background
The neural network is an ideal choice for constructing an energy-efficient storage and calculation integrated data processing center as a next-generation neuromorphic calculation technology. To implement a sensory and computational integrated intelligent processing system, an efficient sensory information interface (biologically called an afferent nerve) needs to be built to establish real-time links between the data processing center and the sensors. However, the electronic afferent neurons constructed by adopting CMOS in the prior art have the problems of high power consumption, complex circuit structure and process and the like, and are difficult to be suitable for the novel nerve morphology neural network.
Disclosure of Invention
The invention aims to solve the technical problems of high power consumption, complex circuit structure and process and the like, and provides a nerve cell network based on a floating gate transistor, which is suitable for a novel nerve morphology nerve network.
In order to solve the above problems, the present invention provides a floating gate transistor-based neuron network comprising a multi-node input unit: the multi-node input unit comprises a multi-input floating gate transistor, wherein a plurality of grid input ends of the multi-input floating gate transistor are respectively connected with a plurality of external bionic sensor input signals, a source electrode is grounded, and a drain electrode is used as an output end of the neuron network.
The invention provides a brand-new electronic afferent neuron realization architecture. The architecture is applied to a hardware nerve form neural network, realizes the conversion from an analog signal to a neuron signal, has the advantages of simple structure, multiple functions, low power consumption and the like, and is more suitable for the neuron network.
Drawings
Fig. 1 is a schematic structural diagram of a neural network based on floating gate transistors according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an implementation of an electronic afferent neuron according to an embodiment of the present invention.
Fig. 3A and 3B are device structure diagrams of a floating gate transistor according to an embodiment of the present invention.
Detailed Description
The following describes in detail the embodiments of the floating gate transistor-based neural network provided by the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a neural network based on floating gate transistors according to an embodiment of the present invention, including a multi-node input unit. The multi-node input unit comprises a multi-input floating gate transistor, wherein a plurality of grid input ends of the multi-input floating gate transistor are respectively connected with a plurality of external bionic sensor input signals V 01、V02、……V0N, a source electrode is grounded, and a drain electrode is used as an output end U d(t) of the neuron network.
The multi-node input unit integrates information of the input signal V 01～V0N of the external bionic sensor to obtain the floating gate voltage VF of the floating gate transistor with multiple input ends, and the voltage is jointly given by the following combination with the structure shown in the figure 1
Where V 0 to V N are the floating gate voltages of each column of floating gate transistors, are weighted averages of the input voltages of each gate node, C 01～C0N is the parasitic capacitance between the floating gate and gate oxide of the first column of floating gate transistors, and the corresponding C N1～CNN is the parasitic capacitance between the floating gate and gate oxide of the nth column of floating gate transistors. The weighted average is that the floating gate voltage V F,C1～CN of the multi-input floating gate transistor is the parasitic capacitance between the gate oxide and the top layer silicon of each column of floating gate transistors.
When the floating gate voltage V F of the multi-input floating gate transistor is less than the threshold voltage V T, the multi-input floating gate transistor is not turned on; when the floating gate voltage V F reaches the threshold voltage V T of the multi-input floating gate transistor, the multi-input floating gate transistor begins to turn on. After the multi-input floating gate transistor is conducted, the voltage of the drain terminal is correspondingly increased, so that the information integration function of signals is realized.
Based on the above principle, the present embodiment provides a new implementation architecture of electronic afferent neurons, and the architecture diagram is shown in fig. 2. The architecture is applied to a hardware nerve form neural network, realizes the conversion from an analog signal to a neuron signal, has the advantages of simple structure, multiple functions, low power consumption and the like, and is more suitable for the neuron network.
In a specific embodiment, the multi-input floating gate transistor of the multi-node input unit is a multi-input floating gate transistor using a fully depleted SOI material of a 22nm process node as a substrate, and the device structure of the multi-input floating gate transistor is shown in FIG. 3A and FIG. 3B. The transistor comprises a substrate (Subtrate), a buried oxide (Buried Oxide) on the surface of the substrate, and top-layer silicon on the oxidized surface of the buried layer, wherein the top-layer silicon forms a Source (Source), a Drain (Drain) and a conductive channel between the Source and the Drain, which is formed by adopting a Thin-film silicon (Thin Si-body) material through doping. A Gate (Gate) is provided on the surface of the conductive channel and a Floating Gate (Floating Gate) is provided on the surface of the Gate. The method has the advantages that the characteristics of the fully depleted SOI material can be utilized, the source, the drain and the conducting channel are directly formed on the top silicon through doping, and the series connection between the transistors is directly formed, so that an additional conductive isolation well is not required to be manufactured, and the method is a low-cost and high-efficiency selection mode.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (2)
1. A floating gate transistor-based neural network comprising a multi-node input unit: the multi-node input unit comprises a multi-input floating gate transistor, wherein a plurality of grid input ends of the multi-input floating gate transistor are respectively connected with a plurality of external bionic sensor input signals, a source electrode is grounded, and a drain electrode is used as an output end of the neuron network;
The multi-input-end floating gate transistor of the multi-node input unit is a multi-input-end floating gate transistor taking fully-depleted SOI material as a substrate;
the transistor comprises a substrate, a buried oxide layer on the surface of the substrate and top silicon on the oxidized surface of the buried oxide layer, wherein the top silicon is doped to form a source, a drain and a conductive channel between the source and the drain, wherein the conductive channel is formed by adopting a thin film silicon material;
the surface of the conducting channel is provided with a grid electrode and a floating gate on the surface of the grid electrode, a source electrode, a drain electrode and the conducting channel are directly formed on the top silicon through doping, and series connection among transistors is directly formed.
2. The floating gate transistor based pulsed neural network of claim 1, wherein the fully depleted SOI material is employed as a substrate for a multi-input floating gate transistor using a 22nm node process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011638469.XA CN112836812B (en) | 2020-12-31 | Neural network based on floating gate transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011638469.XA CN112836812B (en) | 2020-12-31 | Neural network based on floating gate transistor |
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| CN112836812A CN112836812A (en) | 2021-05-25 |
| CN112836812B true CN112836812B (en) | 2024-07-05 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416086A (en) * | 2019-07-10 | 2019-11-05 | 复旦大学 | A kind of half floating transistor of FD-SOI structure and preparation method thereof |
| CN111753976A (en) * | 2020-07-02 | 2020-10-09 | 西安交通大学 | Electronic afferent neuron for neuromorphic impulse neural network and implementation method |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416086A (en) * | 2019-07-10 | 2019-11-05 | 复旦大学 | A kind of half floating transistor of FD-SOI structure and preparation method thereof |
| CN111753976A (en) * | 2020-07-02 | 2020-10-09 | 西安交通大学 | Electronic afferent neuron for neuromorphic impulse neural network and implementation method |
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