CN112834035A

CN112834035A - CMOS (complementary Metal oxide semiconductor) driving circuit of micro spectrometer

Info

Publication number: CN112834035A
Application number: CN202011581633.8A
Authority: CN
Inventors: 邱晓晗; 林方; 王煜; 司福棋
Original assignee: Hefei Institutes of Physical Science of CAS
Current assignee: Hefei Institutes of Physical Science of CAS
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2021-05-25
Anticipated expiration: 2040-12-28
Also published as: CN112834035B

Abstract

The CMOS drive circuit of the micro spectrometer comprises a USB3.0 interface, an FPGA, a CYUSB3014, an AD9826, an AD847, a 74H14 and other peripheral chips. The driving of a micro spectrometer CMOS detector S11639 can be achieved by the FPGA sending a driving clock via 74H14 and generating an analog video signal. The generated analog signals are acquired by the AD9826 after passing through the AD847 to generate digital video signals, and the digital video signals are transmitted to an upper computer through a CYUSB3014 and a USB3.0 interface. The upper computer can send instructions such as UART protocol signal control S11639 exposure time through the same USB3.0 interface. The upper computer can send an I/O signal through the USB3.0 interface as an external trigger instruction. The invention reduces the use of driving signals and off-chip RAM, reduces the complexity of code programming, and reduces peripheral chips, thereby further reducing the size and cost of the PCB. In addition, on the premise of not increasing a peripheral interface, an external trigger function is added, and the accuracy of data acquisition is improved.

Description

CMOS (complementary Metal oxide semiconductor) driving circuit of micro spectrometer

Technical Field

The invention relates to the technical field of driving circuits, in particular to a CMOS (complementary metal oxide semiconductor) driving circuit of a micro spectrometer.

Background

Chlorophyll fluorescence is a rapid and effective probe for plant photosynthesis. After dark adaptation of plant cells, several enzymes participating in Calvin cycle lose activity, and after re-illumination, the plant cells need to pass through a photosynthetic induction period to normally operate. In the photosynthetic induction period, the absorbed excitation energy no longer participates in photochemical reaction, and the rapid increase of chlorophyll fluorescence is shown, namely the rapid phase chlorophyll fluorescence kinetic process. From this process, photosynthesis parameters such as Fo (fixed fluorescence), Fm (maximum fluorescence yield), and σ PSII (functional absorption cross section of PSII) can be inverted. The photosynthetic parameters can reflect the photosynthetic photoreaction process, and are physiological indicators of the influence of the physiological state and stress environment of the plant on the plant.

In order to trigger the high-frequency pulse light to induce chlorophyll fluorescence and synchronously acquire chlorophyll fluorescence signals generated by the high-frequency pulse light triggering induction, the design requirement of a spectrometer capable of generating external trigger signals and synchronously acquiring fluorescence is generated. Since the micro spectrometer is commonly used in the external field test, in order to make the spectrometer small in size, light in weight and portable, the use of interfaces and chips needs to be reduced in the design of the CMOS driving circuit. Thus creating a design requirement for such micro-spectral CMOS driver circuits.

In the article of "research on ultraviolet-visible micro fiber optic spectrometer", published by "Dongjian Ping and Dong Shao-Bo of the university of industry in Zhejiang, the driving circuit of S11639 in the micro fiber optic spectrometer adopts the scheme shown in FIG. 1. The data acquisition of the spectrometer mainly depends on circuit design, including the receipt, processing and transmission of optical signals, the receipt of optical signals mainly depends on optical detection elements, the optical signals are converted into electrical signals by the optical detection elements, the electrical signals need to adjust reference points and levels through circuits, data storage is carried out by utilizing an external RAM chip after A/D conversion, data acquisition and transmission are carried out by adopting an ARM micro processor, the obtained data are transmitted to an upper computer through a USB for spectrum display, and in order to control the cooperation of all devices in the circuit, a control circuit consisting of CPLD logic devices is needed to generate driving pulses matched with a CMOS, address codes of the external RAM and A/D sampling pulses.

The concrete reality is shown in fig. 2. The driver circuit is designed to provide a CLK master clock signal and an ST signal at S11639 and to utilize the Trig signal sent by them as a clock signal for subsequent data a/D conversion and an address generation signal stored in the data RAM. The A/D adopts an AD9235 chip and can carry out 12-bit parallel output; the external RAM adopts IS61LV3216L with 512 static spaces and maximum access time of 20 ns; the control chip adopts an STM32F103 chip; and the S11639 driving time sequence, the A/D sampling time sequence and the RAM address generating time sequence are realized by adopting a CPLD chip EPM7064 AE.

By utilizing the timer function of the STM32F103 chip, 1M clock signals are generated and output to the S11639 through the internal control of the CPLD to be used as a CLK clock, the Trig signals of the S11639 are collected into the CPLD and matched with the control of the STM32F103 chip to generate an A/D sampling time sequence and an RAM address generation time sequence. The Video signal output by the S11639 is adopted by the AD9235, 12-bit parallel data is output, stored in an external SRAM, read into an internal data buffer area of the STM32F103, and finally copied to a USB common buffer area, and the data is transmitted to an upper computer by taking an internal USB interface of the STM32F103 as a data transmission channel.

The main disadvantages of the prior art are that the design is complex, the number of chips used is large, the area and cost of the PCB are increased, and an external trigger signal is lacked.

The method comprises the following specific steps:

1. the prior design adopts STM32F103 and CPLD to jointly generate a CLK signal and an ST signal to drive S11639 through a driving chip, and needs to receive a Trig signal for triggering an A/D sampling signal and a RAM address generating signal. Thus, three signals are required to complete the driving and acquisition of the S11639, and the complexity of the driving design is increased.

2. Because the analog signals of the S11639 are continuously acquired for the AD9235 by adopting the A/D conversion chip, the data volume is large, at the moment, the internal RAM of the STM32F103 does not meet the data transmission requirement, an additional external SRAM is required to be added, and therefore the area and the cost of the PCB are increased.

3. The data transmission adopts the USB of STM32F103 internal interface to transmit data, and this USB interface does not possess the control function of I/O signal, needs the additional I/O control interface that increases. Resulting in a further increase in the area of the PCB board. In addition, because the chlorophyll fluorescence collected by the micro spectrometer is induced by high-frequency pulse light, if an external trigger signal is additionally provided, the condition that the trigger pulse light and the collection are not synchronous can be caused.

Interpretation of related terms:

usb 3.0: universal Serial Bus 3.0, a short for Universal Serial Bus, is an external Bus standard, and is used to standardize the connection and communication between a computer and external devices.

B, FPGA: the Field Programmable Gate Array is a kind of semiconductor integrated circuit for short.

C, UART: a universal serial data bus for asynchronous communications.

D, CMOS: a Complementary Metal-Oxide-Semiconductor, known by Chinese academy name as CMOS.

Disclosure of Invention

The CMOS drive circuit of the micro spectrometer can solve the technical problem.

In order to achieve the purpose, the invention adopts the following technical scheme:

a CMOS drive circuit of a Micro spectrometer is based on an FPGA chip (Xilinx Spartan 6), an AD acquisition chip (AD9826) and a USB3.0 main control chip (CYUSB3014), and further comprises a signal drive chip 74H14, an operational amplifier chip (AD847), a USB interface (USB Micro B) chip and other power chips;

the FPGA module sends a driving control signal, the S11639 detector is driven by a driving chip 74H14, the S11639 detector sends a video analog signal by driving, and the video analog signal is sent to an AD9826 chip for data acquisition after being conditioned by an analog signal of an AD847 chip; before the video analog signal is collected, the FPGA module sends a working mode control instruction to an AD9826 chip through an SPI interface and simultaneously sends an AD driving clock and a sampling clock;

the acquired video signals are cached and packaged in the FPGA module and are transmitted to the USB3.0 main control chip in parallel, the FPGA module also needs to transmit a control instruction to control the USB3.0 main control chip and finally are transmitted to an upper computer through the USB Micro B chip;

and the upper computer sends a digital control instruction through a USB3.0 main control chip through a USB interface, and obtains exposure time and gain information after the digital control instruction is cached and analyzed by the FPGA module for changing an S11639 chip driving control signal.

Further, when high-frequency pulse light needs to be triggered externally, the upper computer sends an I/O signal to the FPGA module through the USB3.0 main control chip through the USB interface, the FPGA module obtains the I/O signal and then forwards the I/O signal to the external trigger interface, and meanwhile, the information is written into a video signal packet header for subsequent data processing.

Furthermore, the FPGA module comprises a drive control unit, an AD acquisition unit, a data processing unit, a CYUSB3014 control instruction and data transmission unit, a digital control unit and an external trigger interface unit;

the drive control unit is used for generating two paths of drive signals required by the CMOS detector S11639, and the CMOS detector drives a clock signal and a starting pulse signal;

the AD acquisition unit is used for generating an AD9826 control signal, sending the AD9826 control signal to the AD9826 through the SPI interface, setting an AD working mode, gain and bias information, setting the AD working mode to be a single-channel SHA mode, simultaneously providing an AD9826 driving clock AD CLK and a sampling signal SHP, receiving the AD9826 through an 8-bit data interface in a time-sharing mode, sending high and low 8-bit image data according to the high and low levels of the AD _ CLK respectively, and finally combining the high and low 8-bit image data into 16-bit image data to be sent to the ping-;

the data processing unit is used for adding a packet header, a frame number, exposure time, AD gain and external trigger information in front of each frame of image data, wherein the packet header is used for identifying the start of one frame of image; the external trigger is used for identifying when the detector receives chlorophyll fluorescence induced by the high-frequency pulse light; the frame number is used for calculating that the current image is the image of several times and judging that the image is the induced chlorophyll fluorescence data of several times;

the control command and data transmission unit of the CYUSB3014 generates a control signal of the CYUSB3014, including: the full-empty state, the read enable, the write enable, the address, the clock and the chip select signal are used for controlling the data transmission of the USB3.0 interface and sending 16-bit parallel data signals;

the digital control unit receives control instructions sent by a USB3.0 interface through a CYUSB3014 by a UART protocol according to 115200 baud rate, wherein the control instructions comprise exposure time, gain, photographing times and a working mode, and analyzes the control instructions after caching the control instructions to obtain control information for controlling an S11639 driving clock;

after receiving the I/O signal sent by the USB3.0 interface through the CYUSB3014, the FPGA forwards the I/O signal to the external trigger interface, and simultaneously writes the signal into the header of the image signal.

Further, the USB3.0 main control chip includes two interfaces:

1) the first interface is a UART interface, and the UART interface comprises three endpoints which are respectively a sending endpoint, a receiving endpoint and an interruption endpoint so as to realize the function of a serial port;

2) the second interface is a synchronous slave equipment queue interface, and the interface comprises a synchronous slave equipment queue endpoint for receiving the transmission data of the FPGA; the synchronous slave queue interface is used for an application of which an external processor needs to perform data read/write access to an internal buffer of the CYUSB 3014.

Further, the upper computer connected with the USB3.0 main control chip can send requests to the USB3.0 main control chip, wherein the types of the requests are divided into three types according to functions, namely standard requests, class requests and custom requests;

wherein the standard request acts on all USB3.0 devices; the class request corresponds to a particular class of USB3.0 device.

Furthermore, the FPGA module generates a driving clock and adopts a main clock counter.

Further, the upper computer sends a trigger signal to the CYUSB3014 through the USB Micro B interface, and the CYUSB3014 controls the internal GPIO to send the same signal to the FPGA after receiving the self-setting request; the signal is directly transmitted to an external trigger interface through the FPGA on one hand and is used for triggering high-frequency pulse light; on the other hand, the signal is used as an enabling signal, the enabling total counter is used for driving S11639 to start collecting, and the signal is written into the header of the frame image as a flag bit;

during subsequent data processing, the first frame image after the high-frequency pulse light is triggered can be known, effective frames are searched according to the frame count in the packet header, and the number of photos after the high-frequency pulse light is triggered is sent to the FPGA number control unit through the USB Micro B interface and the CYUSB3014 by the upper computer;

the frequency and intensity of the high-frequency pulse light are determined by the frequency and duty ratio of the I/O control signal transmitted by the upper computer.

Further, the S11639 detector drives the clock to continuously operate according to the exposure time and the gain parameters set by the control instruction sent by the upper computer;

according to the trigger signal of the upper computer setting frequency and duty ratio, continuously sending the trigger signal to trigger the high-frequency pulse;

s11639 the detector continues to collect optical signal in the whole test process, when the trigger signal is enabled, the flag bit in the header of the next frame image is enabled, when the trigger is stopped, the flag bit is reset, so that the effective frame data can be screened out in the data processing.

According to the technical scheme, the micro spectrum CMOS drive circuit comprises a USB3.0 interface, an FPGA, a CYUSB3014 (a USB3.0 main control chip), an AD9826, an AD847, a 74H14 and other peripheral chips. The driving of a micro spectrometer CMOS detector S11639 can be achieved by the FPGA sending a driving clock via 74H14 and generating an analog video signal. The generated analog signals are acquired by the AD9826 after passing through the AD847 to generate digital video signals, and the digital video signals are transmitted to an upper computer through a CYUSB3014 and a USB3.0 interface. The upper computer can send instructions such as UART protocol signal control S11639 exposure time through the same USB3.0 interface. The upper computer can send an I/O signal through the USB3.0 interface as an external trigger instruction.

The micro spectrum CMOS drive circuit has the following advantages:

1. the USB3.0 can solve the problems of image data transmission and control instruction sending, and can also send an I/O signal as an external trigger signal through the USB3.0 interface, and an external trigger interface is not required to be additionally arranged.

2. When the CMOS detector S11639 is driven by the FPGA, the CMOS detector S11639 can be driven and video signal acquisition can be completed only by sending CLK signals (Clock, CMOS detector driving Clock signals) and ST signals (Start pulse signals) through the 74H14 driving chip, and it is not necessary to receive EOS signals (End of scan) and Trig signals (Trigger pulse signals for video signal acquisition, analog video signal acquisition Trigger pulse signals of the CMOS detector).

In conclusion, the invention reduces the use of driving signals and off-chip RAM, reduces the complexity of code programming, and reduces peripheral chips, thereby further reducing the size and cost of the PCB. In addition, on the premise of not increasing a peripheral interface, an external trigger function is added, and the accuracy of data acquisition is improved.

Drawings

FIGS. 1 and 2 are schematic diagrams of an S11639 driving circuit in a micro fiber spectrometer mentioned in the prior art;

FIG. 3 is an overall block diagram of the driving circuit of the micro spectrometer based on S11639 according to the present invention;

FIG. 4 is a functional block diagram of the FPGA components of the present invention;

FIG. 5 is a block diagram of the USB3.0 configuration of the present invention;

FIG. 6 is a diagram of a USB3.0 application architecture of the present invention;

FIG. 7 is an internal structural diagram of the driving timing of S11639 of the present invention;

FIG. 8 is a specific phase relationship for each type of S11639 drive timing of the present invention;

FIG. 9 is a diagram of the exposure time of the driving sequence of S11639 according to the present invention;

FIG. 10 is a driving timing diagram of the whole S11639 of the present invention;

FIG. 11 is a timing diagram of the AD9826 acquisition driver of the present invention;

FIG. 12 is a graph of AD acquisition driver test results of the present invention;

FIG. 13 is a test chart of the CMOS driver clocks CLK and ST of the present invention;

FIG. 14 is a clock cycle test chart of the present invention;

FIG. 15 is a sample start test chart of the present invention;

FIG. 16 is a schematic diagram of the synchronized external trigger mode of the present invention;

FIG. 17 is a schematic of the present invention with respect to an external trigger mode.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.

The CMOS driving circuit of the Micro spectrometer described in this embodiment, specifically, the whole block diagram of the driving circuit of the Micro spectrometer based on S11639 is shown in fig. 3, and the driving circuit mainly includes an FPGA (Xilinx Spartan 6), a driving chip (74H14), a USB3.0 main control chip (CYUSB3014), an operational amplifier chip (AD847), an AD acquisition chip (AD9826), a USB interface (USB Micro B), and other peripheral chips.

The FPGA sends a drive control signal, the S11639 is driven by 74H14, the S11639 sends a video signal by driving, and the video signal is sent to the AD9826 for data acquisition after being conditioned by the AD847 analog signal. Before the video signal is collected, the FPGA sends a working mode control instruction to the AD9826 through the SPI interface and simultaneously sends an AD driving clock and a sampling clock. The collected video signals are cached and packaged in the FPGA and are parallelly sent to the CYUSB3014, the FPGA also needs to send a control instruction to control the CYUSB3014, and finally the video signals are sent to an upper computer through the USB Micro B interface.

The upper computer can send a digital control instruction through a USB Micro B interface and a CYUSB3014, and obtains information such as exposure time, gain and the like after the information is cached and analyzed by the FPGA for changing an S11639 drive control signal.

In the actual test process, when external trigger high-pulse light is needed, the upper computer can send an I/O signal to the FPGA from the USB Micro B interface through the CYUSB3014, the FPGA acquires the I/O signal and then forwards the I/O signal to the external trigger interface, and meanwhile, the information is written into a video signal packet header for subsequent data processing.

The main functional block diagram of the FPGA is shown in fig. 4:

the FPGA mainly completes the following work:

1. driving clock

The drive control unit generates two drive signals, CLK signal (Clock, CMOS detector drive Clock signal) and ST signal (Start pulse signal), required by the CMOS detector S11639.

2. AD acquisition

AD acquisition unit produces AD9826 control signal, sends to AD9826 through the SPI interface for information such as setting AD mode of operation, gain and bias, and set up to single channel SHA mode. And meanwhile, an AD9826 driving clock AD CLK and a sampling signal SHP are provided, high and low 8-bit image data are respectively sent according to the high and low levels of AD _ CLK by receiving the AD9826 through an 8-bit data interface in a time-sharing mode, and finally combined into 16-bit image data to be sent to a ping-pong cache unit.

3. Data processing unit

In order to facilitate subsequent data processing, information such as a packet header, a frame number, exposure time, AD gain, and an external trigger needs to be added before each frame of image data. Wherein the packet header is used for identifying the start of a frame of image; the external trigger is used for identifying when the detector receives chlorophyll fluorescence induced by the high-frequency pulse light; the frame number is used for calculating that the current image is the image of the second few, and can be used for judging that the image is the induced chlorophyll fluorescence data of the second few.

4. CYUSB3014 control command and data transmission unit

The unit generates control signals of CYUSB3014, including: the full-empty state, the read enable, the write enable, the address, the clock, the chip select signal and the like are used for controlling data transmission of the USB3.0 interface and sending 16-bit parallel data signals.

5. Digital control unit

And receiving control instructions such as exposure time, gain, photographing times, working modes and the like sent by a USB3.0 interface through a CYUSB3014 by using a UART protocol according to the 115200 baud rate, caching the control instructions and then analyzing the control instructions. The parsed control information is used to control S11639 to drive the clock.

6. External trigger

USB3.0 firmware design

The micro spectrometer drive circuit USB3.0 main control chip adopts CYUSB3014 chip produced by Cypress company. The chip integrates a USB3.0, a USB2.0 physical layer and a 32-bit ARM926EJ-S microprocessor, has strong data processing capability, supports 16 output interfaces and 16 input interfaces at most, and is provided with a RAM (random access memory) of 512KB for storing firmware and data.

The chip mainly fulfills the following functions:

1. data transfer function and data pipe function

The USB3.0 configuration structure designed this time is shown in fig. 5, and two interfaces are configured for the USB3.0 device:

1) the first interface is a UART interface, which includes three endpoints, namely a Transmit (TX), a Receive (RX), and an INTERRUPT (INTERRUPT) endpoint, to implement a serial port function.

2) The second Interface is a Synchronous Slave queue Interface (Synchronous Slave FIFO Interface) which comprises a Synchronous Slave queue (Slave FIFO) endpoint for receiving FPGA transmission data. The synchronous slave device queue interface is generally used for an application of which an external processor needs to perform data read/write access to an internal buffer of the CYUSB3014, and the structure of the synchronous slave device queue interface is shown in fig. 6;

2. I/O control

The upper computer connected with the USB3.0 device may send a Request (Request) to the USB3.0 device, where the Request is classified into three types according to its function, which are a Standard Request (Standard Request), a Class Request (Class Request), and a custom Request (Vendor Request).

Wherein, the standard request can act on all USB3.0 devices; the class request corresponds to a specific class of USB3.0 devices (e.g., HID devices have a common class request); in the invention, partial pins can be configured into a GPIO output form through a CYUSB3014 chip, the output high and low levels of the GPIO pins are set through an CyU3 PgpiosteValue function in firmware, and the response to a specific self-defined request is added to realize the control function of the GPIO.

S11639 drive control design

1. S11639 driving sequence

S11639 is a high-sensitivity CMOS linear array detector produced by Hamamatsu corporation, which comprises a row of 2048 pixels in total and has a maximum driving time sequence of 10 MHZ. The internal structure is shown in fig. 7.

The detector comprises 24 pins, 5 clock pins besides 5 pins of Vdd and Vss, and other pins are suspended. Wherein the clock pins are respectively: CLK, ST, Trig, EOS and Video, the specific effects are as follows:

(1)CLK

CLK is an external clock input that functions to provide a clock input to the COMS internal clock generator, and the CLK clock frequency is the output pixel clock frequency.

(2)ST

ST is an external input driving trigger signal, and an image signal is generated at the 89 th rising edge of the CLK clock after the first falling edge of the ST signal is generated. The high level of ST determines the exposure time of an image.

(3)EOS

EOS is a frame end signal and is output by COMS, and when EOS rising edge is generated, it represents that one frame of image is ended.

(4)Trig

The Trig is a video signal acquisition trigger signal and is output by the COMS, when the rising edge of the Trig is generated, the rising edge corresponds to the high level of the image signal, and the falling edge corresponds to the low level of the image signal.

(5)Video

The Video is a Video signal and is output by the COMS, the output of the Video signal needs to be filtered, amplified and impedance matched, and the Video signal is accompanied by a voltage bias of 0.3-0.9V and needs to be processed subsequently.

The specific phase relationship of each type is shown in fig. 8:

in this example, the CLK driving clock is 2MHz, and the output frequency of the pixel is consistent with the CLK driving clock. And the ST driving clock mainly provides the pixel signal output start signal and provides the exposure time. The exposure time is determined by the ratio of the high and low levels of the ST, and is determined by the ratio of the high and low levels of the ST plus 48 CLK driving clock periods according to the technical manual of S11639. As shown in fig. 9, since the entire one-frame image operation period is 2140 CLK drive clock periods, the entire period is 1070 μ s.

When the driving clock frequency is maximized (the video data rate is also maximized), the time of the 1-frame image is now minimized, and the integration time is maximized (outputting signals of all 2048 channels).

Driving clock frequency 2MHz, i.e. 0.5 mus

Start pulse period 2140/f (clk) 2140/2MHz 1070 mus

High-level period of start pulse-start pulse low-level minimum

＝2140/f(CLK)–100/f(CLK)＝2140/2MHz–100/2MHz＝1020μs

The integration time is equal to the high level period of the initial pulse +48 driving clock periods 1020+24 1044 mus

At this time, it can be seen that the maximum exposure time is 1044 μ s in the case of the 10MHz driving clock.

When the high level period is the minimum period, i.e., 6 CLKs, the minimum exposure time, i.e., the integration time is the minimum 6 CLKs +48 CLKs of the high level, i.e., the minimum exposure time is 27 μ s.

Therefore, the exposure time in the invention is adjustable within 17-1044 mu s

In addition, if the first start pulse is after the ST signal falls, the video signal is generated at the rising edge of the 89 th trigger signal. The driving timing of the entire S11639 can be obtained. As shown in fig. 10.

The FPGA generates a driving clock, a main clock counter is adopted, and all signals are finished by referring to the main clock counter in the execution process. The advantage of using the master clock counter is that the driving signals are generated synchronously, so that the position of the master clock counter when the Video signal is generated can be determined according to the phase relation of the driving clocks CLK and Video, and at this time, the sampling signal of the Video analog signal can be determined without referring to the Trig and EOS signals. Since the S11639 needs a 5V power supply, the voltage of the Trig and EOS signals is also 5V, and at this time, when the FPGA wants to receive the two signals, an additional chip needs to be added to convert the signals into 3.3V signals that can be received by the FPGA I/O port. Therefore, the scheme of adopting the master clock counter reduces the use of the Trig and the EOS signals, thereby reducing the complexity of code writing, simultaneously reducing the use of chips and further reducing the area of a PCB (printed circuit board).

2. AD9826 acquisition drive timing

S11639 the video signal needs to be A/D converted, in this example, the A/D conversion chip is AD 9826. The AD9826 is an integrated chip integrating the related double sampling and a/D conversion functions, and the chip is a chip specially used for an imaging system and widely applied to acquisition of image signals. The method is characterized in that a three-channel structure design is adopted, each channel comprises an input clamp, a correlated double sampling CDS, a Programmable bias of 300mV, a Programmable Gain Amplifier (PGA) of 0-63 stages and a multiplexed high-performance 16-bit A/D converter, and the maximum conversion rate is 15 MSPS. The output process of the AD9826 is that 2 pieces of 8-bit data are respectively output at the high and low levels of an AD driving clock AD _ CL, and then the data are combined into 16-bit data according to the high and low levels. AD9826 has 6 different modes of operation: three-channel CDS mode and SHA mode, two-channel CDS mode and SHA mode, one-channel CDS mode and SHA mode. The programmable configuration register is controlled via the serial interface to select which mode of operation to use. Since the video signal output at S11639 is not a differential signal, only the one-channel SHA mode needs to be adopted. At the moment, only one path of sampling is needed for related double sampling, and the other path of sampling is grounded. In order to correctly sample S11639, the AD driving clock AD _ CLK and the sampling clock SHP are generated by using the lower 4 bits of the master clock counter, and keep synchronous with the S11639 driving clock, and the specific timing diagram is shown in fig. 11.

The AD acquisition drive test is shown in fig. 12.

S11639 drive test

First, CMOS driving clock CLK and ST test pattern

As shown in fig. 13, the driver circuit divides the clock by 16 with a 32MHz crystal oscillator to generate a CMOS drive clock CLK of 2 MHz. The ST high level is exposure time, firstly delays 4 COMS clocks, then starts exposure, the exposure time is 30us, namely 60 COMS clocks, according to a data manual, exposure is continued for 48 COMS clocks after the ST falling edge starts, and the ST rising edge is 16 COMS clocks, namely 256 crystal oscillator clocks (32MHZ, 31.25ns) and 8000 ns.

Two, periodic test

As shown in fig. 14, the Clock period of the entire 1 frame pixel is 2140 COMS _ Clock, i.e. 2140 × 16 crystal periods, which is: 2140 × 16 × 31.25ns ═ 1070 us;

third, sample initial test

As shown in fig. 15, according to the technical manual, the ST falling edge starts and the pixel signal starts to be generated 88 clocks later, i.e. 88 COMS _ Clock +5 crystal periods after the ST falling starts, and the SH sampling Clock starts to sample. (88 × 16+5) × 31.25 ns-44165.25 ns.

External trigger design

The micro spectrometer is mainly used for collecting chlorophyll fluorescence, and high-frequency pulse light is needed for inducing the excitation of the chlorophyll fluorescence. At this time, a trigger signal is needed to trigger the high-frequency pulse light, and when the trigger signal triggers the high-frequency pulse light, the induced chlorophyll fluorescence signal is collected.

The micro spectrometer adopts two working modes: namely a synchronous external trigger mode and a synchronous automatic trigger mode.

1. Synchronous external trigger mode

The upper computer sends a trigger signal to the CYUSB3014 through the USB Micro B interface, and the CYUSB3014 controls the internal GPIO to send the same signal to the FPGA after receiving the self-setting request. The signal is directly transmitted to an external trigger interface through the FPGA on one hand and is used for triggering high-frequency pulse light; on the other hand, the signal is used as an enable signal, the capture is started by enabling the total counter driver S11639 as shown in fig. 16, and the signal is written as a flag bit in the header of the frame image, so this mode may also be referred to as a photographing mode. During subsequent data processing, the first frame image after the high-frequency pulse light is triggered can be known, and effective frames can be searched according to the frame count in the packet header. The number of photos after triggering the high-frequency pulse light is sent to the FPGA number control unit through the USB Micro B interface and the CYUSB3014 by the upper computer. The frequency and intensity of the high-frequency pulse light are determined by the frequency and duty ratio of the I/O control signal transmitted by the upper computer. The synchronous triggering acquisition mode solves the problem that the acquisition of the induced chlorophyll fluorescence and the high-frequency pulse light is asynchronous when an additional triggering mode is adopted. In addition, the photographing mode can be used for photographing for multiple times when chlorophyll fluorescence is weak and high-frequency pulse light is triggered once, and accumulating multiple frames of data, so that the signal-to-noise ratio is improved.

2. Synchronous auto-trigger mode

As shown in fig. 17, in the external trigger mode, S11639 drives the clock to continuously operate according to parameters such as exposure time and gain set by the control command sent from the host computer, and thus the mode may be regarded as the video recording mode. And continuously sending a trigger signal according to the trigger signal with the set frequency and duty ratio of the upper computer to trigger the high-frequency pulse. S11639 continues to collect the image data during the whole test, and when the trigger signal is enabled, the flag bit in the header of the next frame of image is enabled, and when the trigger is stopped, the flag bit is reset. Therefore, the effective frame data can be screened out in the data processing.

In summary, the present invention has the following features:

1. the driving of the CMOS S11639 and the video signal acquisition can be completed only by using the CMOS driving clock CLK and ST signals.

2. The trigger functions are added, including synchronous external trigger and synchronous automatic trigger, and the S11639 data transmission function, the data counting function and the trigger function can be completed only through one USB Micro B interface.

3. The invention only outputs two paths of driving signals: the CMOS drives clocks CLK and ST. The Trig and EOS signals do not need to be received, the complexity of code programming is reduced, and the use of peripheral chips is reduced.

4. The invention adds the synchronous triggering function to avoid the condition that the pulse light triggering and the fluorescence acquisition are not synchronous. In addition, the external trigger signal interface is integrated in the USB Micro B interface, and an external trigger signal input interface does not need to be additionally arranged.

5. The invention adopts the AD9826 integrating the related double sampling function and the FPGA with small combined data volume, and the FPGA on-chip RAM can solve the function of data caching without additionally increasing off-chip RAM, thereby reducing the use of peripheral chips. In addition, the USB3.0 interface is adopted to further improve the data transmission rate, further reduce the burden of data caching and reduce the complexity of code programming.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A CMOS drive circuit of a micro spectrometer is based on FPGA chips (Xilinx Spartan 6), AD acquisition chips (AD9826) and a USB3.0 main control chip (CYUSB3014), and is characterized in that:

the USB driver further comprises a signal driving chip 74H14, an operational amplifier chip (AD847 chip) and a USB interface (USB Micro B chip);

the FPGA module sends a driving control signal, the S11639 detector is driven by a driving chip 74H14, the S11639 detector sends a video signal by driving, and the video signal is sent to an AD9826 chip for data acquisition after being conditioned by an analog signal of an AD847 chip; before the video signal is collected, the FPGA module sends a working mode control instruction to an AD9826 chip through an SPI interface and simultaneously sends an AD driving clock and a sampling clock;

the acquired video signals are cached and packaged in the FPGA module and are transmitted to the USB3.0 main control chip in parallel, the FPGA module also needs to transmit a control instruction to control the USB3.0 main control chip and finally are transmitted to an upper computer through a USB Micro B interface;

2. The CMOS driver circuit for a micro spectrometer of claim 1, wherein: when high-pulse light needs to be triggered externally, the upper computer sends an I/O signal to the FPGA module through the USB3.0 main control chip through the USB interface, the FPGA module obtains the I/O signal and forwards the I/O signal to the external trigger interface, and meanwhile, the information is written into a video signal packet header for subsequent data processing.

3. The CMOS driver circuit for a micro spectrometer of claim 1, wherein: the FPGA module comprises a drive control unit, an AD acquisition unit, a data processing unit, a CYUSB3014 control instruction and data transmission unit, a digital control unit and an external trigger interface unit;

4. The CMOS driver circuit for a micro spectrometer of claim 1, wherein: the USB3.0 main control chip comprises two interfaces:

5. The micro spectrometer CMOS driver circuit as claimed in claim 4, wherein: the upper computer connected with the USB3.0 main control chip can send requests to the USB3.0 main control chip, wherein the types of the requests are divided into three types according to functions, namely standard requests, class requests and custom requests;

6. The CMOS driver circuit for a micro spectrometer of claim 1, wherein: the FPGA module generates a driving clock and adopts a main clock counter.

7. The CMOS driver circuit for a micro spectrometer of claim 1, wherein: the upper computer sends a trigger signal to the CYUSB3014 through the USB Micro B interface, and the CYUSB3014 controls an internal GPIO to send the same signal to the FPGA after receiving a self-setting request; the signal is directly transmitted to an external trigger interface through the FPGA on one hand and is used for triggering high-frequency pulse light; on the other hand, the signal is used as an enabling signal, the enabling total counter is used for driving S11639 to start collecting, and the signal is written into the header of the frame image as a flag bit;

8. The CMOS driver circuit for a micro spectrometer of claim 1, wherein:

the SS11639 drives the chip to drive the clock to continuously run according to the exposure time and the gain parameter set by the control instruction sent by the upper computer;

the SS11639 driving chip continuously collects data in the whole test process, when the trigger signal is enabled, the zone bit in the packet head of the next frame of image is enabled, when the trigger signal is stopped, the zone bit is reset, and therefore valid frame data can be screened out in the data processing process.