CN112833943A - Automatic optical detection and wafer test all-in-one machine - Google Patents
Automatic optical detection and wafer test all-in-one machine Download PDFInfo
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- CN112833943A CN112833943A CN202011589862.4A CN202011589862A CN112833943A CN 112833943 A CN112833943 A CN 112833943A CN 202011589862 A CN202011589862 A CN 202011589862A CN 112833943 A CN112833943 A CN 112833943A
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- 230000003287 optical effect Effects 0.000 title claims abstract description 42
- 238000012360 testing method Methods 0.000 title claims abstract description 39
- 238000001514 detection method Methods 0.000 title claims abstract description 27
- 238000004891 communication Methods 0.000 claims abstract description 33
- 239000000523 sample Substances 0.000 claims abstract description 23
- 230000002159 abnormal effect Effects 0.000 claims description 26
- 238000007689 inspection Methods 0.000 claims description 15
- 235000012431 wafers Nutrition 0.000 description 24
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241000282414 Homo sapiens Species 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000013072 incoming material Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D21/00—Measuring or testing not otherwise provided for
- G01D21/02—Measuring two or more variables by means not covered by a single other subclass
Abstract
The invention discloses an automatic optical detection and wafer test integrated machine, which comprises an automatic optical detection device, a first GPIB communication interface, a GPIB communication line, a second GPIB communication interface, a probe station and a test machine, wherein the automatic optical detection device is connected with the first GPIB communication interface; the automatic optical detection device comprises a structured light scanner; the first GPIB communication interface is arranged on the structured light scanner, the second GPIB communication interface is arranged on a probe station, the first GPIB communication interface is connected with the second GPIB communication interface through the GPIB communication line, and the probe station is connected with the tester. The invention effectively combines the automatic optical detection equipment with the probe station and the tester, the tester reads the coordinate value of each chip, and the coordinate value is compared and screened with the database of the automatic optical detection equipment, thereby ensuring that no chips with bad appearance are mixed into good products to be tested and ensuring the reliability of finished chips.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an automatic optical detection and wafer test integrated machine.
Background
The semiconductor industry in China starts late but develops rapidly, and keeps higher acceleration continuously for years. The three major industries of integrated circuits have been steadily growing. The appearance and development of integrated circuit chips provide a source for human beings to enter an information era. In the information age, integrated circuit chips are being widely used in work, life, and production. Along with the mass production of integrated chips, the chip is especially important in the control of each link yield, promotes the chip quality, reduce cost, and as the first process that the chip came out, wafer test process is vital. When the wafer is processed in a flow studio, the chips are 6-inch, 8-inch or 12-inch circles formed by splicing thousands of chips, which are called wafers. In the manufacturing process of the wafer, due to various factors (poor process, equipment scratch and manual touch) and the friction of the filter paper in the transportation process, when the wafer reaches the electrical testing process, the wafer is scratched to different degrees, as shown in fig. 1A, fig. 1B, fig. 2A and fig. 2B, an IQC (intelligent object inspection) person can scan the picture of the abnormal chip on the wafer through an automatic optical inspection equipment (called AOI for short) before testing and feed back the abnormal phenomenon to a customer, and the customer usually returns that the abnormal chip is manually clicked and removed, so that the test can be continued. However, in the actual operation process, as shown in fig. 3, after the abnormal chip is found by the automatic optical detection device, the artificial difficulty is removed completely, and only a slight scratch is made in the test process, all the electrical parameters are normal during the test, and the abnormal chip is determined to be a good product, so that the abnormal chip flows into the finished product and finally reaches the customer application, but the chip is a defective chip after all, the reliability is unstable, and the function of the whole application board is disabled when the abnormality occurs. The reason is that the chip with abnormal incoming material is only detected by automatic optical detection equipment, the abnormal chip cannot be identified and led into a test procedure machine to be directly removed, and the abnormal chip is manually removed, so that the efficiency is low, the coverage is incomplete, and the serious reliability failure is caused. The above problems are urgently needed to be solved.
Disclosure of Invention
The present invention is directed to solving the problems set forth in the background section above by an automated optical inspection and wafer test integrated machine.
In order to achieve the purpose, the invention adopts the following technical scheme:
an automated optical inspection and wafer test all-in-one machine, comprising: the automatic optical detection device comprises an automatic optical detection device, a first GPIB communication interface, a GPIB communication line, a second GPIB communication interface, a probe station and a test machine; the automatic optical detection device comprises a structured light scanner; the first GPIB communication interface is arranged on the structured light scanner, the second GPIB communication interface is arranged on a probe station, the first GPIB communication interface is connected with the second GPIB communication interface through the GPIB communication line, and the probe station is connected with the tester.
Particularly, the structured light scanner is used for scanning and recording abnormal chips, recording coordinates of all the abnormal chips in a database, and automatically generating an MAP image file according to the input wafer batch number, the wafer number and the size of the chip.
In particular, the structured light scanner is also used to directly identify the abnormal chip as a specific BIN and the remaining normal chips as T in the MAP file.
Particularly, the probe station is used for automatically reading the batch number and the sheet number of the wafer before testing the chip, reading the MAP graph file on automatic optical detection equipment, and directly generating a new MAP graph file by directly SIKP for an abnormal chip on the MAP graph file after coordinate conversion.
Particularly, the tester is used for testing the functional electrical parameters of the chips to be tested, which are marked as T, according to the new MAP graph file generated by the probe station, screening all the chips with abnormal appearance and poor electrical property after the whole wafer is tested, and generating the final MAP graph file.
The automatic optical detection and wafer test integrated machine provided by the invention effectively combines the automatic optical detection equipment with the probe station and the test machine, the test machine reads the coordinate value of each chip, and the coordinate value is compared and screened with the database of the automatic optical detection equipment, so that the chips without poor appearance are ensured to be mixed into good test products, and the reliability of finished chips is ensured.
Drawings
FIG. 1A shows a chip manufactured by FAB process;
FIG. 1B shows a process-abnormal chip from FAB process;
both fig. 2A and fig. 2B are the abnormal chip scratched by FAB process;
FIG. 3 shows a FAB abnormal chip with defective testing;
FIG. 4 is a schematic diagram of an integrated automatic optical inspection and wafer test machine according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an operation of the integrated automatic optical inspection and wafer test machine according to the embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following figures and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It is also to be noted that, for the convenience of description, only a part of the contents, not all of the contents, which are related to the present invention, are shown in the drawings, and unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
As shown in fig. 4, fig. 4 is a structural diagram of the integrated automatic optical inspection and wafer test machine 100 according to the embodiment of the present invention, in which the integrated automatic optical inspection and wafer test machine 100 includes: the automatic optical detection device comprises an automatic optical detection device 101, a first GPIB communication interface, a GPIB communication line, a second GPIB communication interface, a probe station 102 and a test machine 103; the automatic optical inspection apparatus 101 includes a structured light scanner 105; the first GPIB communication interface is disposed on the structured light scanner 105, the second GPIB communication interface is disposed on the probe station 102, the first GPIB communication interface is connected to the second GPIB communication interface through the GPIB communication line, the probe station 102 is connected to the tester 103, the chip to be tested is placed 104 on the probe station 102, and the probe station 102 is further provided with a cassete device 106.
As shown in fig. 5, fig. 5 is a schematic diagram of an operation of the integrated automatic optical inspection and wafer test machine 100 according to the embodiment of the present invention. During operation, the structured light scanner 105 is configured to scan and record the abnormal chips, record coordinates of all the abnormal chips in the database, and automatically generate an MAP file according to the input lot number and the chip number of the wafer and the size of the chip. Specifically, in this embodiment, the structured light scanner 105 is further configured to directly identify an abnormal chip as a specific BIN and identify the remaining normal chips as T in the MAP file. The probe station 102 is used for automatically reading the batch number and the sheet number of the wafer before the chip test, reading the MAP graph file on the automatic optical detection equipment 101, and generating a new MAP graph file by directly SIKP for the abnormal chip on the MAP graph file after coordinate conversion. The tester 103 is configured to test the functional electrical parameters of the to-be-tested chips identified as T according to the new MAP file generated by the probe station 102, and screen out all chips with abnormal appearance and poor electrical properties after the entire wafer is tested, so as to generate a final MAP file.
According to the technical scheme provided by the invention, the automatic optical detection equipment is effectively combined with the probe station and the testing machine, the testing machine reads the coordinate value of each chip, and the coordinate value is compared with the database of the automatic optical detection equipment for screening, so that the chips without poor appearance are ensured to be mixed into good products, and the reliability of finished chips is ensured.
It will be understood by those skilled in the art that all or part of the above embodiments may be implemented by the computer program to instruct the relevant hardware, and the program may be stored in a computer readable storage medium, and when executed, may include the procedures of the embodiments of the methods as described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory or a random access memory.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (5)
1. An automatic optical detection and wafer test all-in-one machine, comprising: the automatic optical detection device comprises an automatic optical detection device, a first GPIB communication interface, a GPIB communication line, a second GPIB communication interface, a probe station and a test machine; the automatic optical detection device comprises a structured light scanner; the first GPIB communication interface is arranged on the structured light scanner, the second GPIB communication interface is arranged on a probe station, the first GPIB communication interface is connected with the second GPIB communication interface through the GPIB communication line, and the probe station is connected with the tester.
2. The integrated machine for automatic optical inspection and wafer testing as claimed in claim 1, wherein the structured light scanner is configured to scan and record the abnormal chips, record coordinates of all the abnormal chips in the database, and automatically generate a MAP file according to the lot number of the wafer, the wafer number, and the size of the chip.
3. The integrated automatic optical inspection and wafer testing machine of claim 2, wherein the structured light scanner is further configured to directly identify an abnormal chip as a specific BIN and the remaining normal chips as T in a MAP file.
4. The integrated machine for automatic optical inspection and wafer test as claimed in claim 3, wherein the probe station is configured to automatically read the lot number and the sheet number of the wafer before the chip test, read the MAP graph file on the automatic optical inspection device, and generate a new MAP graph file by converting coordinates and directly SIKP for an abnormal chip on the MAP graph file.
5. The integrated automatic optical inspection and wafer test machine of claim 4, wherein the tester is configured to test the functional electrical parameters of the chips to be tested identified as T according to a new MAP graph file generated by the probe station, and screen out all chips with abnormal appearance and poor electrical properties after the entire wafer is tested, so as to generate a final MAP graph file.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011589862.4A CN112833943A (en) | 2020-12-29 | 2020-12-29 | Automatic optical detection and wafer test all-in-one machine |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011589862.4A CN112833943A (en) | 2020-12-29 | 2020-12-29 | Automatic optical detection and wafer test all-in-one machine |
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| CN112833943A true CN112833943A (en) | 2021-05-25 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW452915B (en) * | 1996-07-09 | 2001-09-01 | Scanis Inc | Method of sorting and investigating automatic semiconductor wafer with extended optical inspection and apparatus for implementing the same |
| US6747464B1 (en) * | 2001-06-21 | 2004-06-08 | Lsi Logic Corporation | Wafer holder for backside viewing, frontside probing on automated wafer probe stations |
| JP2005243939A (en) * | 2004-02-26 | 2005-09-08 | Nec Electronics Corp | Probe card and wafer probing method using it |
| CN106370992A (en) * | 2016-08-17 | 2017-02-01 | 上海华岭集成电路技术股份有限公司 | UID write-in system and method for semiconductor chip tests |
| CN108400100A (en) * | 2018-02-27 | 2018-08-14 | 上海华岭集成电路技术股份有限公司 | A kind of wafer test parameters setting method |
| CN110673019A (en) * | 2018-12-19 | 2020-01-10 | 上海华力微电子有限公司 | Wafer-level automatic test system |
| CN111293048A (en) * | 2018-12-07 | 2020-06-16 | 紫光同芯微电子有限公司 | Wafer test system and method thereof |
| CN111983412A (en) * | 2020-07-21 | 2020-11-24 | 深圳安博电子有限公司 | Monitoring system, monitoring method, monitoring terminal and storage medium |
-
2020
- 2020-12-29 CN CN202011589862.4A patent/CN112833943A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW452915B (en) * | 1996-07-09 | 2001-09-01 | Scanis Inc | Method of sorting and investigating automatic semiconductor wafer with extended optical inspection and apparatus for implementing the same |
| US6747464B1 (en) * | 2001-06-21 | 2004-06-08 | Lsi Logic Corporation | Wafer holder for backside viewing, frontside probing on automated wafer probe stations |
| JP2005243939A (en) * | 2004-02-26 | 2005-09-08 | Nec Electronics Corp | Probe card and wafer probing method using it |
| CN106370992A (en) * | 2016-08-17 | 2017-02-01 | 上海华岭集成电路技术股份有限公司 | UID write-in system and method for semiconductor chip tests |
| CN108400100A (en) * | 2018-02-27 | 2018-08-14 | 上海华岭集成电路技术股份有限公司 | A kind of wafer test parameters setting method |
| CN111293048A (en) * | 2018-12-07 | 2020-06-16 | 紫光同芯微电子有限公司 | Wafer test system and method thereof |
| CN110673019A (en) * | 2018-12-19 | 2020-01-10 | 上海华力微电子有限公司 | Wafer-level automatic test system |
| CN111983412A (en) * | 2020-07-21 | 2020-11-24 | 深圳安博电子有限公司 | Monitoring system, monitoring method, monitoring terminal and storage medium |
Non-Patent Citations (1)
| Title |
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