CN112825594A

CN112825594A - Apparatus and method for notifying time and frequency resource allocation of multi-slot transmission

Info

Publication number: CN112825594A
Application number: CN202011293185.1A
Authority: CN
Inventors: 谢尔盖·潘泰列夫; 基里安·罗斯; 阿列克谢·霍里亚耶夫; 米哈伊尔·希洛夫; 列奥纳多·戈梅斯·波尔塔
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2019-11-20
Filing date: 2020-11-18
Publication date: 2021-05-21

Abstract

The present disclosure provides an apparatus and method for notifying time and frequency resource allocation for multi-slot transmission. An apparatus for a UE comprising processor circuitry to: generating a first index a based on a number n of additional slots following the first slot, a number S of available subchannels in each additional slot, and a number m of assigned subchannels in each additional slot, wherein the first slot and the additional slots are for carrying the same TB; based on n, S, m, and an index k for the starting subchannel for each additional slot_jGenerating a second index b; generating a third index I based on a sum of the first index a and the second index b; and for the third in the SCI of the PSCCHThe index I is encoded for transmission to the recipient UE. Other embodiments are also disclosed and claimed.

Description

Apparatus and method for notifying time and frequency resource allocation of multi-slot transmission

Priority declaration

The present application is based on U.S. provisional application serial No. 62/938,093 filed on 20/11/2019 and claims priority from that application. The entire contents of this application are incorporated herein by reference in their entirety.

Technical Field

Embodiments of the present disclosure relate generally to the field of wireless communications, and in particular, to an apparatus and method for notifying time and frequency resource allocations for multi-slot transmissions.

Background

With the development of wireless communication, New Radio (NR) vehicle-to-everything (V2X) services may be implemented through various types of V2X applications, such as vehicle-to-vehicle (V2V), vehicle-to-pedestrian (V2P), vehicle-to-infrastructure (V2I), vehicle-to-network (V2N), and the like. The present disclosure will provide solutions regarding informing the time and frequency resource allocation for multi-slot transmission in NR V2X.

Disclosure of Invention

An aspect of the present disclosure provides an apparatus for a User Equipment (UE), the apparatus comprising: a Radio Frequency (RF) interface; and a processor circuit coupled with the RF interface, wherein the processor circuit is to: generating a first index a based on a number n of additional slots following a first slot, a number S of available subchannels in each of the additional slots, and a number m of allocated subchannels in each of the additional slots, wherein the first slot and the additional slots are for carrying a same Transport Block (TB); based on the number n of additional slots, the number S of available subchannels in each of the additional slots, the number m of allocated subchannels in each of the additional slots, and an index k of a starting subchannel for each of the additional slots_jGenerating a second index b, wherein j ∈ {0, …, n-1 }; generating a third index I based on a sum of the first index a and the second index b, wherein the third index I is used to inform of the division in each of the additional slotsThe number m of allocated subchannels and the index k of the starting subchannel for each of said additional slots_jBoth of them; and encoding the third index I in a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) for transmission to a recipient UE via the RF interface.

An aspect of the present disclosure provides an apparatus for a User Equipment (UE), the apparatus comprising: a Radio Frequency (RF) interface; and a processor circuit coupled with the RF interface, wherein the processor circuit is to: decoding a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) received from a sender UE via the RF interface to obtain a single index I; decoding time resource signaling received from the sender UE via the RF interface to obtain a number n of additional time slots after a first time slot; obtaining a number S of available subchannels in each of the additional time-slots according to a resource pool configuration; and determining the number of allocated subchannels m in each of the additional slots and the index k of the starting subchannel for each of the additional slots based on the index I, the number of additional slots n, and the number of available subchannels S in each of the additional slots_jWhere j ∈ {0, …, n-1 }.

An aspect of the disclosure provides a computer-readable medium having instructions stored thereon, which when executed by a processor circuit, cause the processor circuit to: generating a first index a based on a number n of additional slots following a first slot, a number S of available subchannels in each of the additional slots, and a number m of allocated subchannels in each of the additional slots, wherein the first slot and the additional slots are for carrying a same Transport Block (TB); based on the number n of additional slots, the number S of available subchannels in each of the additional slots, the number m of allocated subchannels in each of the additional slots, and for each of the additional slotsIndex k of the starting subchannel of a slot_jGenerating a second index b, wherein j ∈ {0, …, n-1 }; generating a third index I based on a sum of the first index a and the second index b, wherein the third index I is used to inform the number m of allocated subchannels in each of the additional slots and an index k of a starting subchannel for each of the additional slots_jBoth of them; and encoding the third index I in a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) for transmission to a receiving User Equipment (UE), wherein n is 1 or n is 2.

The present disclosure provides a computer-readable medium having stored thereon instructions that, when executed by a processor circuit, cause the processor circuit to: decoding a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) received from a transmitting User Equipment (UE) to obtain a single index I; decoding the time resource signaling received from the sender UE to obtain a number n of additional time slots after the first time slot; obtaining a number S of available subchannels in each of the additional time-slots according to a resource pool configuration; and determining the number of allocated subchannels m in each of the additional slots and the index k of the starting subchannel for each of the additional slots based on the index I, the number of additional slots n, and the number of available subchannels S in each of the additional slots_jWhere j ∈ {0, …, n-1}, where n ═ 1 or n ═ 2.

Drawings

Embodiments of the present disclosure will be described by way of example, and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements.

Fig. 1 illustrates an example architecture of a system according to some embodiments of the present disclosure.

Fig. 2 illustrates a flow diagram of a method for notifying frequency resource allocation for multi-slot transmission in accordance with some embodiments of the present disclosure.

Fig. 3 illustrates an example of notifying frequency resource allocation for multi-slot transmission in accordance with some embodiments of the present disclosure.

Fig. 4 illustrates a flow diagram of a method for notifying frequency resource allocation for multi-slot transmission in accordance with some embodiments of the present disclosure.

Fig. 5 illustrates an example of notifying frequency resource allocation for multi-slot transmission in accordance with some embodiments of the present disclosure.

Fig. 6 illustrates example components of a device according to some embodiments of the present disclosure.

Fig. 7 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium and performing any one or more of the methodologies discussed herein, according to some example embodiments.

Fig. 8 illustrates an example of an infrastructure device in accordance with various embodiments.

Detailed Description

Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of the disclosure to others skilled in the art. However, it will be readily appreciated by those skilled in the art that many alternative embodiments may be practiced using portions of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that alternative embodiments may be practiced without the specific details. In other instances, well-known features may be omitted or simplified in order not to obscure the illustrative embodiments.

Further, various operations will be described as multiple discrete operations, in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. The phrase generally does not refer to the same embodiment; however, it may refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise. The phrases "A or B" and "A/B" mean "(A), (B) or (A and B)".

The third generation partnership project (3GPP) Radio Access Network (RAN) has completed a research project (SI) on NR-V2X, which is defined in 3GPP TR 38.885 V2.0.0(2019-03) ("NR; vehicle to everything research (16 th edition)", 3 months 2019). Furthermore, the 3GPP RAN approved a new Work Item (WI) to develop the corresponding fifth generation (5G) V2X specification (3GPP RP-190766: "New WID in 5G V2X with NR side link", LG Electron, Ware, 3.2019), specifically the NR-based side link (SIDELink, SL) section. The present disclosure will provide a scheme regarding the notification of time and frequency resource allocations for multi-slot transmission in NR V2X, in particular the NR based SL part.

In the case of resource sensing for resource selection, it is beneficial for the physical side link control channel (PSCCH) side link control information (SCI) to inform the physical side link shared channel (PSCCH) resources allocated for transmission of the same Transport Block (TB) in multiple time slots or Transmission Time Intervals (TTIs). Since SCIs need to be transmitted in the most robust physical layer format, each additional bit in an SCI affects the overall coverage. Accordingly, the present disclosure will provide a scheme regarding efficiently informing time and frequency resource allocation for multi-slot transmission in NR V2X. Both mode 1 and mode 2 side chain operations are applicable. In mode 1, the signaling includes reserving resources (allocated by the network) for future transmissions. In mode 2, resources are not allocated by the network. In both cases, the reservation for future transmissions is contained in the SCI.

Fig. 1 illustrates an example architecture of a system 100 according to some embodiments of the present disclosure. The following description is provided for an example system 100 operating in conjunction with the Long Term Evolution (LTE) system standard and the 5G or New Radio (NR) system standard provided by the 3GPP Technical Specification (TS). However, the example embodiments are not limited in this respect and the described embodiments may be applied to other networks that benefit from the principles described herein, such as future 3GPP systems (e.g., sixth generation (6G)) systems, Institute of Electrical and Electronics Engineers (IEEE)802.16 protocols (e.g., wireless Metropolitan Area Network (MAN), Worldwide Interoperability for Microwave Access (WiMAX), etc.), and so forth.

As shown in FIG. 1, the system 100 can include a UE 101a and a UE 101b (collectively referred to as "UE(s) 101"). As used herein, the term "user equipment" or "UE" may refer to devices having radio communication capabilities and may describe remote users of network resources in a communication network. The terms "user equipment" or "UE" may be considered synonyms and may be referred to as a client, a mobile phone, a mobile device, a mobile terminal, a user terminal, a mobile unit, a mobile station, a mobile user, a subscriber, a user, a remote station, an access agent, a user agent, a receiver, a radio, a reconfigurable mobile, and the like. Furthermore, the terms "user equipment" or "UE" may include any type of wireless/wired device or any computing device that includes a wireless communication interface. In this example, the UE 101 is shown as a smartphone (e.g., a handheld touchscreen mobile computing device connectable to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as a consumer electronic device, a cellular phone, a smartphone, a feature phone, a tablet, a wearable computer device, a Personal Digital Assistant (PDA), a pager, a wireless handheld device, a desktop computer, a laptop computer, an in-vehicle infotainment system (IVI), an in-vehicle entertainment (ICE) device, an Instrument panel (Instrument Cluster, IC), a head-up display (HUD) device, an in-vehicle diagnostics (OBD) device, a dashboard mobile Device (DME), a Mobile Data Terminal (MDT), an Electronic Engine Management System (EEMS), an electronic/Engine Control Unit (ECU), an electronic/Engine Control Module (ECM), a mobile computing device(s), a mobile computing device, a mobile, Embedded systems, microcontrollers, control modules, Engine Management Systems (EMS), networked or "smart" devices, Machine Type Communication (MTC) devices, machine-to-machine (M2M), internet of things (IoT) devices, and/or the like.

In some embodiments, any of the UEs 101 may include an IoT UE, which may include a network access layer designed for low-power IoT applications that utilize short-term UE connections. IoT UEs may utilize technologies such as M2M or MTC to exchange data with MTC servers or devices via PLMNs, proximity-based services (ProSe) or device-to-device (D2D) communications, sensor networks, or IoT networks. The data exchange of M2M or MTC may be a machine initiated data exchange. An IoT network describes interconnected IoT UEs that may include uniquely identifiable embedded computing devices (within the internet infrastructure) with short-term connections. The IoT UE may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate connection of the IoT network.

UE 101 may be configured to connect with (e.g., communicatively couple with) RAN 110. In an embodiment, RAN 110 may be a Next Generation (NG) RAN or a 5G RAN, an evolved Universal Mobile Telecommunications System (UMTS) terrestrial radio access network (E-UTRAN), or a legacy RAN, such as a UTRAN (UMTS terrestrial radio access network) or a GERAN (GSM (global system for Mobile communications or group Sp specific Mobile) EDGE (GSM evolution) radio access network). As used herein, the term "NG RAN" or the like may refer to RAN 110 operating in an NR or 5G system 100, and the term "E-UTRAN" or the like may refer to RAN 110 operating in an LTE or 4G system 100. The UE 101 utilizes connections (or channels) 103 and 104, respectively, each of which includes a physical communication interface or layer (discussed in further detail below). As used herein, the term "channel" may refer to any tangible or intangible transmission medium that communicates data or a stream of data. The term "channel" may be synonymous and/or equivalent to "communication channel," "data communication channel," "transmission channel," "data transmission channel," "access channel," "data access channel," "link," "data link," "carrier," "radio frequency carrier," and/or any other similar term denoting a path or medium through which data is communicated. In addition, the term "link" may refer to a connection between two devices for the purpose of transmitting and receiving information over a Radio Access Technology (RAT).

In this example,

connections

103 and 104 are shown as air interfaces to enable communicative coupling, and may be consistent with a cellular communication protocol, such as a global system for mobile communications (GSM) protocol, a Code Division Multiple Access (CDMA) network protocol, a push-to-talk (PTT) protocol, a cellular PTT (poc) protocol, a Universal Mobile Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a fifth generation (5G) protocol, a New Radio (NR) protocol, and/or any other communication protocol discussed herein. In an embodiment, the UE 101 may exchange communication data directly via the ProSe interface 105. The ProSe interface 105 may alternatively be referred to as a Sidelink (SL) interface 105 and may include one or more logical channels including, but not limited to, a Physical Sidelink Control Channel (PSCCH), a physical sidelink shared channel (PSCCH), a Physical Sidelink Discovery Channel (PSDCH), and a Physical Sidelink Broadcast Channel (PSBCH).

UE 101b is shown configured to access an Access Point (AP)106 (also referred to as "WLAN node 106", "WLAN terminal 106", or "WT 106", etc.) via a connection 107. The connection 107 may comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, where the AP106 would comprise a wireless fidelity (WiFi) router. In this example, the AP106 is shown connected to the internet without being connected to the core network of the wireless system (described in further detail below). In various embodiments, UE 101b, RAN 110, and AP106 may be configured to utilize LTE-WLAN aggregation (LWA) operations and/or WLAN LTE/WLAN radio level integration (LWIP) operations with IPsec tunneling. LWA operation may involve UE 101b in RRC _ CONNECTED being configured by RAN node 111 to utilize radio resources of LTE and WLAN. The LWIP operation may involve the UE 101b using WLAN radio resources (e.g., connection 107) via an internet protocol security (IPsec) protocol tunnel to authenticate and encrypt packets (e.g., Internet Protocol (IP) packets) sent over the connection 107. An IPsec tunnel may include encapsulating the entire original IP packet and adding a new packet header to protect the original header of the IP packet.

RAN 110 may include one or

more RAN nodes

111a and 111b (collectively referred to as "RAN node(s) 111") that enable

connections

103 and 104. As used herein, the terms "Access Node (AN)", "access point", "RAN node", and the like may describe a device that provides radio baseband functionality for data and/or voice connections between a network and one or more users. These access nodes may be referred to as Base Stations (BSs), next generation node BS (gnbs), RAN nodes, evolved nodebs (enbs), nodebs, Road Side Units (RSUs), transmission reception points (TRxP or TRP), etc., and may include ground stations (e.g., ground access points) or satellite stations that provide coverage within a geographic area (e.g., a cell). As used herein, the term "NG RAN node" or the like may refer to a RAN node 111 (e.g., a gNB) operating in the NR or 5G system 100, and the term "E-UTRAN node" or the like may refer to a RAN node 111 (e.g., an eNB) operating in the LTE or 4G system 100. According to various embodiments, the RAN node 111 may be implemented as one or more dedicated physical devices such as a macro cell base station and/or a Low Power (LP) base station for a femto cell, pico cell or other similar cell providing a smaller coverage area, smaller user capacity or higher bandwidth than a macro cell.

In some embodiments, all or part of the RAN node 111 may be implemented as one or more software entities running on a server computer as part of a virtual network, which may be referred to as a Cloud Radio Access Network (CRAN) and/or a virtual baseband unit pool (vbbp). In these embodiments, the CRAN or vbbp may implement RAN functional partitioning, such as: PDCP partitioning, wherein RRC and PDCP layers are operated by the CRAN/vbbp, while other layer 2 (L2) protocol entities are operated by individual RAN nodes 111; MAC/PHY division, where RRC, PDCP, RLC and MAC layers are operated by the CRAN/vbup, and PHY layers are operated by individual RAN nodes 111; or "lower PHY" division, where the RRC, PDCP, RLC, MAC layers and upper parts of the PHY layers are operated by the CRAN/vbup and lower parts of the PHY layers are operated by the individual RAN node 111. The virtualization framework allows freeing up processor cores of RAN node 111 to execute other virtualized applications. In some implementations, the individual RAN nodes 111 may represent individual gNB-DUs that are connected to the gNB-CUs via individual F1 interfaces (not shown in fig. 1). In these implementations, the gbb-DUs may include one or more remote radio heads or radio front-end modules (RFEM), and the gbb-CUs may be operated by a server (not shown) located in the RAN 110 or by a server pool in a similar manner to the CRAN/vbbp. Additionally or alternatively, one or more RAN nodes 111 may be next generation enbs (NG-enbs), which are RAN nodes that provide E-UTRA user plane and control plane protocol terminations towards the UE 101 and which are connected to the 5GC via an NG interface.

In the V2X scenario, one or more RAN nodes 111 may be or act as RSUs. The term "roadside unit" or "RSU" may refer to any transportation infrastructure entity for V2X communication. The RSU may be implemented in or by a suitable RAN node or a fixed (or relatively stationary) UE, where the RSU in or by the UE may be referred to as a "UE-type RSU", the RSU in or by the eNB may be referred to as an "eNB-type RSU", the RSU in or by the gNB may be referred to as a "gNB-type RSU", and so on. In one example, an RSU is a computing device coupled with radio frequency circuitry located at the curb side that provides connectivity support for a passing vehicle UE 101(vUE 101). The RSU may also include internal data storage circuitry for storing intersection map geometry, traffic statistics, media, and applications/software for sensing and controlling ongoing vehicle and pedestrian traffic. The RSU may operate on the 5.9GHz Direct Short Range Communication (DSRC) band to provide very low latency communications required for high speed events, such as collision avoidance, traffic warnings, etc. Additionally or alternatively, the RSU may operate on the cellular V2X frequency band to provide the low latency communications described above as well as other cellular communication services. Additionally or alternatively, the RSU may operate as a WiFi hotspot (2.4GHz band) and/or provide a connection to one or more cellular networks to provide uplink and downlink communications. The computing device(s) and some or all of the radio frequency circuitry of the RSU may be enclosed in a weatherproof enclosure suitable for outdoor installation, and may include a network interface controller to provide wired (e.g., ethernet) connectivity to a traffic signal controller and/or a backhaul network.

Any RAN node 111 may terminate the air interface protocol and may be the first point of contact for the UE 101. In some embodiments, any RAN node 111 may fulfill various logical functions of RAN 110, including but not limited to Radio Network Controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

In an embodiment, the UEs 101 may be configured to communicate with each other or any of the RAN nodes 111 over a multicarrier communication channel in accordance with various communication techniques, such as, but not limited to, Orthogonal Frequency Division Multiple Access (OFDMA) communication techniques (e.g., for downlink communications) or single carrier frequency division multiple access (SC-FDMA) communication techniques (e.g., for uplink and ProSe or sidelink communications), using Orthogonal Frequency Division Multiplexing (OFDM) communication signals, although the scope of the embodiments is not limited in this respect. The OFDM signal may include a plurality of orthogonal subcarriers.

In some embodiments, the downlink resource grid may be used for downlink transmissions from any RAN node 111 to the UE 101, while uplink transmissions may use similar techniques. The grid may be a time-frequency grid, referred to as a resource grid or time-frequency resource grid, which is the physical resource in the downlink per slot. Such a time-frequency plane representation is common practice for OFDM systems, which makes radio resource allocation intuitive. Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one time slot in a radio frame. The smallest time-frequency unit in the resource grid is represented as a resource element. Each resource grid includes a plurality of resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block comprises a set of resource elements; in the frequency domain, this may represent the minimum amount of resources that can currently be allocated. There are several different physical downlink channels transmitted using such resource blocks.

According to various embodiments, UE 101 and RAN node 111 communicate (e.g., transmit and receive) data over a licensed medium (also referred to as "licensed spectrum" and/or "licensed band") and an unlicensed shared medium (also referred to as "unlicensed spectrum and/or" unlicensed band "). The licensed spectrum may include channels operating in a frequency range of about 400MHz to about 3.8GHz, while the unlicensed spectrum may include a 5GHz band.

To operate in unlicensed spectrum, the UE 101 and RAN node 111 may operate using Licensed Assisted Access (LAA), enhanced LAA (elaa), and/or other elaa (felaa) mechanisms. In these implementations, UE 101 and RAN node 111 may perform one or more known medium sensing operations and/or carrier sensing operations to determine whether one or more channels in the unlicensed spectrum are unavailable or otherwise occupied prior to transmission in the unlicensed spectrum. The medium/carrier sensing operation may be performed according to a Listen Before Talk (LBT) protocol.

LBT is a mechanism in which a device (e.g., UE 101, RAN node 111,112, etc.) senses a medium (e.g., channel or carrier frequency) and transmits when the medium is sensed to be idle (or when a particular channel in the medium is sensed to be unoccupied). The medium sensing operation may include Clear Channel Assessment (CCA) that utilizes at least Energy Detection (ED) to determine whether other signals are present on the channel in order to determine whether the channel is occupied or clear. The LBT mechanism allows the cellular/LAA network to coexist with incumbent systems in unlicensed spectrum and with other LAA networks. ED may include sensing Radio Frequency (RF) energy over an expected transmission band for a period of time and comparing the sensed RF energy to a predetermined or configured threshold.

Generally, an incumbent system in the 5GHz band is a WLAN based on IEEE 802.11 technology. WLANs employ a contention-based channel access mechanism known as carrier sense multiple access with collision avoidance (CSMA/CA). Here, when a WLAN node (e.g., a Mobile Station (MS) such as UE 101, AP 106) intends to transmit, the WLAN node may first perform a CCA prior to the transmission. In addition, a back-off mechanism is used to avoid collisions in the case where more than one WLAN node senses the channel as idle and transmits at the same time. The back-off mechanism may be a counter drawn randomly within the Contention Window Size (CWS) that is exponentially increased when collisions occur and reset to a minimum value when a transmission is successful. The LBT mechanism designed for LAA is somewhat similar to CSMA/CA of WLAN. In some implementations, an LBT procedure for a DL or UL transmission burst including PDSCH or PUSCH transmissions, respectively, may have an LAA contention window of variable length between X and Y extended cca (ecca) slots, where X and Y are minimum and maximum values of a CWS for the LAA. In one example, the minimum CWS for LAA transmission may be 9 microseconds (μ β); however, the size of the CWS and the Maximum Channel Occupancy Time (MCOT) (e.g., transmission bursts) may be based on government regulatory requirements.

The LAA mechanism is established based on the Carrier Aggregation (CA) technique of the LTE-Advanced (LTE-Advanced) system. In CA, each aggregated carrier is referred to as a Component Carrier (CC). The CCs may have bandwidths of 1.4, 3, 5, 10, 15, or 20MHz, and may be aggregated for up to five CCs, and thus, the maximum aggregated bandwidth is 100 MHz. In a Frequency Division Duplex (FDD) system, the number of aggregated carriers may be different for DL and UL, where the number of UL CCs is equal to or lower than the number of DL component carriers. In some cases, individual CCs may have different bandwidths than other CCs. In a Time Division Duplex (TDD) system, the number of CCs and the bandwidth of each CC are typically the same for DL and UL.

The CA also includes individual serving cells to provide individual CCs. The coverage of the serving cell may be different, e.g., because CCs on different frequency bands will experience different path losses. A primary serving cell or primary cell (PCell) may provide a primary cc (pcc) for both UL and DL and may handle Radio Resource Control (RRC) and non-access stratum (NAS) related activities. The other serving cells are referred to as secondary cells (scells), and each SCell may provide a separate secondary cc (scc) for both UL and DL. SCCs may be added and removed as needed, while changing the PCC may require the UE 101 to undergo handover. In LAA, eLAA, and feLAA, some or all scells may operate in unlicensed spectrum (referred to as "LAA scells"), and the LAA scells are assisted by pcells operating in licensed spectrum. When a UE is configured with more than one LAA SCell, the UE may receive a UL grant on the configured LAA SCell, the UL grant indicating different Physical Uplink Shared Channel (PUSCH) starting positions within the same subframe.

The Physical Downlink Shared Channel (PDSCH) may carry user data and higher layer signaling to the UE 101. A Physical Downlink Control Channel (PDCCH) may carry information on a transport format and resource allocation related to a PDSCH channel, and the like. It may also inform the UE 101 of transport format, resource allocation and H-ARQ (hybrid automatic repeat request) information related to the uplink shared channel. In general, downlink scheduling (allocation of control and shared channel resource blocks to UEs 101b within a cell) may be performed at any RAN node 111 based on channel quality information fed back from any UE 101. The downlink resource allocation information may be sent on a PDCCH for (e.g., allocated to) each UE 101.

The PDCCH may use Control Channel Elements (CCEs) to convey control information. The PDCCH complex-valued symbols may first be organized into quadruplets before mapping to resource elements, which may then be permuted using a sub-block interleaver for rate matching. Each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements called Resource Element Groups (REGs). Four Quadrature Phase Shift Keying (QPSK) symbols may be mapped to each REG. The PDCCH may be transmitted using one or more CCEs, depending on the size of Downlink Control Information (DCI) and channel conditions. Four or more different PDCCH formats with different numbers of CCEs may be defined in LTE (e.g., aggregation level, L ═ 1, 2, 4, or 8).

Some embodiments may use the concept of resource allocation for control channel information, which is an extension of the above-described concept. For example, some embodiments may use an Enhanced Physical Downlink Control Channel (EPDCCH) that uses PDSCH resources for control information transmission. The EPDCCH may be transmitted using one or more Enhanced Control Channel Elements (ECCEs). Similar to the above, each ECCE may correspond to nine sets of four physical resource elements referred to as Enhanced Resource Element Groups (EREGs). In some cases, ECCE may have other numbers of EREGs.

The RAN nodes 111 may be configured to communicate with each other via an interface 112. In embodiments where system 100 is an LTE system, interface 112 may be an X2 interface 112. An X2 interface may be defined between two or more RAN nodes 111 (e.g., two or more enbs, etc.) connected to the EPC 120 and/or two enbs connected to the EPC 120. In some implementations, the X2 interfaces may include an X2 user plane interface (X2-U) and an X2 control plane interface (X2-C). The X2-U may provide a flow control mechanism for user data packets transmitted over the X2 interface and may be used to communicate information about user data transfer between enbs. For example, X2-U may provide specific sequence number information for user data transmitted from a master enb (menb) to a secondary enb (senb); information on successful in-order transmission of PDCP PDUs for user data from the SeNB to the UE 101; information of PDCP PDUs not delivered to the UE 101; information on a current minimum required buffer size at the SeNB for transmitting user data to the UE; and so on. X2-C may provide intra-LTE access mobility functions including context transfer from source eNB to target eNB, user plane transfer control, etc.; a load management function; and an inter-cell interference coordination function.

In embodiments where system 100 is a 5G or NR system, interface 112 may be an Xn interface 112. An Xn interface is defined between two or more RAN nodes 111 (e.g., two or more gnbs, etc.) connected to the 5GC 120, between a RAN node 111 (e.g., a gNB) connected to the 5GC 120 and an eNB, and/or between two enbs connected to the 5GC 120. In some implementations, the Xn interface can include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. The Xn-U can provide unsecured transport of user plane PDUs and support/provide data forwarding and flow control functionality. Xn-C may provide: management and error handling functions; managing the function of the Xn-C interface; mobility support for a UE 101 in CONNECTED mode (e.g., CM-CONNECTED) includes functionality to manage CONNECTED mode UE mobility between one or more RAN nodes 111. Mobility support may include context transfer from the old (source) serving RAN node 111 to the new (target) serving RAN node 111; and control of user plane tunnels between the old (source) serving RAN node 111 and the new (target) serving RAN node 111. The protocol stack of the Xn-U may include a transport network layer established above an Internet Protocol (IP) transport layer and a GTP-U layer above UDP(s) and/or IP layers for carrying user plane PDUs. The Xn-C protocol stack may include an application layer signaling protocol, referred to as the Xn application protocol (Xn-AP), and a transport network layer built over SCTP. SCTP can be located above the IP layer and can provide guaranteed delivery of application layer messages. In the transport IP layer, point-to-point transport is used to deliver signaling PDUs. In other implementations, the Xn-U protocol stack and/or the Xn-C protocol stack may be the same as or similar to the user plane and/or control plane protocol stack(s) shown and described herein.

RAN 110 is shown communicatively coupled to a core network, in this embodiment, Core Network (CN) 120. CN 120 may include a plurality of network elements 122 configured to provide various data and telecommunications services to clients/subscribers (e.g., users of UE 101) connected to CN 120 through RAN 110. The term "network element" may describe a physical or virtualized device used to provide wired or wireless communication network services. The term "network element" may be considered synonymous with and/or referred to as: a networking computer, network hardware, network device, router, switch, hub, bridge, radio network controller, radio access network device, gateway, server, Virtualized Network Function (VNF), Network Function Virtualization Infrastructure (NFVI), and/or the like. The components of CN 120 may be implemented in one physical node or separate physical nodes, including components that read and execute instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In some embodiments, Network Function Virtualization (NFV) may be used to virtualize any or all of the above network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). Logical instantiations of the CN 120 may be referred to as network slices, and logical instantiations of a portion of the CN 120 may be referred to as network subslices. The NFV architecture and infrastructure may be used to virtualize one or more network functions or be executed by dedicated hardware onto physical resources including a combination of industry standard server hardware, storage hardware, or switches. In other words, the NFV system may be used to perform a virtual or reconfigurable implementation of one or more EPC components/functions.

In general, the application server 130 may be an element that provides applications that use IP bearer resources with a core network (e.g., UMTS Packet Service (PS) domain, LTE PS data services, etc.). The application server 130 may also be configured to support one or more communication services (e.g., voice over internet protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UE 101 via the EPC 120.

In an embodiment, the CN 120 may be a 5GC (referred to as "5 GC 120" or the like), and the RAN 110 may be connected with the CN 120 via the NG interface 113. In an embodiment, the NG interface 113 may be divided into two parts: a NG user plane (NG-U) interface 114 that carries traffic data between RAN node 111 and User Plane Functions (UPFs); and S1 control plane (NG-C) interface 115, which is the signaling interface between RAN node 111 and the AMF.

In an embodiment, the CN 120 may be a 5G CN (referred to as "5 GC 120," etc.), while in other embodiments, the CN 120 may be an Evolved Packet Core (EPC). In the case where CN 120 is an EPC (referred to as "EPC 120," etc.), RAN 110 may connect with CN 120 via S1 interface 113. In an embodiment, the S1 interface 13 may be divided into two parts: an S1 user plane (S1-U) interface 114, which carries traffic data between the RAN node 111 and the serving gateway (S-GW); and S1-Mobility Management Entity (MME) interface 115, which is a signaling interface between RAN node 111 and the MME.

In order to inform the frequency resource allocation for multi-slot transmission, both the starting subchannel and the number of allocated subchannels are required. The starting subchannel and the number of allocated subchannels may be informed jointly or separately. First, the frequency resource allocation for multi-slot transmission is described in detail below in conjunction with notification.

In case there are S available subchannels in a slot and n slots after the first slot (the first slot and the n slots are to carry the same Transport Block (TB)), the number of different allocations (ranging from 1 to S) may be

For the particular case where n is 2, the number of different allocations may be

The value of n may be obtained from separate time resource signaling.

Fig. 2 illustrates a flow diagram of a method 200 for notifying frequency resource allocation for multi-slot transmission in accordance with some embodiments of the present disclosure. The method 200 may be used to jointly inform the starting sub-channel and the number of allocated sub-channels. The method 200 may be performed by a sender UE and may include

steps

210, 220, 230, and 240.

In 210, a first index a may be generated based on the number n of additional slots after the first slot, the number S of available subchannels in each additional slot, and the number m of assigned subchannels in each additional slot. As described above, the first slot and the additional slot are used to carry the same TB.

In some embodiments, the first index a may be determined by equation (1):

wherein m is equal to or less than S.

In 220, the number of additional slots n, the number of available subchannels in each additional slot S, the number of assigned subchannels in each additional slot m, and the index of the starting subchannel k for each additional slot may be based on_j(e.g., a list of starting subchannel indices for each slot: k₀,…,k_n-1) A second index b is generated.

In some embodiments, the second index b may be determined by equation (2):

at 230, a third index I may be generated based on the sum of the first index a and the second index b, as shown in equation (3):

I＝a+b (3)。

the third index I is used for notifying m and k_jAnd both. In other words, the receiving UE may learn the frequency resource allocation for the multi-slot transmission from the single third index.

In 240, the third index I may be encoded in the SCI of the PSCCH for transmission to the recipient UE.

In the method 200, the sender UE may be based on S, m, n, and k_jA third index I is generated and included in the SCI for transmission to the recipient UE.

For example, in the case where n is 2, the first index a may be determined based on formula (4), the second index b may be determined based on formula (5), and the third index I may be determined based on formula (3) above.

b＝k₀+(S+1-m)k₁ (5)

For example, in the case where n is 3, the first index a may be determined based on formula (6), the second index b may be determined based on formula (7), and the third index I may be determined based on formula (3) described above.

b＝k₀+(S+1-m)k₁+(S+1-m)²k₂ (7)

In the example of fig. 3, it is assumed that there are three available subchannels in each slot and that two slots follow the first slot of the same TB, i.e. S-3 and n-2 are defined as part of the pool definition. As shown in FIG. 3, k₀＝0,k₁1. In addition, one subchannel is allocated in each slot, i.e., m is 1. According to equations (1) and (2) (or equations (4) and (5)), it is determined that a is 0 and b is 3. According to equation (3), I-3 is determined.

In another example, n ═ 1 is applicable. In yet another example, other values of n are also applicable. The present disclosure is not limited in this respect.

The embodiments described above in connection with fig. 2 and 3 are described from the perspective of the sender UE. In other words, the embodiments describe a coding process for notifying frequency resource allocation for multi-slot transmission. Some embodiments will be described below from the perspective of the receiving UE, i.e. a decoding procedure for notifying frequency resource allocation for multi-slot transmission will be described.

Fig. 4 illustrates a flow diagram of a method 400 for notifying frequency resource allocation for multi-slot transmission in accordance with some embodiments of the present disclosure. The method 400 may be performed by a recipient UE and may include

steps

410, 420, 430, and 440.

In 410, the SCI of the PSCCH received from the sender UE may be decoded to obtain a single index I. The index I may inform the frequency resource allocation for multi-slot transmission.

In 420, the time resource signaling received from the transmitting UE may be decoded to obtain a number n of additional time slots after the first time slot. The first slot and the additional slot are used to carry the same TB.

In 430, the number S of available subchannels in each additional time-slot may be obtained according to the resource pool configuration.

In 440, the number of allocated subchannels m in each additional slot and the index k of the starting subchannel for each additional slot may be determined based on the index I, the number of additional slots n, and the number of available subchannels S in each additional slot_j。

In some embodiments, the first sub-index a may be determined based on equation (8)_m：

The number of allocated subchannels, m, in each additional time-slot may be determined based on equation (9):

a_m≤I<a_m+1wherein a is₁＝0,a_S+1＝∞ (9)。

In some embodiments, a may be subtracted from I_mTo determine a second sub-index b, e.g. publicFormula (10):

b＝I-a_m (10)。

the index k of the starting subchannel for each additional slot may be determined based on equation (11)_j：

Wherein modulo denotes a modulo operation.

In the example of fig. 5, it is assumed that there are three available subchannels in each slot and that there are two slots after the first slot of the same TB, i.e., the receiving UE obtains S-3 and n-2 from the resource pool configuration and time resource signaling, respectively. In addition, in the example of fig. 5, it is assumed that the receiving UE receives I ═ 11 from the transmitting UE. According to equation (8), a is determined_mIs {0,9,13, ∞ }. According to equation (9), m is determined to be 2. According to equation (10), b is determined to be 2. According to equation (11), k is determined₀0 and k₁＝1。

With the above-described method for notifying frequency resource allocation for multi-slot transmission according to some embodiments, a receiving UE may determine the number m of allocated subchannels in each additional slot and the index k of the starting subchannel for each additional slot from a single index I received in the SCI_jAnd both. In other words, with the above method, the receiving UE can know the frequency resource allocation for multi-slot transmission from a single index I received in the SCI. In this way, the minimum number of bits in the SCI is transmitted. This enables the control channel to achieve maximum coverage with minimal signaling overhead.

Some embodiments of jointly informing frequency resource allocations for multi-slot transmissions are described above. Still other methods may jointly inform the frequency resource allocation for multi-slot transmission. For example, if only one slot is allocated after the first slot, i.e., n is 1, only the number of sub-channels allocated for the slot may be notified. If two slots, i.e., n-2, are allocated after the first slot, a standard Resource Indication Value (RIV) of a frequency resource of a second slot of the n slots may be notified. If more than two time slots are allocated after the first time slot, i.e. n >2, the above notification method of frequency resource allocation for multi-slot transmission can be employed.

In some embodiments, the frequency resource allocation for multi-slot transmission may be signaled separately. For example, RIV signaling may be used separately for each of the n slots. In the case where only a single slot is allocated, only the number of sub-channels allocated for the slot is notified.

It can be seen that the frequency resource allocations for multi-slot transmission can be signaled jointly or separately. Similarly, the time resource allocation for multi-slot transmission may be signaled jointly or separately.

In some embodiments, a single index may be encoded by the sending UE to inform the receiving UE. The receiving UE may then determine the number n of additional slots after the first slot and the offset of the additional slots from the first slot based on the index.

In some embodiments, the number n of additional time slots may be encoded in a first time resource signaling for notification to the receiving UE, and the offset of the additional time slots relative to the first time slots may be encoded in another second time resource signaling for notification to the receiving UE. The receiving UE may then decode two different time resource signalings separately to obtain the number n and the offset of the additional time slots with respect to the first time slot.

The above notifications of frequency resource and time resource allocations for multi-slot transmissions may be joint or separate. These different notification methods may be combined in any manner. For example, jointly informing the frequency resource allocation for multi-slot transmission and separately informing the time resource allocation for multi-slot transmission may be used to inform the time and frequency resources. As another example, the joint notification of the frequency resource allocation for multi-slot transmission and the joint notification of the time resource allocation for multi-slot transmission may be used to notify of time and frequency resources. For another example, separately informing the frequency resource allocation for multi-slot transmission and separately informing the time resource allocation for multi-slot transmission may be used to inform the time and frequency resources. As another example, separately informing the frequency resource allocation for multi-slot transmission and jointly informing the time resource allocation for multi-slot transmission may be used to inform of time and frequency resources. The present disclosure is not limited in this respect.

Fig. 6 illustrates example components of a device 600 according to some embodiments. In some embodiments, device 600 may include application circuitry 602, baseband circuitry 604, Radio Frequency (RF) circuitry 606, Front End Module (FEM) circuitry 608, one or more antennas 610, and Power Management Circuitry (PMC)612 coupled together at least as shown. The illustrated components of the apparatus 600 may be included in a UE or AN. In some embodiments, the apparatus 600 may include fewer elements (e.g., the AN may not use the application circuitry 602, but rather include a processor/controller to process IP data received from the EPC). In some embodiments, device 600 may include additional elements, such as memory/storage devices, displays, cameras, sensors, or input/output (I/O) interfaces. In other embodiments, the components described below may be included in more than one device (e.g., for a Cloud-RAN (C-RAN) implementation, the circuitry may be included separately in more than one device).

The application circuitry 602 may include one or more application processors. For example, the application circuitry 602 may include circuitry such as, but not limited to: one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, etc.). The processor may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications and/or operating systems to run on the device 600. In some embodiments, the processor of the application circuitry 602 may process IP packets received from the EPC.

Baseband circuitry 604 may include circuitry such as, but not limited to: one or more single-core or multi-core processors. Baseband circuitry 604 may include one or more baseband processors or control logic to process baseband signals received from the receive signal path of RF circuitry 606 and to generate baseband signals for the transmit signal path of RF circuitry 606. Baseband processing circuitry 604 may interface with application circuitry 602 to generate and process baseband signals and control operation of RF circuitry 606. For example, in some embodiments, the baseband circuitry 604 may include a third generation (3G) baseband processor 604A, a fourth generation (4G) baseband processor 604B, a fifth generation (5G) baseband processor 604C, or other baseband processor(s) 604D for other existing generations, generations in development or to be developed in the future (e.g., sixth generation (6G), etc.). Baseband circuitry 604 (e.g., one or more of baseband processors 604A-D) may handle various radio control functions that support communication with one or more radio networks via RF circuitry 606. In other embodiments, some or all of the functions of the baseband processors 604A-D may be included in modules stored by the memory 604G and executed via a Central Processing Unit (CPU) 604E. The radio control functions may include, but are not limited to: signal modulation/demodulation, encoding/decoding, radio frequency shifting, etc. In some embodiments, the modulation/demodulation circuitry of baseband circuitry 604 may include Fast Fourier Transform (FFT), precoding, and/or constellation mapping/demapping functionality. In some embodiments, the encoding/decoding circuitry of baseband circuitry 604 may include convolution, tail-biting convolution, turbo, Viterbi (Viterbi), and/or Low Density Parity Check (LDPC) encoder/decoder functionality. Embodiments of modulation/demodulation and encoder/decoder functions are not limited to these examples, and other suitable functions may be included in other embodiments.

In some embodiments, the baseband circuitry 604 may include one or more audio Digital Signal Processors (DSPs) 604F. The audio DSP(s) 604F may include elements for compression/decompression and echo cancellation, and may include other suitable processing elements in other embodiments. In some embodiments, components of the baseband circuitry may be combined as appropriate in a single chip, a single chipset, or disposed on the same circuit board. In some embodiments, some or all of the constituent components of the baseband circuitry 604 and the application circuitry 602 may be implemented together, for example, on a system on a chip (SOC).

In some embodiments, the baseband circuitry 604 may provide communications compatible with one or more radio technologies. For example, in some embodiments, baseband circuitry 604 may support communication with an Evolved Universal Terrestrial Radio Access Network (EUTRAN) or other Wireless Metropolitan Area Network (WMAN), Wireless Local Area Network (WLAN), Wireless Personal Area Network (WPAN). Embodiments in which the baseband circuitry 604 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

RF circuitry 606 may support communication with a wireless network using modulated electromagnetic radiation through a non-solid medium. In various embodiments, RF circuitry 606 may include switches, filters, amplifiers, and the like to facilitate communication with the wireless network. RF circuitry 606 may include a receive signal path that may include circuitry to down-convert RF signals received from FEM circuitry 608 and provide baseband signals to baseband circuitry 604. RF circuitry 606 may also include a transmit signal path that may include circuitry to up-convert baseband signals provided by baseband circuitry 604 and provide RF output signals to FEM circuitry 608 for transmission.

In some embodiments, the receive signal path of RF circuitry 606 may include mixer circuitry 606a, amplifier circuitry 606b, and filter circuitry 606 c. In some embodiments, the transmit signal path of RF circuitry 606 may include filter circuitry 606c and mixer circuitry 606 a. The RF circuitry 606 may also include synthesizer circuitry 606d for synthesizing frequencies for use by the mixer circuitry 606a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 606a of the receive signal path may be configured to down-convert the RF signal received from the FEM circuitry 608 based on the synthesized frequency provided by the synthesizer circuitry 606 d. The amplifier circuit 606b may be configured to amplify the downconverted signal, and the filter circuit 606c may be a Low Pass Filter (LPF) or a Band Pass Filter (BPF) configured to remove unwanted signals from the downconverted signal to generate an output baseband signal. The output baseband signal may be provided to baseband circuitry 604 for further processing. In some embodiments, the output baseband signal may be a zero frequency baseband signal, but this is not required. In some embodiments, mixer circuit 606a of the receive signal path may comprise a passive mixer, although the scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuitry 606a of the transmit signal path may be configured to up-convert the input baseband signal based on the synthesis frequency provided by the synthesizer circuitry 606d to generate the RF output signal for the FEM circuitry 608. The baseband signal may be provided by baseband circuitry 604 and may be filtered by filter circuitry 606 c.

In some embodiments, mixer circuitry 606a of the receive signal path and mixer circuitry 606a of the transmit signal path may comprise two or more mixers and may be arranged for quadrature down-conversion and/or up-conversion, respectively.

In some embodiments, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuits 606a of the receive signal path and the mixer circuits 606a of the transmit signal path may be arranged for direct down-conversion and/or direct up-conversion, respectively. In some embodiments, mixer circuit 606a of the receive signal path and mixer circuit 606a of the transmit signal path may be configured for superheterodyne operation.

In some embodiments, the output baseband signal and the input baseband signal may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternative embodiments, the output baseband signal and the input baseband signal may be digital baseband signals. In these alternative embodiments, RF circuitry 606 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry, and baseband circuitry 604 may include a digital baseband interface to communicate with RF circuitry 606.

In some dual-mode embodiments, separate radio IC circuitry may be provided to process signals for each spectrum, although the scope of the embodiments is not limited in this respect.

In some embodiments, synthesizer circuit 606d may be a fractional-N or fractional-N/N +1 type synthesizer, although the scope of embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuit 606d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer including a phase locked loop with a frequency divider.

The synthesizer circuit 606d may be configured to synthesize an output frequency for use by the mixer circuit 606a of the RF circuit 606 based on the frequency input and the divider control input. In some embodiments, synthesizer circuit 606d may be a fractional-N/N +1 type synthesizer.

In some embodiments, the frequency input may be provided by a Voltage Controlled Oscillator (VCO), but this is not required. The divider control input may be provided by the baseband circuitry 604 or the application processor 602 depending on the desired output frequency. In some embodiments, the divider control input (e.g., N) may be determined from a look-up table based on the channel indicated by the application processor 602.

Synthesizer circuit 606d of RF circuit 606 may include a frequency divider, a Delay Locked Loop (DLL), a multiplexer, and a phase accumulator. In some embodiments, the divider may be a dual-mode divider (DMD) and the phase accumulator may be a Digital Phase Accumulator (DPA). In some embodiments, the DMD may be configured to divide an input signal by N or N +1 (e.g., based on a carry out) to provide a fractional division ratio. In some example embodiments, a DLL may include a set of cascaded, tunable delay elements, a phase detector, a charge pump, and a D-type flip-flop. In these embodiments, the delay elements may be configured to decompose the VCO period into at most Nd equal phase groups, where Nd is the number of delay elements in the delay line. In this manner, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

In some embodiments, synthesizer circuit 606d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used with a quadrature generator and divider circuit to generate a plurality of signals having a plurality of different phases from one another at the carrier frequency. In some embodiments, the output frequency may be the LO frequency (fLO). In some embodiments, RF circuit 606 may include an IQ/polarity converter.

FEM circuitry 608 may include a receive signal path that may include circuitry configured to operate on RF signals received from one or more antennas 610, amplify the received signals, and provide amplified versions of the received signals to RF circuitry 606 for further processing. FEM circuitry 608 may also include a transmit signal path, which may include circuitry configured to amplify signals provided for transmission by RF circuitry 606 for transmission by one or more of one or more antennas 610. In various embodiments, amplification through the transmit signal path or the receive signal path may be done only in RF circuitry 606, only in FEM 608, or both RF circuitry 606 and FEM 608.

In some embodiments, FEM circuitry 608 may include TX/RX switches to switch between transmit mode and receive mode operation. The FEM circuitry may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include a Low Noise Amplifier (LNA) to amplify the received RF signal and provide the amplified received RF signal as an output (e.g., to RF circuitry 606). The transmit signal path of FEM circuitry 608 may include a Power Amplifier (PA) to amplify an input RF signal (e.g., provided by RF circuitry 606) and one or more filters to generate an RF signal for subsequent transmission (e.g., by one or more of one or more antennas 610).

In some embodiments, the PMC 612 may manage power provided to the baseband circuitry 604. Specifically, the PMC 612 may control power selection, voltage scaling, battery charging, or DC-DC conversion. The PMC 612 may generally be included when the device 600 is capable of being powered by a battery, for example, when the device is included in a UE. The PMC 612 may improve power conversion efficiency while providing desired implementation size and heat dissipation characteristics.

Although figure 6 shows the PMC 612 coupled only to the baseband circuitry 604. However, in other embodiments, PMC 612 may additionally or alternatively be coupled with and perform similar power management operations on other components, such as, but not limited to, application circuitry 602, RF circuitry 606, or FEM 608.

In some embodiments, PMC 612 may control or otherwise be part of various power saving mechanisms of device 600. For example, if the device 600 is in an RRC _ Connected state where it is still Connected to the RAN node when the device 600 expects to receive traffic soon, then after a period of inactivity it may enter a state called discontinuous reception mode (DRX). During this state, the device 600 may be powered down for a brief interval of time, thereby saving power.

If there is no data traffic activity for an extended period of time, the device 600 may transition to an RRC _ Idle state in which the device 600 is disconnected from the network and no operations such as channel quality feedback, handover, etc. are performed. The device 600 enters a very low power state and performs paging, where the device 600 again periodically wakes up to listen to the network and then powers down again. The device 600 may not receive data in this state and it may transition back to the RRC Connected state in order to receive data.

The additional power-save mode may allow the device to be unavailable to the network for a period longer than the paging interval (ranging from a few seconds to a few hours). During this time, the device is completely unable to access the network and may be completely powered down. Any data transmitted during this period will incur a significant delay and the delay is assumed to be acceptable.

The processor of the application circuitry 602 and the processor of the baseband circuitry 604 may be used to execute elements of one or more instances of a protocol stack. For example, the processor of the baseband circuitry 604, alone or in combination, may be configured to perform layer 3, layer 2, or layer 1 functions, while the processor of the application circuitry 604 may utilize data (e.g., packet data) received from these layers and further perform layer 4 functions (e.g., Transmission Communication Protocol (TCP) and User Datagram Protocol (UDP) layers). As mentioned herein, layer 3 may include an RRC layer. As referred to herein, layer 2 may include a Medium Access Control (MAC) layer, a Radio Link Control (RLC) layer, and a Packet Data Convergence Protocol (PDCP) layer. As referred to herein, layer 1 may comprise the Physical (PHY) layer of the UE/RAN node.

Fig. 7 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methodologies discussed herein, according to some example embodiments. In particular, fig. 7 shows a diagrammatic representation of hardware resources 700, which includes one or more processors (or processor cores) 710, one or more memory/storage devices 720, and one or more communication resources 730, each of which may be communicatively coupled by a bus 740. For embodiments utilizing node virtualization (e.g., NFV), hypervisor 702 may be executed to provide an execution environment for one or more network slices/subslices to utilize hardware resources 700.

Processor 710 (e.g., a Central Processing Unit (CPU), a Reduced Instruction Set Computing (RISC) processor, a Complex Instruction Set Computing (CISC) processor, a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP) such as a baseband processor, an Application Specific Integrated Circuit (ASIC), a Radio Frequency Integrated Circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, processor 712 and processor 714.

Memory/storage 720 may include a main memory, a disk storage, or any suitable combination thereof. The memory/storage 720 may include, but is not limited to, any type of volatile or non-volatile memory, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid state storage, and the like.

Communication resources 730 may include interconnection or network interface components or other suitable devices to communicate with one or more peripherals 704 or one or more databases 706 via network 708. For example, communication resources 730 may include wired communication components (e.g., for coupling via a Universal Serial Bus (USB)), cellular communication components, NFC components, bluetooth components (e.g., bluetooth low energy), Wi-Fi components, and other communication components.

Instructions 750 may include software, programs, applications, applets, apps, or other executable code for causing at least any processor 710 to perform any one or more of the methods discussed herein. The instructions 750 may reside, completely or partially, within at least one of the processor 710 (e.g., within a processor's cache memory), the memory/storage 720, or any suitable combination thereof. Further, any portion of instructions 750 may be communicated to hardware resource 700 from any combination of peripheral device 704 or database 706. Thus, the processor 710, memory/storage 720, peripherals 704, and the memory of database 706 are examples of computer-readable and machine-readable media.

Fig. 8 illustrates an example of an infrastructure device 800 according to various embodiments. Infrastructure device 800 (or "system 800") may be implemented as a base station, a radio head, a RAN node, etc., such as RAN nodes 111 and 112 and/or AP106 shown and described previously. In other examples, system 800 may be implemented in or by a UE, application server(s) 130, and/or any other elements/devices discussed herein. The system 800 may include one or more of the following: an application circuit 805, a baseband circuit 810, one or more radio front end modules 815, a memory 820, a Power Management Integrated Circuit (PMIC) 825, a power tee circuit 830, a network controller 835, a network interface connector 840, a satellite positioning circuit 845, and a user interface 850. In some embodiments, device 800 may include additional elements, such as memory/storage, a display, a camera, sensors, or input/output (I/O) interface elements. In other embodiments, the components described below may be included in more than one device (e.g., for a cloud RAN (C-RAN) implementation, the circuitry may be included separately in more than one device).

As used herein, the term "circuitry" may refer to, be part of, or include hardware components such as the following configured to provide the described functionality: electronic circuits, logic circuits, processors (shared, dedicated, or group) and/or memories (shared, dedicated, or group), Application Specific Integrated Circuits (ASICs), field-programmable devices (FPDs) (e.g., field-programmable gate arrays (FPGAs), Programmable Logic Devices (PLDs), complex PLDs (complex PLDs, CPLDs), high-capacity PLDs (HCPLDs), structured ASICs, or System on Chip (socs)), Digital Signal Processors (DSPs), and so forth. In some embodiments, the circuitry may execute one or more software or firmware programs to provide at least some of the described functionality. Furthermore, the term "circuitry" may also refer to a combination of one or more hardware elements (or circuitry used in an electrical or electronic system) and program code for performing the functions of the program code. In these embodiments, the combination of hardware elements and program code may be referred to as a particular type of circuitry.

The terms "application circuitry" and/or "baseband circuitry" may be considered synonymous with "processor circuitry" and may be referred to as "processor circuitry". As used herein, the term "processor circuit" may refer to, be part of, or include circuitry that: the circuit is capable of sequentially and automatically performing a sequence of arithmetic or logical operations; and recording, storing and/or transmitting digital data. The term "processor circuit" may refer to one or more application processors, one or more baseband processors, physical Central Processing Units (CPUs), single-core processors, dual-core processors, tri-core processors, quad-core processors, and/or any other device capable of executing or otherwise manipulating computer-executable instructions, such as program code, software modules, and/or functional processes.

Further, the various components of the core network 120 (or CN 120 discussed previously) may be referred to as "network elements. The term "network element" may describe a physical or virtualized device used to provide wired or wireless communication network services. The term "network element" may be considered synonymous with and/or referred to as: a networking computer, networking hardware, network device, network node, router, switch, hub, bridge, radio network controller, radio access network device, gateway, server, Virtualized Network Function (VNF), Network Function Virtualization Infrastructure (NFVI), and so forth.

The application circuitry 805 may include one or more Central Processing Unit (CPU) cores and one or more of the following: a cache memory, a Low Drop Out (LDO) regulator, an interrupt controller, a Serial Interface such as SPI, I2C, or a Universal programmable Serial Interface module, a Real Time Clock (RTC), a timer-counter including interval and watchdog timers, a Universal input/output (I/O or IO), a memory card controller such as a Secure Digital (SD)/multimedia card (MMC), a Universal Serial Bus (USB) Interface, a Mobile Industrial Processor Interface (MIPI) Interface, and a Joint Test Access Group (JTAG) Test Access port. By way of example, the application circuit 805 may include one or more Intels

Or

A processor; ultramicron semiconductor (Advanced Micro Devices, AMD)

A processor, an Accelerated Processing Unit (APU), or

A processor; and so on. In some embodiments, system 800 may not utilize application circuitry 805, but may include, for example, a dedicated processor/controller to process IP data received from the EPC or 5 GC.

Additionally or alternatively, the application circuitry 805 may include circuitry such as (but not limited to) the following: one or more Field Programmable Devices (FPDs), such as Field Programmable Gate Arrays (FPGAs), etc.; programmable Logic Devices (PLDs), such as complex PLDs (cplds), high capacity PLDs (hcplds), and the like; ASICs, such as structured ASICs and the like; programmable soc (psoc); and so on. In such embodiments, the circuitry of the application circuitry 805 may comprise a logic block or logic architecture, including other interconnected resources, that may be programmed to perform various functions, such as the processes, methods, functions, etc. of the various embodiments discussed herein. In such embodiments, the circuitry of the application circuit 805 may include a storage unit (e.g., an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a static memory (e.g., Static Random Access Memory (SRAM), an antifuse, etc.) for storing logic blocks, logic architectures, data, etc. in a lookup table (LUT), and so forth.

Baseband circuitry 810 may be implemented, for example, as a solder-in substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more integrated circuits. Although not shown, baseband circuitry 810 may include one or more digital baseband systems, which may be coupled to a CPU subsystem, an audio subsystem, and an interface subsystem via an interconnection subsystem. The digital baseband subsystem may also be coupled to the digital baseband interface and the mixed signal baseband subsystem via additional interconnect subsystems. Each interconnection subsystem may include a bus system, a point-to-point connection, a Network On Chip (NOC) fabric, and/or some other suitable bus or interconnection technology, such as those discussed herein. The audio subsystem may include digital signal processing circuitry, buffer memory, program memory, voice processing accelerator circuitry, data converter circuitry such as analog-to-digital and digital-to-analog converter circuitry, analog circuitry including one or more amplifiers and filters, and/or other similar components. In an aspect of the disclosure, the baseband circuitry 810 may include protocol processing circuitry having one or more instances of control circuitry (not shown) to provide control functionality for digital baseband circuitry and/or radio frequency circuitry (e.g., radio front end module 815).

The user interface circuitry 850 may include one or more user interfaces designed to enable interaction with a user of the system 800 or peripheral component interfaces designed to enable interaction with peripheral components of the system 800. The user interface may include, but is not limited to, one or more physical or virtual buttons (e.g., a reset button), one or more indicators (e.g., a Light Emitting Diode (LED)), a physical keyboard or keypad, a mouse, a touchpad, a touch screen, a speaker or other audio emitting device, a microphone, a printer, a scanner, a headset, a display screen or display device, and so forth. The peripheral component interfaces may include, but are not limited to, a non-volatile memory port, a Universal Serial Bus (USB) port, an audio jack, a power supply interface, and the like.

The Radio Front End Module (RFEM)815 may include a millimeter wave RFEM and one or more sub-millimeter wave Radio Frequency Integrated Circuits (RFICs). In some implementations, the one or more sub-millimeter wave RFICs may be physically separate from the millimeter wave RFEM. The RFIC may include a connection to one or more antennas or antenna arrays, and the RFEM may be connected to multiple antennas. In alternative implementations, both millimeter wave and sub-millimeter wave radio functions may be implemented in the same physical radio front end module 815. RFEM 815 may include both millimeter wave and sub-millimeter wave antennas.

Memory circuit 820 may include one or more of the following: a volatile memory (or a non-volatile memory),including Dynamic Random Access Memory (DRAM) and/or Synchronous Dynamic Random Access Memory (SDRAM); and nonvolatile memory (NVM), including high speed electrically erasable memory (often referred to as flash memory), phase change random access memory (PRAM), Magnetoresistive Random Access Memory (MRAM), and the like, and may include data from one or more of the above-mentioned sources

And

a three-dimensional (3D) cross point (XPOINT) memory. Memory circuit 820 may be implemented as one or more of a solder-in package integrated circuit, a socket memory module, and a plug-in memory card.

PMIC 825 may include a voltage regulator, a surge protector, a power alarm detection circuit, and one or more backup power sources such as a battery or a capacitor. The power alarm detection circuit may detect one or more of power down (under voltage) and surge (over voltage) conditions. Power tee circuit 830 may provide power drawn from a network cable to provide both power supply and data connectivity to infrastructure device 800 using a single cable.

The network controller circuit 835 may provide connectivity to a network using a standard network interface protocol such as ethernet, GRE tunnel based ethernet, Multiprotocol Label Switching (MPLS) based ethernet, or some other suitable protocol. Network connectivity may be provided to/from infrastructure device 800 via network interface connector 840 using a physical connection, which may be electrical (commonly referred to as a "copper interconnect"), optical, or wireless. The network controller circuit 835 may include one or more special purpose processors and/or FPGAs to communicate using one or more of the above-described protocols. In some implementations, the network controller circuit 835 can include multiple controllers to provide connectivity to other networks using the same or different protocols.

The positioning circuitry 845 may include circuitry to receive and decode signals transmitted by one or more constellations of navigation satellites of a Global Navigation Satellite System (GNSS). Examples of a Navigation Satellite Constellation (or GNSS) may include the Global Positioning System (GPS) in the united states, the Global Navigation System (GLONASS) in russia, the galileo System in the european union, the beidou Navigation Satellite System in china, the regional Navigation System or the GNSS augmentation System (e.g., Indian Constellation Navigation with Indian Navigation, NAVIC), the Quasi-Zenith Satellite System (QZSS) in japan, the Satellite Integrated Doppler orbit imaging and Radio Positioning in france (dongler and Radio-Positioning Integrated by Satellite System, DORIS), and so forth. The positioning circuitry 845 may include various hardware elements (e.g., including hardware devices, such as switches, filters, amplifiers, antenna elements, and so forth, to facilitate communication over-the-air (OTA) communication) to communicate with components of a positioning network (e.g., navigation satellite constellation nodes).

Nodes or satellites of the navigation satellite constellation(s) ("GNSS nodes") may provide positioning services by continuously transmitting or broadcasting GNSS signals along a line of sight that may be used by a GNSS receiver (e.g., positioning circuitry 845 and/or positioning circuitry implemented by the UE 101 or the like) to determine its GNSS position. The GNSS signals may include a pseudorandom code known to the GNSS receiver (e.g., a sequence of ones and zeros) and a message including a time of transmission ToT (e.g., a defined point in the pseudorandom code sequence) of code epochs and a GNSS node position at ToT. A GNSS receiver may monitor/measure GNSS signals transmitted/broadcast by multiple GNSS nodes (e.g., four or more satellites) and solve various equations to determine a corresponding GNSS location (e.g., spatial coordinates). The GNSS receiver also implements a clock that is generally less stable and accurate than the atomic clock of the GNSS node, and the GNSS receiver may use the measured GNSS signals to determine a deviation of the GNSS receiver from real time (e.g., a deviation of the GNSS receiver clock from the GNSS node time). In some embodiments, the Positioning circuit 845 may include a Micro-Technology for Positioning, Navigation, and Timing (Micro-PNT) IC that uses a master Timing clock to perform position tracking/estimation without GNSS assistance.

The GNSS receiver may measure the time of arrival (ToA) of GNSS signals from multiple GNSS nodes according to its own clock. The GNSS receiver may determine a time of flight (ToF) value for each received GNSS signal based on ToA and ToT, and may then determine a three-dimensional (3D) position and clock bias based on the ToF. The 3D location may then be converted to latitude, longitude, and altitude. The positioning circuitry 845 may provide data to the application circuitry 805, which may include one or more of location data or time data. The application circuit 805 may use the time data to operate synchronously with other radio base stations (e.g., of the RAN nodes 111,112, etc.).

The components shown in fig. 8 may communicate with each other using interface circuitry. As used herein, the term "interface circuit" may refer to, be part of, or include a circuit that supports the exchange of information between two or more components or devices. The term "interface circuit" may refer to one or more hardware interfaces, such as a bus, an input/output (I/O) interface, a peripheral component interface, a network interface card, and so forth. Any suitable bus technology may be used in various implementations, which may include any number of technologies, including Industry Standard Architecture (ISA), Extended ISA (EISA), Peripheral Component Interconnect (PCI), PCI express, or any number of other technologies. The bus may be a dedicated bus, such as used in SoC-based systems. Other bus systems may be included, such as an I2C interface, an SPI interface, a point-to-point interface, and a power bus, among others.

The following paragraphs describe examples of various embodiments.

Example 1 includes a method for usingAn apparatus of a User Equipment (UE), the apparatus comprising: a Radio Frequency (RF) interface; and a processor circuit coupled with the RF interface, wherein the processor circuit is to: generating a first index a based on a number n of additional slots following a first slot, a number S of available subchannels in each of the additional slots, and a number m of allocated subchannels in each of the additional slots, wherein the first slot and the additional slots are for carrying a same Transport Block (TB); based on the number n of additional slots, the number S of available subchannels in each of the additional slots, the number m of allocated subchannels in each of the additional slots, and an index k of a starting subchannel for each of the additional slots_jGenerating a second index b; generating a third index I based on a sum of the first index a and the second index b, wherein the third index I is used to inform the number m of allocated subchannels in each of the additional slots and an index k of a starting subchannel for each of the additional slots_jBoth of them; and encoding the third index I in a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) for transmission to a recipient UE via the RF interface.

Example 2 includes the apparatus of example 1, wherein the processor circuit is to: encoding the number n of additional time slots in a first time resource signaling for transmission to the recipient UE via the RF interface.

Example 3 includes the apparatus of example 2, wherein the processor circuit is to: encoding an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the recipient UE via the RF interface.

Example 4 includes the apparatus of example 1, wherein the processor circuit is to: encoding a single index for transmission to the recipient UE, the single index for informing both the number n of additional slots and the offset of the additional slots relative to the first slot.

Example 5 includes the apparatus of example 1, wherein the processor circuit is to generate the first index a based on the following equation:

example 6 includes the apparatus of example 1, wherein the processor circuit is to generate the second index b based on the following equation:

example 7 includes the apparatus of any one of examples 1 to 6, wherein n-1 or n-2.

Example 8 includes an apparatus for a User Equipment (UE), the apparatus comprising: a Radio Frequency (RF) interface; and a processor circuit coupled with the RF interface, wherein the processor circuit is to: decoding a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) received from a sender UE via the RF interface to obtain a single index I; decoding time resource signaling received from the sender UE via the RF interface to obtain a number n of additional time slots after a first time slot; obtaining a number S of available subchannels in each of the additional time-slots according to a resource pool configuration; and determining the number of allocated subchannels m in each of the additional slots and the index k of the starting subchannel for each of the additional slots based on the index I, the number of additional slots n, and the number of available subchannels S in each of the additional slots_j。

Example 9 includes the apparatus of example 8, wherein the processor circuit is to: based on the formula

To determine a first sub-index a_m(ii) a And based on formula a_m≤I<a_m+1Determining the number m of allocated subchannels in each of said additional time-slots, wherein a₁＝0,a_S+1＝∞。

Example 10 includes the apparatus of example 9, wherein the processor circuit is to: based on I minus a_mTo determine a second sub-index b; and based on a formula

To determine an index k of a starting sub-channel for each of the additional slots_j。

Example 11 includes the apparatus of example 8, wherein the processor circuit is to: decoding the time resource signaling to obtain an offset of the additional slot relative to the first slot.

Example 12 includes the apparatus of example 8, wherein the processor circuit is to: decoding additional time resource signaling to obtain an offset of the additional slot relative to the first slot.

Example 13 includes the apparatus of any one of examples 8 to 12, wherein n-1 or n-2.

Example 14 includes a computer-readable medium having instructions stored thereon, which when executed by a processor circuit, causes the processor circuit to: generating a first index a based on a number n of additional slots following a first slot, a number S of available subchannels in each of the additional slots, and a number m of allocated subchannels in each of the additional slots, wherein the first slot and the additional slots are for carrying a same Transport Block (TB); based on the number n of additional slots, the number S of available subchannels in each of the additional slots, the number m of allocated subchannels in each of the additional slots, and a pinAn index k to a starting subchannel of each of the additional slots_jGenerating a second index b; generating a third index I based on a sum of the first index a and the second index b, wherein the third index I is used to inform the number m of allocated subchannels in each of the additional slots and an index k of a starting subchannel for each of the additional slots_jBoth of them; and encoding the third index I in a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) for transmission to a receiving User Equipment (UE), wherein n is 1 or n is 2.

Example 15 includes the computer-readable medium of example 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: encoding the number n of additional slots in a first time resource signaling for transmission to the receiver UE.

Example 16 includes the computer-readable medium of example 15, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: encoding an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the receiver UE.

Example 17 includes the computer-readable medium of example 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: encoding a single index for transmission to the recipient UE, the single index for informing both the number n of additional slots and the offset of the additional slots relative to the first slot.

Example 18 includes the computer-readable medium of example 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to generate the first index a based on the following equation:

example 19 includes the computer-readable medium of example 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to generate the second index b based on the following equation:

example 20 includes a computer-readable medium having instructions stored thereon, which when executed by a processor circuit, causes the processor circuit to: decoding a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) received from a transmitting User Equipment (UE) to obtain a single index I; decoding the time resource signaling received from the sender UE to obtain a number n of additional time slots after the first time slot; obtaining a number S of available subchannels in each of the additional time-slots according to a resource pool configuration; and determining the number of allocated subchannels m in each of the additional slots and the index k of the starting subchannel for each of the additional slots based on the index I, the number of additional slots n, and the number of available subchannels S in each of the additional slots_jWherein n-1 or n-2.

Example 21 includes the computer-readable medium of example 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: based on the formula

Example 22 includes the computer-readable medium of example 21, wherein the instructions are inThe processor circuit, when executed, further causes the processor circuit to: based on I minus a_mTo determine a second sub-index b; and based on a formula

Example 23 includes the computer-readable medium of example 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: decoding the time resource signaling to obtain an offset of the additional slot relative to the first slot.

Example 24 includes the computer-readable medium of example 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: decoding additional time resource signaling to obtain an offset of the additional slot relative to the first slot.

Example 25 includes an apparatus for a User Equipment (UE), the apparatus comprising: means for generating a first index a based on a number n of additional slots following a first slot, a number S of available subchannels in each of the additional slots, and a number m of allocated subchannels in each of the additional slots, wherein the first slot and the additional slots are for carrying a same Transport Block (TB); for determining a number of additional time slots based on the number of additional time slots n, the number of available subchannels in each of the additional time slots S, the number of assigned subchannels in each of the additional time slots m, and an index of a starting subchannel for each of the additional time slots k_jMeans for generating a second index b; means for generating a third index I based on a sum of the first index a and the second index b, wherein the third index I is used to inform the number m of allocated subchannels in each of the additional slots and an index k of a starting subchannel for each of the additional slots_jBoth of them; and use ofMeans for encoding the third index I in a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) for transmission to a recipient UE.

Example 26 includes the apparatus of example 25, further comprising: means for encoding the number n of additional slots in a first time resource signaling for transmission to the recipient UE.

Example 27 includes the apparatus of example 26, further comprising: means for encoding an offset of the additional time slot relative to the first time slot in second time resource signaling for transmission to the recipient UE.

Example 28 includes the apparatus of example 25, further comprising: means for encoding a single index for transmission to the recipient UE, the single index for informing both the number n of additional slots and the offset of the additional slots relative to the first slot.

Example 29 includes the apparatus of example 25, further comprising means for generating the first index a based on the following equation:

example 30 includes the apparatus of example 25, further comprising means for generating the second index b based on the following formula:

example 31 includes the apparatus of any one of examples 25 to 30, wherein n-1 or n-2.

Example 32 includes an apparatus for a User Equipment (UE), the apparatus comprising: means for decoding a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) received from a sender UE to obtain a single index I; means for decoding time resource signaling received from the sender UE to obtain a number n of additional slots after a first slotPlacing; means for obtaining a number S of available subchannels in each of the additional time-slots according to a resource pool configuration; and means for determining the number of allocated subchannels in each of the additional slots m and the index k of the starting subchannel for each of the additional slots based on the index I, the number of additional slots n, and the number of available subchannels in each of the additional slots S_jThe apparatus of (1).

Example 33 includes the apparatus of example 32, further comprising: for basing on formulas

To determine a first sub-index a_mThe apparatus of (1); and for basing on formula a_m≤I<a_m+1Means for determining the number m of assigned subchannels in each of said additional time-slots, wherein a₁＝0,a_S+1＝∞。

Example 34 includes the apparatus of example 33, further comprising: for subtracting a from I_mMeans for determining a second sub-index b; and for basing on formulas

To determine an index k of a starting sub-channel for each of the additional slots_jThe apparatus of (1).

Example 35 includes the apparatus of example 32, further comprising: means for decoding the time resource signaling to obtain an offset of the additional slot relative to the first slot.

Example 36 includes the apparatus of example 32, further comprising: means for decoding additional time resource signaling to obtain an offset of the additional slot relative to the first slot.

Example 37 includes the apparatus of any one of examples 32 to 36, wherein n-1 or n-2.

Example 38 includes a method for a User Equipment (UE), the method comprising: generating a first index a based on a number n of additional slots following a first slot, a number S of available subchannels in each of the additional slots, and a number m of allocated subchannels in each of the additional slots, wherein the first slot and the additional slots are for carrying a same Transport Block (TB); based on the number n of additional slots, the number S of available subchannels in each of the additional slots, the number m of allocated subchannels in each of the additional slots, and an index k of a starting subchannel for each of the additional slots_jGenerating a second index b; generating a third index I based on a sum of the first index a and the second index b, wherein the third index I is used to inform the number m of allocated subchannels in each of the additional slots and an index k of a starting subchannel for each of the additional slots_jBoth of them; and encoding the third index I in Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) for transmission to a recipient UE.

Example 39 includes the method of example 38, further comprising: encoding the number n of additional slots in a first time resource signaling for transmission to the receiver UE.

Example 40 includes the method of example 39, further comprising: encoding an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the receiver UE.

Example 41 includes the method of example 38, further comprising: encoding a single index for transmission to the recipient UE, the single index for informing both the number n of additional slots and the offset of the additional slots relative to the first slot.

Example 42 includes the method of example 38, further comprising generating the first index a based on the following formula:

example 43 includes the method of example 38, further comprising generating the second index b based on the following formula:

example 44 includes the method of any one of examples 38 to 43, wherein n-1 or n-2.

Example 45 includes a method for a User Equipment (UE), the method comprising: decoding a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) received from a sender UE to obtain a single index I; decoding the time resource signaling received from the sender UE to obtain a number n of additional time slots after the first time slot; obtaining a number S of available subchannels in each of the additional time-slots according to a resource pool configuration; and determining the number of allocated subchannels m in each of the additional slots and the index k of the starting subchannel for each of the additional slots based on the index I, the number of additional slots n, and the number of available subchannels S in each of the additional slots_j。

Example 46 includes the method of example 45, further comprising: based on the formula

To determine a first sub-index a_m(ii) a And based on formula a_m≤I<a_m+1To determine the allocated in each of the additional time slotsNumber m of sub-channels, where a₁＝0,a_S+1＝∞。

Example 47 includes the method of example 46, further comprising: based on I minus a_mTo determine a second sub-index b; and based on a formula

Example 48 includes the method of example 45, further comprising: decoding the time resource signaling to obtain an offset of the additional slot relative to the first slot.

Example 49 includes the method of example 45, further comprising: decoding additional time resource signaling to obtain an offset of the additional slot relative to the first slot.

Example 50 includes the method of any one of examples 45 to 49, wherein n-1 or n-2.

Example 51 includes a User Equipment (UE) as described and illustrated in the specification.

Example 52 includes a method performed at a User Equipment (UE) as described and illustrated in the specification.

Although certain embodiments have been illustrated and described herein for purposes of description, various alternative and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that the embodiments described herein be limited only by the claims and the equivalents thereof.

Claims

1. An apparatus for a User Equipment (UE), the apparatus comprising:

a Radio Frequency (RF) interface; and

a processor circuit coupled with the RF interface,

wherein the processor circuit is to:

generating a first index a based on a number n of additional slots following a first slot, a number S of available subchannels in each of the additional slots, and a number m of allocated subchannels in each of the additional slots, wherein the first slot and the additional slots are for carrying a same Transport Block (TB);

based on the number n of additional slots, the number S of available subchannels in each of the additional slots, the number m of allocated subchannels in each of the additional slots, and an index k of a starting subchannel for each of the additional slots_jGenerating a second index b, wherein j ∈ {0, …, n-1 };

generating a third index I based on a sum of the first index a and the second index b, wherein the third index I is used to inform the number m of allocated subchannels in each of the additional slots and an index k of a starting subchannel for each of the additional slots_jBoth of them; and

the third index I is encoded in a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) for transmission to a recipient UE via the RF interface.

2. The apparatus of claim 1, wherein the processor circuit is to: encoding the number n of additional time slots in a first time resource signaling for transmission to the recipient UE via the RF interface.

3. The apparatus of claim 2, wherein the processor circuit is to: encoding an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the recipient UE via the RF interface.

4. The apparatus of claim 1, wherein the processor circuit is to: encoding a single index for transmission to the recipient UE, the single index for informing both the number n of additional slots and the offset of the additional slots relative to the first slot.

5. The apparatus of claim 1, wherein the processor circuit is to generate the first index a based on the following equation:

6. the apparatus of claim 1, wherein the processor circuit is to generate the second index b based on the following equation:

7. the apparatus of any one of claims 1-6, wherein n-1 or n-2.

8. An apparatus for a User Equipment (UE), the apparatus comprising:

a Radio Frequency (RF) interface; and

a processor circuit coupled with the RF interface,

wherein the processor circuit is to:

decoding a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) received from a sender UE via the RF interface to obtain a single index I;

decoding time resource signaling received from the sender UE via the RF interface to obtain a number n of additional time slots after a first time slot;

obtaining a number S of available subchannels in each of the additional time-slots according to a resource pool configuration; and

determining the number of allocated subchannels m in each of the additional slots and an index k of a starting subchannel for each of the additional slots based on the index I, the number of additional slots n, and the number of available subchannels S in each of the additional slots_jWhere j ∈ {0, …, n-1 }.

9. The apparatus of claim 8, wherein the processor circuit is to:

based on the formula

To determine a first sub-index a_m(ii) a And

based on the formula a_m≤I<a_m+1Determining the number m of allocated subchannels in each of said additional time-slots, wherein a₁＝0,a_S+1＝∞。

10. The apparatus of claim 9, wherein the processor circuit is to:

based on I minus a_mTo determine a second sub-index b; and

based on the formula

11. The apparatus of claim 8, wherein the processor circuit is to: decoding the time resource signaling to obtain an offset of the additional slot relative to the first slot.

12. The apparatus of claim 8, wherein the processor circuit is to: decoding additional time resource signaling to obtain an offset of the additional slot relative to the first slot.

13. The apparatus of any one of claims 8-12, wherein n-1 or n-2.

14. A computer readable medium having stored thereon instructions that, when executed by a processor circuit, cause the processor circuit to:

encoding the third index I in Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) for transmission to a recipient User Equipment (UE),

wherein n-1 or n-2.

15. The computer readable medium of claim 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: encoding the number n of additional slots in a first time resource signaling for transmission to the receiver UE.

16. The computer readable medium of claim 15, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: encoding an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the receiver UE.

17. The computer readable medium of claim 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: encoding a single index for transmission to the recipient UE, the single index for informing both the number n of additional slots and the offset of the additional slots relative to the first slot.

18. The computer-readable medium of claim 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to generate the first index a based on the following equation:

19. the computer-readable medium of claim 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to generate the second index b based on the formula:

20. a computer readable medium having stored thereon instructions that, when executed by a processor circuit, cause the processor circuit to:

decoding a Sidelink Control Information (SCI) of a Physical Sidelink Control Channel (PSCCH) received from a transmitting User Equipment (UE) to obtain a single index I;

decoding the time resource signaling received from the sender UE to obtain a number n of additional time slots after the first time slot;

determining the number of allocated subchannels m in each of the additional slots and an index k of a starting subchannel for each of the additional slots based on the index I, the number of additional slots n, and the number of available subchannels S in each of the additional slots_jWhere j ∈ {0, …, n-1},

wherein n-1 or n-2.

21. The computer readable medium of claim 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to:

based on the formula

To determine a first sub-index a_m(ii) a And

22. The computer readable medium of claim 21, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to:

based on I minus a_mTo determine a second sub-index b; and

based on the formula

23. The computer readable medium of claim 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: decoding the time resource signaling to obtain an offset of the additional slot relative to the first slot.

24. The computer readable medium of claim 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: decoding additional time resource signaling to obtain an offset of the additional slot relative to the first slot.