CN112825332A - LDMOS device and manufacturing method thereof - Google Patents

LDMOS device and manufacturing method thereof Download PDF

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Publication number
CN112825332A
CN112825332A CN201911148164.8A CN201911148164A CN112825332A CN 112825332 A CN112825332 A CN 112825332A CN 201911148164 A CN201911148164 A CN 201911148164A CN 112825332 A CN112825332 A CN 112825332A
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region
drift region
contact hole
channel
drift
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CN112825332B (en
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曾大杰
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Nantong Shangyangtong Integrated Circuit Co ltd
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Nantong Shangyangtong Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention discloses an LDMOS device, which comprises: a channel region and a drift region in lateral contact, a source region formed at a surface of the channel region and self-aligned to the first side of the gate structure. The drift region is directly connected to the drain electrode composed of the front metal layer through the drift region lead-out region and the second contact hole, so that a leakage-free region structure is formed, and the length of the drift region is directly determined by the distance between the first side face of the drift region and the second contact hole due to the leakage-free region structure. The invention also discloses a manufacturing method of the LDMOS device. The invention can reduce the length of the drift region, thereby reducing the output capacitance of the device and reducing the loss of the device in the switching process.

Description

LDMOS device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an LDMOS device. The invention also relates to a manufacturing method of the LDMOS device.
Background
LDMOS devices have high breakdown voltage and low capacitance, here mainly input capacitance (Ciss), and are widely used in BCD processes to implement high voltage or rf power amplifiers.
For an LDMOS device with excellent performance, it is desirable that the input capacitance (capacitance) is low and the output capacitance (Coss) is low. As shown in fig. 1, it is a cross-sectional structure diagram of a conventional LDMOS device; taking an N-type device as an example, the conventional LDMOS device includes:
a P-doped channel region 2 and an N-doped drift region 3 formed on a semiconductor substrate 1, a first side of said drift region 3 being in lateral contact with said channel region 2.
The gate structure covers the surface of the channel region 2 and extends to the drift region 3; the surface of the channel region 2 covered by the gate structure is used to form a channel.
The grid structure comprises a grid dielectric layer 6 and a grid conducting material layer 4 which are sequentially overlapped.
An N-type heavily doped source region 5a is formed at the surface of the channel region 2 and is self-aligned with the first side of the gate structure.
An N-type heavily doped drain region 5b is formed on the surface of the drift region 3 and spaced from the second side of the gate structure.
The top of the source region 5a is connected to a source electrode composed of a front metal layer through a first contact hole 8.
The top of the drain region 5b is connected to a drain electrode composed of a front metal layer through a second contact hole 7.
Usually, an epitaxial layer is formed on the surface of the semiconductor substrate 1, and the resistivity of the epitaxial layer is related to the breakdown voltage required to be endured by the LDMOS device. The higher the breakdown voltage required for an LDMOS device, the higher the resistivity, and the thicker the epitaxial layer.
The channel region extension region 9 can be implemented by performing photolithography definition and ion implantation separately, or can be implanted after opening the corresponding first contact hole 8 so as to be formed only at the bottom of the corresponding first contact hole 8. For an N-type device, the ion implantation impurity of the channel region extraction region 9 is BF2, the implantation energy is 40keV, and the implantation dosage is up to 1e15cm-2. This makes the B ion concentration on the surface of the corresponding first contact hole 8 high, which increases the doping concentration of the contact interface of the corresponding first contact hole 8 and the channel region 2, thereby achieving a good ohmic contact. In addition, the dosage of the ion-doped implantation of the source region 5a is about 5e15cm-2Therefore, even if the ion implantation of the channel region extraction region 9 is performed on the surface of the source region 5a corresponding to the bottom of the first contact hole 8, the doping concentration of the source region 5a is still high even through inversion, so that the source region 5a can still realize good ohmic contact with the first contact hole 8.
Note that in the prior art, the drain region 5b is necessarily required for the LDMOS device, otherwise the second contact hole 7 would be directly connected to the drift region 3, and because of the low doping concentration of the drift region 3, the contact formed between the second contact hole 7 and the drift region 3 is a schottky contact rather than an ohmic contact. The on-resistance of the LDMOS device can thus become large.
However, because of the presence of the drain region 5b, the length of the entire drift region 3 is increased, as will be explained below:
as shown in fig. 1, the length L3 of the drain region 5b is typically between 0.15 μm and 0.3 μm. For high voltage LDMOS devices, such as devices with a breakdown voltage exceeding 100V, the length L1 of the drift region 3 is typically above 5 μm, which is not so important for the distance L3, and L2 is the difference between L1 and L3, corresponding to the length of the drift region 3 after subtracting the drain region 5 b.
However, for the radio frequency power device, the breakdown voltage is usually 65V, and the length of the drift region 3 is usually only 2.6 μm; or some lower voltage LDMOS devices, such as 30V breakdown devices, drift, 3 is typically only 1.0 μm in length, and this increased distance L2 becomes especially important. The increase of the distance mainly increases the output capacitance of the LDMOS device, thereby increasing the loss of the LDMOS device during the switching process.
Disclosure of Invention
The invention aims to provide an LDMOS device, which can reduce the length of a drift region, thereby reducing the output capacitance of the device and reducing the loss of the device in the switching process. Therefore, the invention also provides a manufacturing method of the LDMOS device.
In order to solve the above technical problem, the LDMOS device provided by the present invention includes:
a second-conductivity-type-doped channel region and a first-conductivity-type-doped drift region formed on the semiconductor substrate, a first side of the drift region being in lateral contact with the channel region.
The gate structure covers the surface of the channel region and extends to the drift region; the surface of the channel region covered by the gate structure is used to form a channel.
The grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped.
A source region of heavily doped first conductivity type is formed at a surface of the channel region and is self-aligned with the first side of the gate structure.
The top of the source region is connected to a source electrode composed of a front metal layer through a first contact hole.
A second contact hole is formed at the top of the drift region, the second contact hole being laterally spaced from the second side of the gate structure.
A drift region leading-out region formed by first conductive type heavily doped ion implantation is formed at the bottom of the second contact hole in a self-alignment mode, the drift region leading-out region and the second contact hole form ohmic contact, the drift region is directly connected to a drain electrode consisting of a front metal layer through the drift region leading-out region and the second contact hole, and therefore a non-drain region structure is formed, the length of the drift region is directly determined by the distance between the first side face of the drift region and the second contact hole due to the non-drain region structure, the influence of the drain region on the length of the drift region is eliminated, the length of the drift region is reduced, and the output capacitance of the device is reduced.
The length direction of the channel is the direction from the source region to the drift region; the width direction of the channel is a direction perpendicular to the length direction of the channel.
The gate structure, the source region, the channel region and the drift region extend continuously in a width direction along the channel, the first contact hole includes one or more and is selectively disposed in the source region, and the second contact hole includes one or more and is selectively disposed in the drift region.
The further improvement is that a channel region leading-out region formed by second conductive type heavily doped ion implantation is formed on the surface of the channel region, and the top of the channel region leading-out region is connected with the source electrode through a corresponding first contact hole.
The further improvement is that the first conductive type heavily doped ion implantation impurities of the drift region lead-out region are also implanted into the bottom of the corresponding first contact hole, the implantation dosage of the first conductive type heavily doped ion implantation of the drift region lead-out region is less than that of the second conductive type heavily doped ion implantation of the channel region lead-out region, the surface of the channel region lead-out region still keeps the second conductive type heavily doped, and the channel region lead-out region and the first contact hole corresponding to the top can form ohmic contact.
In a further improvement, a first injection region is further formed in the drift region, the first injection region is lightly doped with the first conductivity type, the first injection region is overlapped in the drift region near one side of the second contact hole, the junction depth of the first injection region is greater than or equal to the junction depth of the drift region, the second contact hole is located at the top of the first injection region, and the overlapped region of the first injection region and the drift region has a concentration gradient structure in which the doping concentration is gradually reduced in the direction from the second contact hole to the first side surface of the drift region.
In a further improvement, more than one field plate is formed on the top of the drift region, and the field plate is connected to the source electrode; the field plate is a metal field plate or a polysilicon field plate.
In a further refinement, a field oxide is formed in the drift region proximate the first side of the drift region, the gate structure also extending over the field oxide.
The further improvement is that the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities of the first conduction type heavily doped ions in the drift region lead-out region are phosphorus or arsenic, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2(ii) a Or, the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities implanted by the first conduction type heavily doped ions in the drift region lead-out region comprise boron, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2。
In order to solve the above technical problem, the method for manufacturing the LDMOS device provided by the present invention includes the following steps:
step one, providing a semiconductor substrate, and completing the process of forming a channel region doped with a second conduction type, a drift region doped with a first conduction type and a grid structure on the semiconductor substrate.
The first side of the drift region and the channel region are in lateral contact.
The gate structure covers the surface of the channel region and extends to the drift region; the surface of the channel region covered by the gate structure is used to form a channel.
The grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped.
And secondly, performing first conductive type heavily doped ion implantation on the surface of the channel region to form a source region by taking the first side surface of the gate structure as a self-alignment condition, and canceling a drain region forming process while forming the source region.
Step three, forming an interlayer film; etching to form an opening of the contact hole penetrating through the interlayer film, and filling a metal layer in the opening of the contact hole to form the contact hole; and forming a front metal layer and patterning the front metal layer to form a source electrode, a drain electrode and a grid electrode.
The top of the source region is connected to the source electrode through a first contact hole.
A second contact hole is formed at the top of the drift region, the second contact hole being laterally spaced from the second side of the gate structure.
After the opening of the contact hole is opened and before metal filling, a step of performing first conduction type heavy doping ion implantation to form a drift region leading-out region on the surface of the drift region at the bottom of the second contact hole is further included, the drift region leading-out region and the second contact hole form ohmic contact, the drift region is directly connected to a drain electrode formed by a front metal layer through the drift region leading-out region and the second contact hole, so that a leakage-free region structure is formed, the length of the drift region is directly determined by the distance between the first side surface of the drift region and the second contact hole through the leakage-free region structure, the influence of a drain region on the length of the drift region is eliminated, the length of the drift region is reduced, and the output capacitance of the device is reduced.
The length direction of the channel is the direction from the source region to the drift region; the width direction of the channel is a direction perpendicular to the length direction of the channel.
The gate structure, the source region, the channel region and the drift region extend continuously in a width direction along the channel, the first contact hole includes one or more and is selectively disposed in the source region, and the second contact hole includes one or more and is selectively disposed in the drift region.
In a further improvement, before forming the interlayer film, a step of performing second conductivity type heavily doped ion implantation on a channel region lead-out region formed on the surface of the channel region is further included, and in the step three, the corresponding first contact holes are also formed in the channel region lead-out region and connected with the source electrode through the corresponding first contact holes.
The further improvement is that the first conductive type heavily doped ion implantation impurities of the drift region lead-out region are also implanted into the bottom of the corresponding first contact hole, the implantation dosage of the first conductive type heavily doped ion implantation of the drift region lead-out region is less than that of the second conductive type heavily doped ion implantation of the channel region lead-out region, the surface of the channel region lead-out region still keeps the second conductive type heavily doped, and the channel region lead-out region and the first contact hole corresponding to the top can form ohmic contact.
In a further improvement, before forming the interlayer film, the method further includes a step of forming a first injection region in the drift region, the first injection region is lightly doped with the first conductivity type, the first injection region is overlapped in the drift region on a side close to the second contact hole, a junction depth of the first injection region is greater than or equal to a junction depth of the drift region, the second contact hole is located at a top of the first injection region, and an overlapped region of the first injection region and the drift region has a concentration gradient structure in which a doping concentration is gradually reduced in a direction from the second contact hole to the first side of the drift region.
In a further improvement, more than one field plate is formed on the top of the drift region, and the field plate is connected to the source electrode; the field plate is a metal field plate or a polysilicon field plate.
In a further refinement, field oxygen is formed in the drift region proximate the first side of the drift region, the gate structure also extending over the field oxygen.
In a further improvement, the semiconductor substrate is a silicon substrate.
The gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process.
The grid conductive material layer is a polysilicon grid.
The further improvement is that the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities of the first conduction type heavily doped ions in the drift region lead-out region are phosphorus or arsenic, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2(ii) a Or, the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities implanted by the first conduction type heavily doped ions in the drift region lead-out region comprise boron, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2。
The drain region is cancelled in the drift region of the LDMOS device, the drift region is led out to the drain electrode consisting of the front metal layer directly through the contact hole with the drift region lead-out region at the bottom, namely the second contact hole, the drift region lead-out region and the second contact hole form ohmic contact, and compared with the situation that the LDMOS device in the prior art occupies a certain drift region width, the length of the drift region can be reduced under the condition that the voltage endurance capacity of the device is kept, so that the output capacitance of the device can be reduced, and the loss of the device in the switching process can be reduced.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a cross-sectional structural diagram of a conventional LDMOS device;
FIG. 2 is a cross-sectional view of an LDMOS device according to a first embodiment of the present invention;
FIG. 3 is a cross-sectional view of a second exemplary LDMOS device of the present invention;
FIG. 4 is a cross-sectional view of a third exemplary LDMOS device of the present invention;
FIG. 5 is a cross-sectional view of an LDMOS device according to a fourth embodiment of the present invention;
fig. 6 is a cross-sectional structural view of an LDMOS device according to a fifth embodiment of the present invention.
Detailed Description
FIG. 2 is a cross-sectional view of an LDMOS device according to a first embodiment of the present invention; the LDMOS device of the first embodiment of the present invention includes:
a second conductivity type doped channel region 2 and a first conductivity type doped drift region 3 formed on a semiconductor substrate 1, a first side of said drift region 3 being in lateral contact with said channel region 2.
The gate structure covers the surface of the channel region 2 and extends to the drift region 3; the surface of the channel region 2 covered by the gate structure is used to form a channel.
The grid structure comprises a grid dielectric layer 6 and a grid conducting material layer 4 which are sequentially overlapped.
A source region 5a of heavily doped first conductivity type is formed at the surface of the channel region 2 and is self-aligned with the first side of the gate structure.
The top of the source region 5a is connected to a source electrode composed of a front metal layer through a first contact hole 8.
The top of the gate conductive material layer 4 of the gate structure is also formed with a corresponding contact hole and connected to a gate composed of a front metal layer through the top corresponding contact hole.
A second contact hole 7 is formed at the top of the drift region 3, the second contact hole 7 being laterally spaced from a second side of the gate structure.
A drift region leading-out region formed by first conductive type heavily doped ion implantation is formed at the bottom of the second contact hole 7 in a self-alignment manner, the drift region leading-out region and the second contact hole 7 form ohmic contact, the drift region 3 is directly connected to a drain electrode consisting of a front metal layer through the drift region leading-out region and the second contact hole 7, so that a non-drain region structure is formed, the non-drain region structure enables the effective length of the drift region 3 to be directly determined by the distance between the first side surface of the drift region 3 and the second contact hole 7, the influence of a drain region on the effective length of the drift region 3 is eliminated, the effective length of the drift region 3 is reduced, and the output capacitance of the device is reduced.
The length direction of the channel is the direction from the source region 5a to the drift region 3; the width direction of the channel is a direction perpendicular to the length direction of the channel.
The gate structure, the source region 5a, the channel region 2, and the drift region 3 all extend continuously in a width direction (not shown) of the channel, the first contact hole 8 includes one or more and is selectively disposed in the source region 5a, and the second contact hole 7 includes one or more and is selectively disposed in the drift region 3.
A channel region lead-out region 9 formed by second conductive type heavily doped ion implantation is further formed on the surface of the channel region 2, and the top of the channel region lead-out region 9 is connected with the source electrode through a corresponding first contact hole 8.
The first conductive type heavily doped ion implantation impurities of the drift region lead-out region are also implanted into the bottom of the corresponding first contact hole 8, the implantation dosage of the first conductive type heavily doped ion implantation of the drift region lead-out region is smaller than that of the second conductive type heavily doped ion implantation of the channel region lead-out region 9, the surface of the channel region lead-out region 9 still keeps the second conductive type heavily doped, and the channel region lead-out region 9 and the first contact hole 8 corresponding to the top can form ohmic contact.
In the first embodiment of the present invention, the LDMOS device is an N-type device, the first conductivity type is an N-type, and the second conductivity type is an N-typeThe electric type is P type, the implanted impurity of the first conductive type heavily doped ion implantation of the drift region lead-out region is phosphorus or arsenic, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2. In other embodiments can also be: the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities implanted by first conduction type heavily doped ions in the drift region lead-out region comprise boron, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2。
The semiconductor substrate 1 is a silicon substrate. The gate dielectric layer 6 is a gate oxide layer and is formed by adopting a thermal oxidation process. The gate conductive material layer 4 is a polysilicon gate.
Usually, an epitaxial layer is formed on the surface of the semiconductor substrate 1, and the resistivity of the epitaxial layer is related to the breakdown voltage required to be endured by the LDMOS device. The higher the breakdown voltage required for an LDMOS device, the higher the resistivity, and the thicker the epitaxial layer.
The channel region extension region 9 can be implemented by performing photolithography definition and ion implantation separately, or can be implanted after opening the corresponding first contact hole 8 so as to be formed only at the bottom of the corresponding first contact hole 8. For an N-type device, the ion implantation impurity of the channel region extraction region 9 is BF2, the implantation energy is 40keV, and the implantation dosage is up to 1e15cm-2. This makes the B ion concentration on the surface of the corresponding first contact hole 8 high, which increases the doping concentration of the contact interface of the corresponding first contact hole 8 and the channel region 2, thereby achieving a good ohmic contact. In addition, the dosage of the ion-doped implantation of the source region 5a is about 5e15cm-2Therefore, even if the ion implantation of the channel region extraction region 9 is performed on the surface of the source region 5a corresponding to the bottom of the first contact hole 8, the doping concentration of the source region 5a is still high even through inversion, so that the source region 5a can still realize good ohmic contact with the first contact hole 8.
The length of the drift region 3 is different according to the withstand voltage requirement of the LDMOS device, for example:
for such LDMOS devices for high voltage applications with a breakdown voltage exceeding 100V, the length of the drift region 3 is typically above 5 μm
For the LDMOS device as a radio frequency power device, the breakdown voltage is typically 65V. The length of the drift region 3 is typically only 2.6 μm.
For some lower voltage LDMOS devices, such as 30V breakdown devices, the length of the drift region 3 is typically only 1.0 μm.
In the first embodiment of the invention, the drain region is cancelled in the drift region 3 of the LDMOS device, the drift region 3 is led out to the drain electrode consisting of the front metal layer directly through the contact hole with the drift region lead-out region at the bottom, namely the second contact hole 7, and the drift region lead-out region and the second contact hole 7 form ohmic contact.
Second embodiment LDMOS device of the present invention:
the LDMOS device of the second embodiment of the present invention is different from the LDMOS device of the first embodiment of the present invention in that the LDMOS device of the second embodiment of the present invention has the following features:
FIG. 3 is a cross-sectional view of an LDMOS device according to a second embodiment of the present invention; a first injection region 10 is further formed in the drift region 3, the first injection region 10 is lightly doped with the first conductivity type, the first injection region 10 is stacked in the drift region 3 near one side of the second contact hole 7, the junction depth of the first injection region 10 is greater than or equal to the junction depth of the drift region 3, the second contact hole 7 is located at the top of the first injection region 10, and the stacked region of the first injection region 10 and the drift region 3 has a concentration gradient structure with gradually decreasing doping concentration in the direction from the second contact hole 7 to the first side of the drift region 3, which is beneficial to improving the robustness of the device.
Third embodiment LDMOS device of the present invention:
the LDMOS device of the third embodiment of the present invention is different from the LDMOS device of the first embodiment of the present invention in that the LDMOS device of the third embodiment of the present invention has the following features:
FIG. 4 is a cross-sectional view of an LDMOS device according to a third embodiment of the present invention; a field plate 11 is formed on top of the drift region 3, the field plate 11 being connected to the source electrode.
The field plate 11 is a metal field plate or a polysilicon field plate. Polysilicon field plates typically employ heavily doped polysilicon. The metal field plate may be a material with low resistivity, such as a metal silicide.
The benefits of the field plate 11 are as follows:
it acts as a shield for the gate and drift regions 3, so that the gate-drain coupling capacitance (Cgd) can be greatly reduced, but it increases the gate-source coupling capacitance (Cgs), where Cgs is primarily the capacitance of the gate and the field plate 11. With the field plate 11, in the existing LDMOS device with a breakdown voltage of 65V, the Cgd under 28V can be 10fF per millimeter of gate width, that is, the total gate width is 1mm, and with the field plate 11, the Cgd under 28V can be 10 fF.
The field plate 11 also reduces the electric field strength at the gate and drift region 3. In addition, the field plate 11 on the drift region 3 can also be depleted with the drift region 3 in the longitudinal direction, so that the doping concentration of the drift region 3 can be increased, and the specific on-resistance can be reduced.
For these reasons, a field plate structure, i.e., a structure formed with the field plate 11, is the mainstream of the present LDMOS device, and fig. 4 adopts a single-layer field plate structure, i.e., a structure formed with only 1 layer of the field plate 11.
The fourth embodiment LDMOS device of the present invention:
the LDMOS device of the fourth embodiment of the present invention is different from the LDMOS device of the third embodiment of the present invention in that the LDMOS device of the fourth embodiment of the present invention has the following characteristics:
FIG. 5 is a cross-sectional view of an LDMOS device according to a third embodiment of the present invention; including a multi-layer field plate structure, a two-layer field plate structure is shown in fig. 5, where the first layer of field plates is indicated with reference 11, the first layer of field plates 11 being the same as the field plates 11 in fig. 4. The second layer field plate is indicated with reference 12. The multilayer field plate structure is widely applied to LDMOS devices with breakdown voltage exceeding 100V at present. Both field plates 11 and 12 are connected to the source electrode through corresponding contact or via holes.
The multilayer field plate structure can better optimize the electric field intensity distribution of the drift region 3, so that the doping concentration of the drift region 3 can be further improved under the condition of not reducing the breakdown voltage, and lower specific on-resistance can be obtained.
The LDMOS device of the fifth embodiment of the invention:
the LDMOS device of the fifth embodiment of the present invention is different from the LDMOS device of the first embodiment of the present invention in that the LDMOS device of the fifth embodiment of the present invention has the following features:
FIG. 6 is a cross-sectional view of an LDMOS device according to a fifth embodiment of the present invention; a field oxide 13 is formed in the drift region 3 near the first side of the drift region 3, the gate structure also extending over the field oxide 13. Shallow Trench Isolation (STI) processes are widely used in BCD processes to achieve isolation. In fig. 6, the field oxide 13 is formed by using an STI process, and the field oxide 13 is used to reduce the electric field strength at the boundary between the gate and the drift region, which is beneficial to improving the reliability of the device.
Various combinations of the embodiments of the present invention can also result in other various embodiments of device structures, which are not listed here.
The method for manufacturing the LDMOS device of the first embodiment of the invention comprises the following steps:
the method for manufacturing the LDMOS device of the first embodiment of the invention comprises the following steps:
step one, providing a semiconductor substrate 1, and completing the process of forming a channel region 2 doped with a second conduction type, a drift region 3 doped with a first conduction type and a gate structure on the semiconductor substrate 1.
A first side of the drift region 3 is laterally in contact with the channel region 2.
The gate structure covers the surface of the channel region 2 and extends to the drift region 3; the surface of the channel region 2 covered by the gate structure is used to form a channel.
The grid structure comprises a grid dielectric layer 6 and a grid conducting material layer 4 which are sequentially overlapped.
And secondly, performing first conductive type heavily doped ion implantation on the surface of the channel region 2 to form a source region 5a by taking the first side surface of the gate structure as a self-alignment condition, and canceling a drain region forming process while forming the source region 5 a.
Step three, forming an interlayer film; etching to form an opening of the contact hole penetrating through the interlayer film, and filling a metal layer in the opening of the contact hole to form the contact hole; and forming a front metal layer and patterning the front metal layer to form a source electrode, a drain electrode and a grid electrode.
The top of the source region 5a is connected to the source electrode through a first contact hole 8.
The top of the gate conductive material layer 4 of the gate structure is connected to the gate through a corresponding contact hole.
A second contact hole 7 is formed at the top of the drift region 3, the second contact hole 7 being laterally spaced from a second side of the gate structure.
After the opening of the contact hole is opened and before metal filling, a step of performing first conductivity type heavy doping ion implantation to form a drift region leading-out region on the surface of the drift region 3 at the bottom of the second contact hole 7, wherein the drift region leading-out region and the second contact hole 7 form ohmic contact, the drift region 3 is directly connected to a drain electrode composed of a front metal layer through the drift region leading-out region and the second contact hole 7, so that a no-drain region structure is formed, the no-drain region structure enables the effective length of the drift region 3 to be directly determined by the distance between the first side surface of the drift region 3 and the second contact hole 7, so that the influence of a drain region on the effective length of the drift region 3 is eliminated, the effective length of the drift region 3 is reduced, and the output capacitance of the device is reduced.
The length direction of the channel is the direction from the source region 5a to the drift region 3; the width direction of the channel is a direction perpendicular to the length direction of the channel.
The gate structure, the source region 5a, the channel region 2, and the drift region 3 all extend continuously in a width direction along the channel, the first contact hole 8 includes one or more and is selectively disposed in the source region 5a, and the second contact hole 7 includes one or more and is selectively disposed in the drift region 3.
In the method according to the first embodiment of the present invention, before the interlayer film is formed, a step of performing second conductivity type heavily doped ion implantation on a channel region extraction region 9 formed on the surface of the channel region 2 is further included, and in the step three, the corresponding first contact holes 8 are also formed in the channel region extraction region 9 and connected to the source through the corresponding first contact holes 8.
The first conductive type heavily doped ion implantation impurities of the drift region lead-out region are also implanted into the bottom of the corresponding first contact hole 8, the implantation dosage of the first conductive type heavily doped ion implantation of the drift region lead-out region is smaller than that of the second conductive type heavily doped ion implantation of the channel region lead-out region 9, the surface of the channel region lead-out region 9 still keeps the second conductive type heavily doped, and the channel region lead-out region 9 and the first contact hole 8 corresponding to the top can form ohmic contact.
In the method of the first embodiment of the present invention, the LDMOS device is an N-type device, the first conductivity type is an N-type device, the second conductivity type is a P-type device, the implanted impurity of the first conductivity type heavily doped ion implantation of the drift region lead-out region is phosphorus or arsenic, the implantation energy is 30keV to 100keV, and the implantation dose is 1e15cm-2～2e15cm-2. In other embodiments the method can also be: the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities implanted by first conduction type heavily doped ions in the drift region lead-out region comprise boron, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2。
The semiconductor substrate 1 is a silicon substrate. The gate dielectric layer 6 is a gate oxide layer and is formed by adopting a thermal oxidation process. The gate conductive material layer 4 is a polysilicon gate.
Usually, an epitaxial layer is formed on the surface of the semiconductor substrate 1, and the resistivity of the epitaxial layer is related to the breakdown voltage required to be endured by the LDMOS device. The higher the breakdown voltage required for an LDMOS device, the higher the resistivity, and the thicker the epitaxial layer.
The method of fabricating the LDMOS device of the first embodiment of the invention forms the device of the first embodiment of the invention shown in fig. 2.
The method for manufacturing the LDMOS device of the second embodiment of the invention comprises the following steps:
the difference between the method for manufacturing the LDMOS device of the second embodiment of the present invention and the method for manufacturing the LDMOS device of the first embodiment of the present invention is that the method for manufacturing the LDMOS device of the second embodiment of the present invention has the following characteristics:
before the interlayer film is formed, a step of forming a first injection region 10 in the drift region 3 is further included, the first injection region 10 is lightly doped with the first conductivity type, the first injection region 10 is overlapped in the drift region 3 on the side close to the second contact hole 7, the junction depth of the first injection region 10 is greater than or equal to the junction depth of the drift region 3, the second contact hole 7 is positioned on the top of the first injection region 10, and the overlapped region of the first injection region 10 and the drift region 3 has a concentration gradient structure in which the doping concentration is gradually reduced in the direction from the second contact hole 7 to the first side of the drift region 3. The method of fabricating the LDMOS device of the second embodiment of the invention forms the device of the second embodiment of the invention shown in fig. 3.
The method for manufacturing the LDMOS device of the third embodiment of the invention comprises the following steps:
the difference between the method for manufacturing the LDMOS device of the third embodiment of the present invention and the method for manufacturing the LDMOS device of the first embodiment of the present invention is that the method for manufacturing the LDMOS device of the third embodiment of the present invention has the following characteristics:
a field plate 11 is formed on the top of the drift region 3, and the field plate 11 is connected to the source electrode; the field plate 11 is a metal field plate 11 or a polysilicon field plate 11. The method of fabricating the LDMOS device of the third embodiment of the invention forms the device of the third embodiment of the invention shown in fig. 4.
The method for manufacturing the LDMOS device of the fourth embodiment of the invention comprises the following steps:
the difference between the method for manufacturing the LDMOS device of the fourth embodiment of the present invention and the method for manufacturing the LDMOS device of the third embodiment of the present invention is that the method for manufacturing the LDMOS device of the fourth embodiment of the present invention has the following characteristics:
forming more than 2 field plates 11 on top of the drift region 3, each of the field plates 11 being connected to the source electrode; the field plate 11 is a metal field plate 11 or a polysilicon field plate 11. The method of fabricating the LDMOS device of the fourth embodiment of the invention forms the device of the fourth embodiment of the invention shown in fig. 5.
The method for manufacturing the LDMOS device of the fifth embodiment of the invention comprises the following steps:
the difference between the method for manufacturing the LDMOS device of the fifth embodiment of the present invention and the method for manufacturing the LDMOS device of the first embodiment of the present invention is that the method for manufacturing the LDMOS device of the fifth embodiment of the present invention has the following characteristics:
a field oxide 13 is formed in the drift region 3 near a first side of the drift region 3, the gate structure also extending over the field oxide 13.
Typically, the field oxide 13 is formed using an STI process. The field oxide 13 can be formed before or after the formation of the drift region 3.
The method of fabricating the LDMOS device of the fifth embodiment of the invention forms the device of the fifth embodiment of the invention shown in fig. 6.
Various combinations of the methods of the embodiments of the present invention can also be used to obtain other embodiments of the present invention, which are not listed here.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. An LDMOS device, comprising:
a second-conductivity-type-doped channel region and a first-conductivity-type-doped drift region formed on a semiconductor substrate, a first side of the drift region laterally contacting the channel region;
the gate structure covers the surface of the channel region and extends to the drift region; the surface of the channel region covered by the gate structure is used for forming a channel;
the grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped;
a source region with heavily doped first conductivity type is formed on the surface of the channel region and is self-aligned with the first side surface of the gate structure;
the top of the source region is connected to a source electrode consisting of a front metal layer through a first contact hole;
a second contact hole is formed at the top of the drift region, the second contact hole being laterally spaced from the second side of the gate structure by a distance;
a drift region leading-out region formed by first conductive type heavily doped ion implantation is formed at the bottom of the second contact hole in a self-alignment mode, the drift region leading-out region and the second contact hole form ohmic contact, the drift region is directly connected to a drain electrode consisting of a front metal layer through the drift region leading-out region and the second contact hole, and therefore a non-drain region structure is formed, the length of the drift region is directly determined by the distance between the first side face of the drift region and the second contact hole due to the non-drain region structure, the influence of the drain region on the length of the drift region is eliminated, the length of the drift region is reduced, and the output capacitance of the device is reduced;
the length direction of the channel is the direction from the source region to the drift region; the width direction of the channel is perpendicular to the length direction of the channel;
the gate structure, the source region, the channel region and the drift region extend continuously in a width direction along the channel, the first contact hole includes one or more and is selectively disposed in the source region, and the second contact hole includes one or more and is selectively disposed in the drift region.
2. The LDMOS device of claim 1, wherein: and a channel region leading-out region formed by second conductive type heavily doped ion implantation is further formed on the surface of the channel region, and the top of the channel region leading-out region is connected with the source electrode through a corresponding first contact hole.
3. The LDMOS device of claim 2, wherein: and the implantation dosage of the first conductive type heavily doped ion implantation of the drift region lead-out region is less than that of the second conductive type heavily doped ion implantation of the channel region lead-out region, so that the surface of the channel region lead-out region still keeps the second conductive type heavily doped and the channel region lead-out region and the first contact hole corresponding to the top can form ohmic contact.
4. The LDMOS device of claim 1, wherein: a first injection region is further formed in the drift region, the first injection region is lightly doped with a first conductivity type, the first injection region is superposed in the drift region close to one side of the second contact hole, the junction depth of the first injection region is greater than or equal to the junction depth of the drift region, the second contact hole is positioned at the top of the first injection region, and the superposed region of the first injection region and the drift region has a concentration gradient structure with gradually reduced doping concentration in the direction from the second contact hole to the first side surface of the drift region.
5. The LDMOS device of claim 1, wherein: forming more than one field plate on the top of the drift region, wherein the field plate is connected to the source electrode; the field plate is a metal field plate or a polysilicon field plate.
6. The LDMOS device of claim 1, wherein: a field oxide is formed in the drift region proximate the first side of the drift region, the gate structure also extending over the field oxide.
7. The LDMOS device of any of claims 1-6, wherein: the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities implanted by first conduction type heavily doped ions in the drift region lead-out region are phosphorus or arsenic, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2(ii) a Or, the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities implanted by the first conduction type heavily doped ions in the drift region lead-out region comprise boron, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2。
8. A method for manufacturing an LDMOS device is characterized by comprising the following steps:
step one, providing a semiconductor substrate, and completing a process of forming a channel region doped with a second conduction type, a drift region doped with a first conduction type and a grid structure on the semiconductor substrate;
a first side of the drift region and the channel region are in lateral contact;
the gate structure covers the surface of the channel region and extends to the drift region; the surface of the channel region covered by the gate structure is used for forming a channel;
the grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped;
secondly, performing first conductive type heavily doped ion implantation on the surface of the channel region to form a source region by taking the first side surface of the grid structure as a self-alignment condition, and canceling a drain region forming process while forming the source region;
step three, forming an interlayer film; etching to form an opening of the contact hole penetrating through the interlayer film, and filling a metal layer in the opening of the contact hole to form the contact hole; forming a front metal layer and patterning the front metal layer to form a source electrode, a drain electrode and a grid electrode;
the top of the source region is connected to the source electrode through a first contact hole;
a second contact hole is formed at the top of the drift region, the second contact hole being laterally spaced from the second side of the gate structure by a distance;
after the opening of the contact hole is opened and before metal filling, a step of performing first conduction type heavy doping ion implantation to form a drift region leading-out region on the surface of the drift region at the bottom of the second contact hole, wherein the drift region leading-out region and the second contact hole form ohmic contact, the drift region is directly connected to a drain electrode consisting of a front metal layer through the drift region leading-out region and the second contact hole so as to form a leakage-free region structure, and the leakage-free region structure enables the length of the drift region to be directly determined by the distance between the first side surface of the drift region and the second contact hole so as to eliminate the influence of a drain region on the length of the drift region, reduce the length of the drift region and further reduce the output capacitance of the device;
the length direction of the channel is the direction from the source region to the drift region; the width direction of the channel is perpendicular to the length direction of the channel;
the gate structure, the source region, the channel region and the drift region extend continuously in a width direction along the channel, the first contact hole includes one or more and is selectively disposed in the source region, and the second contact hole includes one or more and is selectively disposed in the drift region.
9. The method of fabricating the LDMOS device of claim 8, wherein: and before the interlayer film is formed, a step of performing second conductive type heavily doped ion implantation on a channel region extraction region formed on the surface of the channel region is further included, and in the step three, the corresponding first contact holes are also formed in the channel region extraction region and are connected with the source electrode through the corresponding first contact holes.
10. The method of fabricating the LDMOS device of claim 9, wherein: and the implantation dosage of the first conductive type heavily doped ion implantation of the drift region lead-out region is less than that of the second conductive type heavily doped ion implantation of the channel region lead-out region, so that the surface of the channel region lead-out region still keeps the second conductive type heavily doped and the channel region lead-out region and the first contact hole corresponding to the top can form ohmic contact.
11. The method of fabricating the LDMOS device of claim 8, wherein: before the interlayer film is formed, a step of forming a first injection region in the drift region, wherein the first injection region is lightly doped with the first conductivity type, the first injection region is superposed in the drift region close to one side of the second contact hole, the junction depth of the first injection region is larger than or equal to that of the drift region, the second contact hole is positioned at the top of the first injection region, and the superposed region of the first injection region and the drift region has a concentration gradient structure with the doping concentration gradually reduced in the direction from the second contact hole to the first side surface of the drift region.
12. The method of fabricating the LDMOS device of claim 8, wherein: forming more than one field plate on the top of the drift region, wherein the field plate is connected to the source electrode; the field plate is a metal field plate or a polysilicon field plate.
13. The method of fabricating the LDMOS device of claim 8, wherein: forming field oxygen in the drift region proximate a first side of the drift region, the gate structure also extending over the field oxygen.
14. The method of fabricating the LDMOS device of claim 8, wherein: the semiconductor substrate is a silicon substrate;
the gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process;
the grid conductive material layer is a polysilicon grid.
15. A method of manufacturing an LDMOS device as claimed in any one of claims 8 to 14 wherein: the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities implanted by first conduction type heavily doped ions in the drift region lead-out region are phosphorus or arsenic, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2(ii) a Or, the LDMOS device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, implanted impurities implanted by the first conduction type heavily doped ions in the drift region lead-out region comprise boron, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm-2～2e15cm-2。
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