CN112825243A - Image display method and device, video processor and image display system - Google Patents
Image display method and device, video processor and image display system Download PDFInfo
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- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
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- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract
The embodiment of the invention discloses an image display method and device, a video processor and an image display system. The image display method includes: receiving and caching an input image frame to obtain a cached input image frame; acquiring the current position of a virtual boundary relative to the cached input image frame; obtaining pixel data of a first side of the current position of the virtual boundary in the cached input image frame to obtain a first image portion; acquiring pixel data of a second side, opposite to the first side, of the current position of the virtual boundary in the cached input image frame, and performing image processing to obtain a second image part; and outputting the first image part and the second image part to a target display screen for display. The embodiment of the invention effectively solves the problem that the contrast display can be realized only by more equipment.
Description
Technical Field
The present invention relates to the field of image display technologies, and in particular, to an image display method, an image display apparatus, a video processor, and an image display system.
Background
In the process of presenting a display effect of a High-quality image or a display effect of another image after image quality processing to a user, for example, an HDR (High-Dynamic Range image) image is presented to the user; due to the characteristics of human vision, the user can obviously feel that the display effect of the processed image is better than that of the image before processing only by comparing and displaying the image before processing and the image after processing at the same time for the effect.
However, in the existing methods for implementing the contrast display, a one-to-two processor is adopted to divide an input source into two paths of identical video sources and output the two paths of identical video sources to two video processors, wherein one video processor performs image quality improvement processing on one path of accessed video source and outputs the video source to one display screen, and the other video processor directly outputs the other path of accessed video source to another display screen arranged in parallel, so that a user can view display effects of images and unprocessed images which are respectively presented on the two display screens after the image quality improvement processing. Therefore, the existing method needs more hardware equipment to set up a system for image contrast display.
Disclosure of Invention
Therefore, embodiments of the present invention provide an image display method, an image display apparatus, a video processor, and an image display system, which effectively solve the problem that a large number of devices are required to implement contrast display.
In one aspect, an image display method provided in an embodiment of the present invention includes: receiving and caching an input image frame to obtain a cached input image frame; acquiring the current position of a virtual boundary relative to the cached input image frame; obtaining pixel data of a first side of the current position of the virtual boundary in the cached input image frame to obtain a first image portion; acquiring pixel data of a second side, opposite to the first side, of the current position of the virtual boundary in the cached input image frame, and performing image processing to obtain a second image part, wherein the second image part and the first image part belong to images of different types of dynamic ranges; and outputting the first image portion and the second image portion to a target display screen to display the first image portion and the second image portion in two different display areas of the target display screen, respectively.
In this embodiment, an input image frame of the same video source is buffered, a part of pixel data of the buffered input image frame is subjected to image processing for output, another part of pixel data of the buffered input image frame is directly output without image processing, and finally the first image part without image processing and the second image part after image processing are displayed in a contrast manner on a display screen.
In one embodiment of the present invention, the image display method further includes: performing frame counting on the buffered input image frames; moving a position of the virtual dividing line with respect to the input image frame as the frame count value changes to obtain the current position of the virtual dividing line.
In one embodiment of the present invention, the image display method further includes: restoring a position of the virtual dividing line with respect to the input image frame to an initial position to obtain the current position of the virtual dividing line in response to the position of the virtual dividing line exceeding a boundary pixel column of the input image frame in a direction in which the virtual dividing line moves.
In an embodiment of the present invention, the two display areas are two display areas of the target display screen that are parallel and connected; and the input image frame and the first image portion are of a standard dynamic range type.
In another aspect, an embodiment of the present invention provides an image display apparatus, including: the image frame caching module is used for receiving and caching the input image frame to obtain a cached input image frame; a boundary acquisition step for acquiring the current position of a virtual boundary relative to the cached input image frame; a first obtaining module, configured to obtain pixel data on a first side of the current position of the virtual boundary in the cached input image frame to obtain a first image portion; a second obtaining module, configured to obtain pixel data of a second side, opposite to the first side, of the current position of the virtual boundary in the cached input image frame, and perform image processing to obtain a second image portion, where the second image portion and the first image portion belong to images in different types of dynamic ranges; and an output display module for outputting the first image portion and the second image portion to a target display screen to display the first image portion and the second image portion in two different display areas of the target display screen, respectively.
In one embodiment of the present invention, the image display apparatus further includes: the frame counting module is used for counting the frames of the cached input image frames; a boundary moving module for moving a position of the virtual boundary with respect to the input image frame as the frame count value changes to obtain the current position of the virtual boundary.
In one embodiment of the present invention, the image display apparatus further includes: a dividing line resetting module, configured to restore a position of the virtual dividing line with respect to the input image frame to an initial position to obtain the current position of the virtual dividing line in response to the position of the virtual dividing line exceeding a boundary pixel column of the input image frame in a direction in which the virtual dividing line moves.
In an embodiment of the invention, the two display areas are two parallel display areas of the display screen and are connected with each other; and the input image frame and the first image portion are of a standard dynamic range type.
In another aspect, an embodiment of the present invention provides a video processor, including: a memory; a programmable logic device electrically connected to the memory for receiving an input image frame and buffering to the memory to obtain a buffered input image frame, obtaining a current position of a virtual dividing line with respect to the buffered input image frame, obtaining pixel data of a first side of the buffered input image frame located at the current position of the virtual dividing line to obtain a first image portion, obtaining pixel data of a second side of the buffered input image frame located at the current position of the virtual dividing line with respect to the first side and performing image processing to obtain a second image portion, and outputting the first image portion and the second image portion to a target display screen to display the first image portion and the second image portion in two different display areas of the display screen, respectively; wherein the second image portion and the first image portion belong to different types of dynamic range images.
In another aspect, an embodiment of the present invention provides an image display system, including: a video processor as described above; and the display screen is connected with the video processor and serves as the target display screen.
In summary, the above embodiments of the present application may have one or more of the following advantages or benefits: i) the method comprises the steps that image frames of the same input source are cached, one part of pixel data of the cached input image frames are subjected to image processing to be output, the other part of pixel data of the cached input image frames are directly output, and finally the first image part which is not subjected to image processing and the second image part which is subjected to image processing are displayed in a contrast mode on a display screen, and an image display system capable of performing contrast display can be built through a video processor and the display screen; ii) when the received and buffered input image frame is an image frame of a continuous video source, the position of the virtual dividing line associated with the buffered input image frame can be changed along with the change of the buffered input image frame, so that the size of the second image part and the size of the first image part are relatively changed, and the dynamic display of the second image part and the first image part on the display screen is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an image display system according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of the video processor in fig. 1.
Fig. 3 is a flowchart illustrating an image display method according to a first embodiment of the present invention.
Fig. 4A-4C are schematic structural diagrams of buffered input image frames, respectively.
Fig. 5 is a flowchart illustrating another image display method according to the first embodiment of the present invention.
Fig. 6A-6F are schematic diagrams illustrating a process in which the virtual boundary changes as the frame count increases.
Fig. 7 is a block diagram of an image display device according to a second embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a computer device according to a third embodiment of the present invention.
Fig. 9 is a schematic structural diagram of a storage medium according to a fourth embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
[ first embodiment ] A method for manufacturing a semiconductor device
Referring to fig. 1, which is a schematic structural diagram of an image display system according to a first embodiment of the present invention, the image display system 200 includes, for example, a video processor 210 and a display screen 220 connected to the video processor 210.
Referring to fig. 2, the video processor 210 includes, for example, a programmable logic device 211 and a memory 213 electrically connected to the programmable logic device 211; the Programmable logic device 211 may be an FPGA (Field Programmable Gate Array) device; the memory 213 may be a volatile memory such as a DDR (Double Data Rate) memory; the video processor 210 further includes, for example, a processor 212, the processor 212 is electrically connected to the programmable logic device 211 and the memory 213, and the processor 212 may include an ARM chip and may further include a microcontroller such as an MCU chip.
The display screen 220 is, for example, an LED display screen, and the LED display screen includes, for example, a plurality of receiving cards and a plurality of LED display light boxes respectively connected to the plurality of receiving cards; the display screen 220 may also be other displays, and is not limited herein.
In one embodiment, video processor 210 may be a transmitter card for controlling display screen 220.
Where video processor 210 is configured to perform the image display method shown in fig. 3 to enable display screen 220 to comparatively display a first image portion without image processing and a second image portion after image processing, for example, programmable logic device 211 in video processor 210 may perform the image display method. Specifically, the image display method includes, for example:
step S10, receiving and caching the input image frame to obtain the cached input image frame;
step S20, obtaining a current position of a virtual boundary relative to the buffered input image frame;
step S30, obtaining pixel data located on a first side of the current position of the virtual boundary in the buffered input image frame to obtain a first image portion;
step S50 of obtaining pixel data of a second side of the buffered input image frame, the second side being opposite to the first side and located at the current position of the virtual dividing line, and performing image processing to obtain a second image portion, wherein the second image portion and the first image portion belong to images of different types of dynamic ranges; and
step S70, outputting the first image portion and the second image portion to a target display screen to display the first image portion and the second image portion in two different display areas of the target display screen, respectively.
Wherein the input image frame may be an image frame having a first Dynamic Range, such as an SDR (Standard Dynamic Range) image, wherein the first Dynamic Range may include image information such as a luminance Range, a color gamut Range, etc.; the first image portion has the first Dynamic Range, and the second image portion has a second Dynamic Range, such as an HDR (High-Dynamic Range) image, which may also include image information such as a luminance Range, a color gamut Range, and the like; for example, the input image frame may be buffered in a volatile memory, such as a DDR memory, and the buffered input image frame may be obtained from the volatile memory.
The virtual boundary is used for dividing the buffered input image frame into a first side and a second side, and the virtual boundary does not exist in the buffered input image frame really; referring to fig. 4A-4C, the virtual boundary may be a location of a single pixel column or a location of a single pixel row of the associated buffered input image frame, for example, a virtual boundary may be located at a location of a 100 th column of pixels or a location of a 100 th row of pixels of the buffered input image frame, and the virtual boundary may also be a curved line or a closed shape such as an ellipse, a circle, a polygon, and the like.
Further, wherein the first side may be a left side of the virtual dividing line of the buffered input image frames and the second side may be a right side of the virtual dividing line of the buffered input image frames; further, when the virtual boundary is a single pixel column, the left and right different display regions of the display screen display the first image portion and the second image portion in parallel, where the left and right different display regions may be connected, and when the virtual boundary is a single pixel row, the upper and lower different display regions of the display screen display the first image portion and the second image portion in parallel, where the upper and lower different display regions may be connected.
Wherein the image processing may be performing image quality improvement processing on pixel data located on the second side of the virtual boundary in the buffered input image frame so that a display effect of the second image portion on the display screen 220 is better than a display effect of the first image portion on the display screen 220, and the image quality improvement processing may be dynamic range adjustment processing, such as adjusting an image of a Standard Dynamic Range (SDR) type to an image of a High Dynamic Range (HDR) type, the dynamic range adjustment including, for example, color gamut range adjustment for adjusting a low color gamut range to a high color gamut range, and the dynamic range adjustment may further include luminance range adjustment for adjusting a low luminance range to a high luminance range; the image processing may also be a scaling process for displaying the scaled second image portion and the non-scaled first image portion in comparison on the display screen 220.
Referring to fig. 5, in one embodiment, the image display method further includes, for example:
step S11, performing frame counting on the buffered input image frames;
a step S12 of moving the position of the virtual dividing line with respect to the input image frame with a change in the frame count value to obtain the current position of the virtual dividing line;
step S21, in response to the position of the virtual borderline exceeding the boundary pixel column of the input image frame in the direction in which the virtual borderline moves, restoring the position of the virtual borderline with respect to the input image frame to an initial position to obtain the current position of the virtual borderline.
The process can realize that the display screen 220 dynamically displays the second image portion and the first image portion, and when the video processor 210 receives continuous input image frames and continuously buffers the input image frames, a display area of the display screen 220 for displaying the first image portion and a display area of the display screen 220 for displaying the second image portion respectively dynamically change, for example, the display area of the display screen 220 for displaying the first image portion gradually increases, and the display area of the display screen 220 for displaying the second image portion correspondingly gradually decreases, so that the effect of contrast display is more obvious.
In one embodiment, the step 11 and the step 12 are performed after the step 10 is performed, and the step 20, the step S30, the step 50 and the step 70 are performed after the step 12 is performed.
In one embodiment, the step S21 is performed after the step S12 or the step S20 is performed, and the step 30, the step 50, and the step 70 are performed after the step 21 is performed.
In one embodiment, when the position of the virtual dividing line is restored to the initial position of the buffered input image frame in step S21, the frame count may also be restored to the initial count. For example, the initial count of the frame count is 1, when the step 11 is performed to increase the frame count to 100, when the step 12 is performed to move the virtual dividing line and the virtual dividing line exceeds the range of the input image frame, the step S21 is performed to restore the frame count to 1, and the virtual dividing line is restored to the initial position of the buffered input image frame.
The case where the virtual boundary exceeds the range of the input image frame includes, for example: the width of the buffered input image frame is 1000, the initial position of the virtual dividing line is located at the position of the first column of pixels of the buffered input image frame, the step 12 is executed every time the virtual dividing line is moved to the right by 100 degrees on the buffered input image frame, so that the position of the virtual dividing line is moved to the position of the 1000 th column of pixels of the buffered input image frame when the step S12 is executed 10 times in succession, and the position of the virtual dividing line is moved to the right of the 1000 th column of pixels of the buffered input image frame when the step S12 is executed 11 times, and the virtual dividing line exceeds the range of the input image frame.
In one embodiment, the programmable logic device 211, the processor 212 and the memory 213 on the video processor 210 cooperate to implement the image display method described above, which is not described herein again.
In order to understand the present embodiment more clearly, the following describes in detail a specific implementation process of the image display method of the present embodiment with reference to fig. 6A to 6F.
The video processor 210 receives a video source, an image frame of the video source is an SDR-type image, a resolution of the image frame of the video source is the same as a resolution of a display screen 220 connected to the video processor 210, and the specific widths of the image frame and the display screen 220 are both 3M
Referring to fig. 6A, the video processor 210 receives and buffers input image frames of a video source, and then obtains buffered input image frames, whose frame count is N, denoted as buffered input image frame N; the position of a virtual boundary on the buffered input image frame N is located at the position of the 1 st column of pixel data of the buffered input image frame N, which is the initial position of the virtual boundary; taking the pixel data of the buffered input image frame N on the first side of the virtual boundary as a first image part of SDR type, specifically including: the 1 st column of pixel data of the buffered input image frame N; performing dynamic range adjustment on the pixel data of the buffered input image frame N located on the second side of the virtual boundary to obtain a second image portion of an HDR type, specifically including: the buffered input image frame N is from the 2 nd column of pixel data to the 3M column of pixel data; outputting the first image portion and the second image portion to a display screen 220, displaying the first image portion on a 1 st column of pixels of the display screen 220, and displaying the second image portion on a 2 nd column of pixels to a 3M column of pixels of the display screen 220.
Further, the video processor 210 receives and buffers the next image frame of the buffered input image frame N, and performs frame count increase, as shown in fig. 6B, to obtain a buffered input image frame N +1, and moves the virtual boundary to the right at the position of the mth column of pixel data of the buffered input image frame N + 1; taking the pixel data of the buffered input image frame N +1 located on the first side of the virtual boundary as a first image portion of SDR type, specifically comprising: the buffered 1 st column pixel data to M column pixel data of the input image frame N + 1; performing dynamic range adjustment on the pixel data of the buffered input image frame N +1 located on the second side of the virtual boundary to obtain a second image portion of an HDR type, specifically including: the cached N +1, M +1 th and 3M th columns of pixel data of the input image frame; the first image portion and the second image portion are output to the display screen 220, specifically, the first image portion is displayed on the 1 st row of pixels to the M th row of pixels of the display screen 220, and the second image portion is displayed on the M +1 st row of pixels to the 3M th row of pixels of the display screen 220.
Further, the video processor 210 receives and buffers the next image frame of the buffered input image frame N +1, and performs frame count increase, as shown in fig. 6C, to obtain a buffered input image frame N +2, and moves the virtual boundary to the right at the position of the 2M column of pixel data of the buffered input image frame N + 2; taking the pixel data of the buffered input image frame N +2 located on the first side of the virtual boundary as a first image portion of SDR type, specifically comprising: the buffered 1 st column pixel data to 2M column pixel data of the input image frame N + 2; performing dynamic range adjustment on the pixel data of the buffered input image frame N +2 located on the second side of the virtual boundary to obtain a second image portion of an HDR type, specifically including: the buffered input image frame is from N +2, 2M +1 column of pixel data to 3M column of pixel data; the first image portion and the second image portion are output to the display screen 220, specifically, the first image portion is displayed on the 1 st row pixel to the 2M th row pixel of the display screen 220, and the second image portion is displayed on the 2M +1 st row pixel to the 3M th row pixel of the display screen 220.
Further, the video processor 210 receives and buffers the next image frame of the buffered input image frame N +2, and performs frame count increase, as shown in fig. 6D, to obtain a buffered input image frame N +3, and moves the virtual boundary to the right at the position of the 3M column of pixel data of the buffered input image frame N + 3; taking the pixel data of the buffered input image frame N +3 located on the first side of the virtual boundary as a first image portion of SDR type, specifically comprising: the buffered 1 st column pixel data to 3M-1 st column pixel data of the input image frame N + 3; performing dynamic range adjustment on the pixel data of the buffered input image frame N +3 located on the second side of the virtual boundary to obtain a second image portion of an HDR type, specifically including: the cached N +3 < rd > M < th > column of pixel data of the input image frame; the first image portion and the second image portion are output to the display screen 220, specifically, the first image portion is displayed on the 1 st row of pixels to the 3M-1 st row of pixels of the display screen 220, and the second image portion is displayed on the 3M th row of pixels of the display screen 220.
Further, the video processor 210 receives and buffers the next image frame of the buffered input image frame N +3, and performs frame count increase to obtain the buffered input image frame N +4, and moves the virtual boundary beyond the rightmost side of the buffered input image frame N +4 according to the above-mentioned moving manner, as shown in fig. 6E, where the virtual boundary exceeds the range of the buffered input image frame N +4, and resets the virtual boundary to the initial position to obtain the position of the virtual boundary as shown in fig. 6F; taking the pixel data of the buffered input image frame N +4 located on the first side of the virtual boundary as a first image portion of SDR type, specifically comprising: the 1 st column of pixel data of the buffered input image frame N + 4; performing dynamic range adjustment on the pixel data of the buffered input image frame N +4 located on the second side of the virtual boundary to obtain a second image portion of an HDR type, specifically including: the buffered input image frame is N +4, the 2 nd column of pixel data to the 3M column of pixel data; outputting the first image portion and the second image portion to a display screen 220, displaying the first image portion on the 1 st row of pixels of the display screen 220, and displaying the second image portion on the 2 nd row of pixels to the 3M row of pixels of the display screen 220.
In an embodiment, in the case shown in fig. 6E, the method may further include resetting the frame count, that is, resetting the virtual boundary to the initial position, and simultaneously resetting the frame count N +4 to the frame count N, where N may be from 1, and if the corresponding frame count is a multiple of 5, resetting the virtual boundary to the initial position, which is the same as the step S21, and is not described herein again.
And repeating the above processes by analogy, and the details are not repeated here.
[ second embodiment ]
Referring to fig. 7, which is an image display device according to a second embodiment of the present invention, the image display device 100 includes:
the image frame caching module 10 is used for receiving and caching the input image frame to obtain a cached input image frame;
a boundary acquiring module 20, configured to acquire a current position of the virtual boundary relative to the cached input image frame;
a first obtaining module 30, configured to obtain pixel data located on a first side of the current position of the virtual boundary in the buffered input image frame to obtain a first image portion;
a second obtaining module 50, configured to obtain pixel data of a second side, opposite to the first side, of the current position of the virtual boundary in the buffered input image frame, and perform image processing on the pixel data to obtain a second image portion; and
an output display module 70, configured to output the first image portion and the second image portion to a same display screen, so as to display the first image portion and the second image portion in two different display areas of the display screen, respectively.
In one embodiment, the image display apparatus 100 further includes, for example:
a frame counting module 11, configured to perform frame counting on the buffered input image frames;
a boundary moving module 12 for moving a position of the virtual boundary with respect to the input image frame as the frame count value changes to obtain the current position of the virtual boundary;
a border line resetting module 21, configured to restore a position of the virtual border line with respect to the input image frame to an initial position to obtain the current position of the virtual border line in response to the position of the virtual border line exceeding a boundary pixel column of the input image frame in a direction in which the virtual border line moves.
Wherein the frame counting module 11 and the boundary moving module 12 are executed after the image frame buffering module 10 is executed, and the boundary acquiring module 20, the first acquiring module 30, the second acquiring module 50 and the output display module 70 are executed after the boundary moving module 12.
Wherein the boundary resetting step 21 is performed after the boundary moving module 12 or the boundary acquiring module 20 is executed, and the first acquiring module 30, the second acquiring module 50 and the output display module 70 are performed after the boundary resetting module 21 is executed.
The image display module 100 may be a software module provided on a programmable logic device 211 of the video processor 210.
In an embodiment, the image frame buffer module 10, the boundary acquisition module 20, the first acquisition module 30, the second acquisition module 50, and the output display module 70 of the image display apparatus 100 cooperate to implement the image display method described in the first embodiment, which is not described herein again.
[ third embodiment ]
Referring to fig. 8, which is a schematic structural diagram of a computer device according to a third embodiment of the present invention, the computer device 400 includes, for example, a processor 430 and a memory 410 electrically connected to the processor 430, the memory 410 stores a computer program 411, and the processor 430 loads the computer program 411 to implement the image display method according to the first embodiment.
[ fourth example ] A
Referring to fig. 9, which is a schematic structural diagram of a storage medium according to a fourth embodiment of the present invention, the storage medium 500 is, for example, a non-volatile memory, and is, for example: magnetic media (e.g., hard disks, floppy disks, and magnetic tape), optical media (e.g., CDROM disks and DVDs), magneto-optical media (e.g., optical disks), and hardware devices specially constructed for storing and executing computer-executable instructions (e.g., Read Only Memories (ROMs), Random Access Memories (RAMs), flash memories, etc.). The storage medium 500 has stored thereon computer-executable instructions 510. The storage medium 500 may execute the computer-executable instructions 510 by one or more processors or processing devices to implement the image display method as described in the first embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and an actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An image display method, comprising:
receiving and caching an input image frame to obtain a cached input image frame;
acquiring the current position of a virtual boundary relative to the cached input image frame;
obtaining pixel data of a first side of the current position of the virtual boundary in the cached input image frame to obtain a first image portion;
acquiring pixel data of a second side, opposite to the first side, of the current position of the virtual boundary in the cached input image frame, and performing image processing to obtain a second image part, wherein the second image part and the first image part belong to images of different types of dynamic ranges; and
outputting the first image portion and the second image portion to a target display screen to display the first image portion and the second image portion in two different display areas of the target display screen, respectively.
2. The image display method according to claim 1, further comprising:
performing frame counting on the buffered input image frames;
moving a position of the virtual dividing line with respect to the input image frame as the frame count value changes to obtain the current position of the virtual dividing line.
3. The image display method according to claim 2, further comprising:
restoring a position of the virtual dividing line with respect to the input image frame to an initial position to obtain the current position of the virtual dividing line in response to the position of the virtual dividing line exceeding a boundary pixel column of the input image frame in a direction in which the virtual dividing line moves.
4. The image display method according to claim 1, wherein the two display areas are two juxtaposed and connected display areas of the target display screen; and the input image frame and the first image portion are of a standard dynamic range type.
5. An image display apparatus, comprising:
the image frame caching module is used for receiving and caching the input image frame to obtain a cached input image frame;
a boundary acquisition step for acquiring the current position of a virtual boundary relative to the cached input image frame;
a first obtaining module, configured to obtain pixel data on a first side of the current position of the virtual boundary in the cached input image frame to obtain a first image portion;
a second obtaining module, configured to obtain pixel data of a second side, opposite to the first side, of the current position of the virtual boundary in the cached input image frame, and perform image processing to obtain a second image portion, where the second image portion and the first image portion belong to images in different types of dynamic ranges; and
and the output display module is used for outputting the first image part and the second image part to a target display screen so as to respectively display the first image part and the second image part in two different display areas of the target display screen.
6. The image display device according to claim 5, further comprising:
the frame counting module is used for counting the frames of the cached input image frames;
a boundary moving module for moving a position of the virtual boundary with respect to the input image frame as the frame count value changes to obtain the current position of the virtual boundary.
7. The image display device according to claim 6, further comprising:
a dividing line resetting module, configured to restore a position of the virtual dividing line with respect to the input image frame to an initial position to obtain the current position of the virtual dividing line in response to the position of the virtual dividing line exceeding a boundary pixel column of the input image frame in a direction in which the virtual dividing line moves.
8. The image display device according to claim 5, wherein the two display regions are two juxtaposed and adjoining display regions of the display screen; and the input image frame and the first image portion are of a standard dynamic range type.
9. A video processor, comprising:
a memory;
a programmable logic device electrically connected to the memory for receiving an input image frame and buffering to the memory to obtain a buffered input image frame, obtaining a current position of a virtual dividing line with respect to the buffered input image frame, obtaining pixel data of a first side of the buffered input image frame located at the current position of the virtual dividing line to obtain a first image portion, obtaining pixel data of a second side of the buffered input image frame located at the current position of the virtual dividing line with respect to the first side and performing image processing to obtain a second image portion, and outputting the first image portion and the second image portion to a target display screen to display the first image portion and the second image portion in two different display areas of the display screen, respectively; wherein the second image portion and the first image portion belong to different types of dynamic range images.
10. An image display system, comprising:
the video processor of claim 9; and
and the display screen is connected with the video processor and serves as the target display screen.
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