CN112823569A - Dimming circuit and integrated circuit - Google Patents

Dimming circuit and integrated circuit Download PDF

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CN112823569A
CN112823569A CN201880098203.5A CN201880098203A CN112823569A CN 112823569 A CN112823569 A CN 112823569A CN 201880098203 A CN201880098203 A CN 201880098203A CN 112823569 A CN112823569 A CN 112823569A
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switch
ith
circuit
dimming
current
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CN112823569B (en
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刘德尚
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/02—Manually-operated control

Abstract

A dimming circuit and an integrated circuit are used for solving the problems of poor visual effect and high cost of the existing dimming mode. The dimming circuit includes: the output end of the ith exponential amplification circuit is connected with the input end of an (i + 1) th exponential amplification circuit through an ith first switch, the output end of the Nth exponential amplification circuit is connected with a driving circuit of a light source to be dimmed, the output end of the ith exponential amplification circuit is also connected with the output end of the (i + 1) th exponential amplification circuit through an ith second switch, i is 1,2 and … N, and N is a positive integer; the input end of the ith exponential amplification circuit is connected with the ith third switch and used for obtaining preset current through the ith third switch. The ith exponential amplifying circuit is used for amplifying the input current of the ith exponential amplifying circuit.

Description

Dimming circuit and integrated circuit Technical Field
The present application relates to the field of circuit technology, and in particular, to a dimming circuit and an integrated circuit.
Background
Backlight technology is widely applied to display screens of mobile phones, tablet computers and other devices to increase the illumination and brightness of the display screens in a low light source environment, wherein the backlight source may be a Light Emitting Diode (LED) or a Cold Cathode Fluorescent Lamp (CCFL).
The brightness of the backlight of the display screen needs to be adjusted (i.e. adjusted) at any time to ensure the display effect of the display screen and the visual effect of the user. The dimming of the display screen is realized by adjusting the magnitude of the driving current of the display screen backlight, and the most common dimming mode at present is a linear dimming mode, that is, the driving current of the display screen backlight changes linearly. The linear dimming method is simple to implement, but has a poor visual effect, for example, in a scene with dark ambient light, since the driving current of the backlight of the display screen in the linear dimming method changes linearly, the minimum adjustable current is a fixed value, the change of light intensity caused by each adjustment easily causes eye discomfort, the resolution bit width needs to be increased to alleviate the problem, and the linear dimming method has high cost and limited benefit.
Disclosure of Invention
The application provides a dimming circuit and an integrated circuit for solve the problem that the current dimming mode visual effect is relatively poor, and is with high costs.
In a first aspect, the present application provides a dimming circuit, comprising: the output end of the ith exponential amplification circuit is connected with the input end of an (i + 1) th exponential amplification circuit through an ith first switch, the output end of the Nth exponential amplification circuit is connected with a driving circuit of a light source to be dimmed, the output end of the ith exponential amplification circuit is also connected with the output end of the (i + 1) th exponential amplification circuit through an ith second switch, i is 1,2 and … N, and N is a positive integer; the input end of the ith exponential amplification circuit is connected with the ith third switch and used for obtaining preset current through the ith third switch. The ith exponential amplifying circuit is used for amplifying the input current of the ith exponential amplifying circuit.
By the scheme, the dimming circuit can enable one or more of the N exponential amplifying circuits to be cascaded by changing the state of the switch connected between the N exponential amplifying circuits in the dimming circuit, the preset current can be quickly adjusted to be the target current by an exponential proportionality coefficient, so that the brightness of the light source to be dimmed reaches the target brightness, the exponential dimming is further realized, the realization mode is simple, the dimming circuit does not need to be controlled through complex digital operation, and the cost is low.
In addition, because the N exponential amplification circuits are cascaded through the switch, the exponential amplification circuits in the dimming circuit can be flexibly combined according to the magnitude of the target current, and the driving current of the light source to be dimmed is quickly adjusted to the target current.
In one possible embodiment, the ith first switch, the ith second switch, the ith third switch, and the nth third switch may be switches formed by a bipolar transistor BJT or a metal oxide semiconductor MOS transistor.
In one possible embodiment, the scaling factor of the ith exponential amplifying circuit is af(i)Wherein a is a set positive number, f (i) is a function value related to i, that is, the output current of the ith exponential amplifying circuit conforms to the following formula:
I Oi＝a f(i)*I INi
wherein, IOiIs the output current of the ith exponential amplifying circuit, IINiAnd a is the set positive number, and f (i) is a function value obtained by inputting the value of i into a preset function f.
Further, f (i) ═ 2(i-1)So that the dimming circuit can realize the preset current, the number of which is a base, is 1 to (2)N-1) amplification of a scaling factor with any integer as a power.
One possible implementation methodIn the formula, the ith exponential amplification circuit comprises a voltage amplification circuit and a voltage-current conversion circuit, and the voltage amplification circuit is connected with the voltage-current conversion circuit; the voltage amplifying circuit is used for amplifying the voltage IINiIs converted into a first voltage VINiAnd for said VINiAmplifying to obtain a second voltage VOiWherein V isOi＝a f(i)*V INi(ii) a The voltage-current conversion circuit is used for converting the voltage V into the current VOiIs converted into the IOi。
Further, the ith exponential amplifying circuit can be implemented by any one of, but not limited to, the following two ways:
in a first mode, the voltage amplifying circuit comprises an operational amplifier, a first resistor and a second resistor; the voltage-current conversion circuit comprises an N-channel metal oxide semiconductor (NMOS) transistor and a current mirror; the positive phase input end of the operational amplifier is connected with one end of the first resistor, the inverting input end of the operational amplifier and the source electrode of the NMOS transistor are connected with one end of the second resistor, the inverting input end of the operational amplifier is connected with the grid electrode of the NMOS transistor, the drain electrode of the NMOS transistor is connected with the input end of the current mirror, the output end of the current mirror is connected with the output end of the (i + 1) th exponential amplification circuit, and the power supply end of the current mirror is connected with a power supply; the other end of the first resistor and the other end of the second resistor are both grounded.
Wherein R is2i＝a f(i)*R 1i，R 2iIs the resistance value, R, of the second resistor1iThe input current of the current mirror is opposite to the output current of the current mirror in polarity as the resistance value of the first resistor.
In a second mode, the voltage amplifying circuit comprises an operational amplifier, a first resistor and a second resistor; the voltage-current conversion circuit comprises a current mirror, the inverting input end of the operational amplifier is connected with one end of the first resistor, the non-inverting input end of the operational amplifier and the input end of the current mirror are connected with one end of the second resistor, the output end of the current mirror is connected with the output end of the (i + 1) th exponential amplification circuit, and the power supply end of the current mirror is connected with a power supply; the other end of the first resistor and the other end of the second resistor are both grounded. At this time, the inverting input terminal of the operational amplifier is the input terminal of the ith exponential amplification circuit, and the output terminal of the current mirror is the output terminal of the ith exponential amplification circuit.
Wherein R is2i＝a f(i)*R 1i，R 2iIs the resistance value, R, of the second resistor1iThe input current of the current mirror is opposite to the output current of the current mirror in polarity as the resistance value of the first resistor.
In a possible embodiment, the dimming circuit further includes a controller, and the controller is connected to the control terminals of the ith first switch, the ith second switch, and the ith third switch respectively.
The controller is configured to control states of the ith first switch, the ith second switch, and the ith third switch according to a magnitude of a target current and a magnitude of the preset current; the target current is determined according to the target brightness to which the light source to be dimmed needs to be adjusted; when the dimming circuit works, the state of the ith first switch is opposite to that of the ith second switch, and only one of the N third switches is in a conducting state.
In a possible embodiment, the dimming circuit further includes a decoding circuit, an input terminal of the decoding circuit is connected to the controller, and an output terminal of the decoding circuit is connected to control terminals of the ith first switch, the ith second switch, and the ith third switch, respectively.
The controller is specifically configured to: generating the dimming code according to the magnitude of the target current and the magnitude of the preset current; the decoding circuit is configured to generate control signals corresponding to the ith first switch, the ith second switch, the ith third switch, and the nth third switch according to the dimming code.
In one possible embodiment, the dimming code is an N-bit binary number, and 1 in the dimming code is represented by a first level and 0 is represented by a second level. The decoding circuit is specifically configured to: using the level corresponding to the (i + 1) th bit from the lower bit in the dimming code as a control signal of the ith first switch; performing non-operation on the (i + 1) th bit of the dimming code to obtain a control signal of the ith second switch; using the level corresponding to the jth digit in the dimming code as a control signal of a jth third switch, and generating the second level as control signals of other third switches except the jth third switch;
wherein, the j-th digit is the first 1 from the low order in the dimming code, j is a positive integer, and j is less than or equal to N; the first level is used for controlling the first switch, the second switch and the third switch to be turned on, and the second level is used for controlling the first switch, the second switch and the third switch to be turned off.
In a second aspect, the present application also provides another dimming circuit, comprising: the output end of the ith exponential amplification circuit is connected with the input end of an (i + 1) th exponential amplification circuit through an ith first switch, the output end of the nth exponential amplification circuit is connected with the input end of the voltage-current conversion circuit, the output end of the voltage-current conversion circuit is connected with a driving circuit of a light source to be dimmed, the output end of the ith exponential amplification circuit is also connected with the output end of the (i + 1) th exponential amplification circuit through an ith second switch, and i is 1,2, … N, wherein N is a positive integer; and the input end of the ith exponential amplification circuit is connected with the ith third switch and used for presetting voltage through the ith third switch. The ith exponential amplifying circuit is used for amplifying the input voltage of the ith exponential amplifying circuit; the voltage-current conversion circuit is used for converting the input voltage of the voltage-current conversion circuit into the target current.
By the scheme, the dimming circuit can enable one or more of the N exponential amplifying circuits to be cascaded by changing the state of the switch connected between the N exponential amplifying circuits in the dimming circuit, the preset voltage is rapidly adjusted to the voltage corresponding to the target current in an exponential amplification mode, so that the brightness of the light source to be dimmed reaches the target brightness, and then the exponential dimming is realized.
In addition, because the N exponential amplification circuits are cascaded through the switch, the exponential amplification circuits in the dimming circuit can be flexibly combined according to the magnitude of the target current, and the driving current of the light source to be dimmed is quickly adjusted to the target current.
In one possible embodiment, the scaling factor of the ith exponential amplifying circuit is af(i)A is a set positive number, f (i) is a function value related to i, namely, the output voltage of the ith exponential amplification circuit conforms to the following formula:
V Oi＝a f(i)*V INi；
wherein, VOiIs the output voltage, V, of the ith exponential amplifying circuitINiAnd a is the set positive number, and f (i) is a function value obtained by inputting the value of i into a preset function f.
Further, f (i) ═ 2(i-1)So that the dimming circuit can realize the preset current, the number of which is a base number is 1 to (2)N-1) amplification of a scaling factor with any integer as a power.
In a possible embodiment, the ith exponential amplifying circuit can be implemented by any one of, but not limited to, the following three ways:
mode a, the ith exponential amplifying circuit includes a first operational amplifier, a first resistor, and a second resistor, where a positive phase input terminal of the first operational amplifier is connected to an output terminal of the ith third switch, a negative phase input terminal of the first operational amplifier is connected to one end of the first resistor and one end of the second resistor, respectively, the other end of the first resistor is grounded, and the other end of the second resistor is connected to an output terminal of the first operational amplifier.
Wherein the content of the first and second substances,
Figure PCTCN2018109661-APPB-000001
R 2iis the resistance value, R, of the second resistor1iIs the resistance value of the first resistor.
Mode B, the ith exponential amplifying circuit includes a first operational amplifier, a first resistor, a second resistor, and a PMOS transistor, and constitutes a source follower amplifying circuit, an inverting input terminal of the first operational amplifier is connected to an output terminal of the ith third switch, a non-inverting input terminal of the first operational amplifier is connected to one end of the first resistor and one end of the second resistor, respectively, the other end of the first resistor is grounded, the other end of the second resistor is connected to a drain of the PMOS transistor, an output terminal of the first operational amplifier is connected to a gate of the PMOS transistor, and a source of the PMOS transistor is connected to a power supply.
Wherein the content of the first and second substances,
Figure PCTCN2018109661-APPB-000002
R 2iis the resistance value, R, of the second resistor1iThe PMOS transistor may also be replaced by a PNP transistor for the resistance of the first resistor.
Mode C, the ith exponential amplifying circuit includes a first operational amplifier, a first resistor, a second resistor, and an NMOS transistor, wherein a positive phase input terminal of the first operational amplifier is connected to an output terminal of the ith third switch, an inverting input terminal of the first operational amplifier is connected to one end of the first resistor and one end of the second resistor, respectively, the other end of the first resistor is grounded, the other end of the second resistor is connected to a source of the NMOS transistor, an output terminal of the first operational amplifier is connected to a gate of the NMOS transistor, and a drain of the NMOS transistor is connected to a power supply.
Wherein the content of the first and second substances,
Figure PCTCN2018109661-APPB-000003
R 2iis the resistance value, R, of the second resistor1iThe PMOS transistor may also be replaced by an NPN transistor as the resistance of the first resistor.
In one possible embodiment, the dimming circuit further includes: the input end of the current-voltage conversion circuit is used for inputting preset current, and the output end of the current-voltage conversion circuit is respectively connected with the input end of the ith third switch and the input end of the Nth third switch; the current-voltage conversion circuit is used for converting the preset current into the preset voltage.
In a possible implementation manner, the current-voltage conversion circuit includes a third resistor, one end of the third resistor is connected to the input end of the ith third switch and the input end of the nth third switch, respectively, for inputting the preset current, and the other end of the third resistor is grounded.
In one possible implementation, the voltage-current conversion circuit includes a second operational amplifier, a fourth resistor, an N-channel metal oxide semiconductor NMOS transistor, and a current mirror. The positive phase input end of the second operational amplifier is connected with the output end of the Nth exponential amplification circuit, the negative phase input end of the second operational amplifier and the source electrode of the NMOS transistor are connected with one end of the fourth resistor, the other end of the fourth resistor is grounded, the grid electrode of the NMOS transistor is connected with the output end of the second operational amplifier, the drain electrode of the NMOS transistor is connected with the input end of the current mirror, the output end of the current mirror is connected with the driving circuit of the light source to be dimmed, and the power supply end of the current mirror is connected with the power supply; the input current of the current mirror is opposite in polarity to the output current of the current mirror.
Further, the resistance value of the fourth resistor and the resistance value of the third resistor satisfy the following formula: r3＝M*R 4，R 3Is the resistance value, R, of the third resistor4And M is the resistance value of the fourth resistor and is a preset positive number.
In a possible embodiment, the dimming circuit further includes a controller, and the controller is connected to the control terminals of the ith first switch, the ith second switch, and the ith third switch respectively.
The controller is used for controlling the states of the ith first switch, the ith second switch and the ith third switch according to the magnitude of target current and the magnitude of the preset voltage; the target current is determined according to the target brightness to which the light source to be dimmed needs to be adjusted; when the dimming circuit works, the state of the ith first switch is opposite to that of the ith second switch, and only one of the N third switches is in a conducting state.
In a possible embodiment, the dimming circuit further includes a decoding circuit, an input terminal of the decoding circuit is connected to the controller, and an output terminal of the decoding circuit is connected to control terminals of the ith first switch, the ith second switch, and the ith third switch, respectively.
Wherein the controller is specifically configured to: generating a dimming code according to the magnitude of the target current and the magnitude of the preset voltage; the decoding circuit is configured to generate control signals corresponding to the ith first switch, the ith second switch, and the ith third switch according to the dimming code.
In one possible embodiment, the dimming code is an N-bit binary number, and 1 in the dimming code is represented by a first level and 0 is represented by a second level. The decoding circuit is specifically configured to use a level corresponding to an i +1 th bit from a lower bit in the dimming code as a control signal of the i-th first switch; performing non-operation on the (i + 1) th bit of the dimming code to obtain a control signal of the ith second switch; using the level corresponding to the jth digit in the dimming code as a control signal of a jth third switch, and generating the second level as control signals of other third switches except the jth third switch; wherein, the j-th digit is the first 1 from the low order in the dimming code, j is a positive integer, and j is not more than N; the first level is used for controlling the first switch, the second switch and the third switch to be turned on, and the second level is used for controlling the first switch, the second switch and the third switch to be turned off.
In a third aspect, the present application further provides an integrated circuit, which includes the dimming circuit described in any one of the possible implementation manners of the first aspect, or the dimming circuit described in any one of the possible implementation manners of the second aspect.
Drawings
Fig. 1 is a schematic structural diagram of a dimming circuit provided in the present application;
fig. 2 is a second schematic diagram of a dimming circuit according to the present application;
fig. 3 is a schematic structural diagram of a voltage amplifying circuit in a dimming circuit provided in the present application;
fig. 4a is a schematic structural diagram of an exponential amplifying circuit in a dimming circuit provided in the present application;
fig. 4b is a second schematic diagram of an exponential amplifying circuit in a dimming circuit provided in the present application;
fig. 4c is a third schematic diagram of an exponential amplifying circuit in a dimming circuit provided in the present application;
fig. 5 is a third schematic diagram of a dimming circuit according to the present application;
fig. 6 is a fourth schematic diagram of a dimming circuit according to the present application;
fig. 7 is a schematic diagram illustrating an operation principle of a decoding circuit in a dimming circuit according to the present application;
fig. 8 is a schematic diagram of another dimming circuit according to the present application;
fig. 9 is a second schematic diagram of another dimming circuit according to the present application;
fig. 10a is a schematic diagram of an exponential amplifying circuit in another dimming circuit provided in the present application;
fig. 10b is a second schematic diagram of an exponential amplifying circuit in another dimming circuit provided in the present application;
fig. 10c is a third schematic diagram of an exponential amplifying circuit in another dimming circuit provided in the present application;
fig. 10d is a fourth schematic diagram of an exponential amplifying circuit in another dimming circuit provided in the present application;
fig. 10e is a fifth schematic diagram of an exponential amplifying circuit in another dimming circuit provided in the present application;
fig. 11 is a third schematic diagram of another dimming circuit according to the present application;
fig. 12 is a schematic structural diagram of a current-voltage conversion circuit in another dimming circuit provided in the present application;
fig. 13 is a schematic structural diagram of a voltage-current conversion circuit in another dimming circuit provided in the present application;
fig. 14 is a fourth schematic diagram of another dimming circuit provided in the present application;
fig. 15 is a fifth schematic diagram of another dimming circuit according to the present application.
Detailed Description
Although the linear dimming mode is simple in implementation mode, the visual effect is poor, the cost is high, and compared with the linear dimming mode, the driving current of the backlight lamp of the display screen in the exponential dimming mode is changed exponentially, and the minimum adjustable current is small, so that the dimming is fine and smooth, and the visual experience of human eyes is good. However, the implementation difficulty of the precise exponential relationship in the analog circuit is high, the implementation mode of the exponential dimming mode is usually complex, the hardware resource consumption is high, and the cost is high.
For example, the exponential dimming is realized by a linear piecewise fitting method, because the corresponding hardware circuit is also realized piecewise, the continuity of the dimming is poor near the piecewise point, and in order to realize more accurate exponential characteristics, the number of piecewise intervals is more, and each piecewise interval needs to be realized by the corresponding hardware circuit, which results in higher realization cost.
In order to solve the above problems, the present application provides a dimming circuit and an integrated circuit, which implement exponential dimming through a plurality of cascaded exponential operational amplification circuits, and have a simpler implementation manner, can reduce the cost of a circuit corresponding to the exponential dimming manner, and have a more accurate exponential characteristic.
In addition, it is to be understood that, in the description of the present application, "a plurality" means two or more; the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor order.
In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.
The present application provides a dimming circuit, as shown in fig. 1, the dimming circuit 100 includes N exponential amplification circuits 110, wherein an output terminal of an ith exponential amplification circuit 110 passes through an ith first switch S<i>The output end of the ith exponential amplification circuit 110 is connected with the input end of the (i + 1) th exponential amplification circuit 110, the output end of the nth exponential amplification circuit 110 is connected with a driving circuit of a light source to be dimmed, and the output end of the ith exponential amplification circuit 110 is also connected with the driving circuit of the light source to be dimmed through the ith second switch NS<i>The output end of the (i + 1) th exponential amplification circuit 110 is connected, i is 1,2, … N, and N is a positive integer; the input terminal of the ith exponential amplifying circuit 110 is further connected with an ith third switch R<i>Is connected for passing through the ith third switch R<i>Obtaining a predetermined current IREF. The ith exponential amplifying circuit 110 is configured to amplify an input current of the ith exponential amplifying circuit 110.
The light source to be dimmed may be a light emitting source of a display screen, that is, the dimming circuit 100 may be applied to a display device; alternatively, the light source to be dimmed may be an illumination light source, i.e., the dimming circuit 100 may be applied to an illumination apparatus. The ith first switch S < i >, the ith second switch NS < i >, the ith third switch R < i >, and the nth third switch R < N > may be controllable switches formed of Bipolar Junction Transistors (BJTs), metal-oxide semiconductor (MOS) transistors, or other semiconductors. It should be noted that, in the embodiments of the present application, specific structures of the ith first switch S < i >, the ith second switch NS < i >, the ith third switch R < i >, and the nth third switch R < N > are not limited, and the structures of the ith first switch S < i >, the ith second switch NS < i >, the ith third switch R < i >, and the nth third switch R < N > may be the same or different.
Further, the scaling factor of the ith exponential amplifying circuit is af(i)Where a is a set positive number and f (i) is a function value associated with i. I.e. the output current I of the I-th exponential amplification circuitOiThe following formula is satisfied:
I Oi＝a f(i)*I INi；
wherein, IINiAnd f (i) a function value obtained after the value i is input into a preset function f, wherein "+" represents multiplication. Wherein the preset function f for i can be determined according to the requirements of the actual dimming scenario (e.g. the adjustment speed) and the requirements of the dimming circuit 100 (e.g. the cost). That is, the output current of each of the exponential amplifying circuits in the dimming circuit 100 is determined by the input current of the exponential amplifying circuit and an exponential value, and the exponential characteristic is more accurate.
Specifically, as shown in fig. 2, the preset function f may be f (i) -2(i-1)So that the dimming circuit 100 can realize the preset current IREFBase number a, 1 to (2)NAny integer of-1) isAmplification of the scaling factor of the power. For example, the dimming circuit 100 may amplify the preset current I through the first exponential amplifying circuit 110REFIs amplified to
Figure PCTCN2018109661-APPB-000004
The predetermined current I can be amplified by the second exponential amplifying circuit 110REFIs amplified to
Figure PCTCN2018109661-APPB-000005
The predetermined current I can be amplified by the first and second exponential amplifying circuits 110 and 110REFIs amplified to
Figure PCTCN2018109661-APPB-000006
And so on.
In one possible embodiment, as shown in fig. 3, the ith exponential amplifying circuit 110 includes a voltage amplifying circuit 111 and a voltage-current converting circuit 112, and the voltage amplifying circuit 111 is connected to the voltage-current converting circuit 112. Wherein the voltage amplifying circuit 111 is used for amplifying the IINiIs converted into a first voltage VINiAnd for said VINiAmplifying to obtain a second voltage VOiWherein V isOi＝a f(i)*V INi(ii) a The voltage-current conversion circuit 112 is used for converting the voltage V into the current VOiIs converted into the IOi。
In specific implementation, the ith exponential amplifying circuit 110 may be implemented by, but is not limited to, any one of the following two ways:
first, as shown in fig. 4a, the voltage amplifying circuit 111 includes an operational amplifier OP0, a first resistor R11 and a second resistor R12; the voltage-current conversion circuit 112 includes an NMOS transistor Q0 and a current mirror M0, a non-inverting input terminal of the operational amplifier OP0 is connected to one end of the first resistor R11, an inverting input terminal of the operational amplifier OP0 and a source of the NMOS transistor Q0 are connected to one end of the second resistor R12, an inverting input terminal of the operational amplifier OP0 is connected to a gate of the NMOS transistor Q0, a drain of the NMOS transistor Q0 is connected to an input terminal of the current mirror M0, an output terminal of the current mirror M0 is connected to an output terminal of the i +1 th exponential amplification circuit 110, and a power supply terminal of the current mirror M0 is connected to a power supply; the other end of the first resistor R11 and the other end of the second resistor R12 are both grounded. At this time, the non-inverting input terminal of the operational amplifier OP0 is the input terminal of the ith exponential amplifying circuit 110, and the output terminal of the current mirror M0 is the output terminal of the ith exponential amplifying circuit 110.
Wherein R is2i＝a f(i)*R 1i，R 2iIs the resistance value of the second resistor R121iThe input current of the current mirror M0 is opposite in polarity to the output current of the current mirror M0 for the resistance value of the first resistor R11.
In addition, the NMOS transistor in the ith exponential amplifying circuit 110 shown in fig. 4a may be replaced by an NPN transistor, as shown in fig. 4 b.
Second, as shown in fig. 4c, the voltage amplifying circuit 111 includes an operational amplifier OP0, a first resistor R11 and a second resistor R12; the voltage-current conversion circuit 112 includes a current mirror M0, an inverting input terminal of the operational amplifier OP0 is connected to one end of the first resistor R11, a non-inverting input terminal of the operational amplifier OP0 and an input terminal of the current mirror M0 are connected to one end of the second resistor R12, an output terminal of the current mirror M0 is connected to an output terminal of the i +1 th exponential amplification circuit 110, and a power supply terminal of the current mirror M0 is connected to a power supply; the other end of the first resistor R11 and the other end of the second resistor R12 are both grounded. At this time, the inverting input terminal of the operational amplifier OP0 is the input terminal of the ith exponential amplifying circuit 110, and the output terminal of the current mirror M0 is the output terminal of the ith exponential amplifying circuit 110.
Wherein R is2i＝a f(i)*R 1i，R 2iIs the resistance value of the second resistor R121iThe input current of the current mirror M0 is opposite in polarity to the output current of the current mirror M0 for the resistance value of the first resistor R11.
In a specific implementation, the current mirror M0 may be implemented by a triode or a MOS transistor. For example, as shown in fig. 4a, 4b and 5, the current mirror M0 includes a PMOS transistor QaAnd a PMOS transistor QbSaid PMOS transistor QaAnd the PMOS transistor QbAs a power supply terminal of the current mirror M0, the PMOS transistor QaAnd the PMOS transistor QaAnd the PMOS transistor QbAs an input of the current mirror M0, the PMOS transistor QbAs an output terminal of the current mirror. The specific structure of the current mirror M0 is merely an example, and is not intended to limit the embodiments of the present application.
Further, the current mirror M0 may be used to change the polarity (i.e. the direction of the current) of the current inputted to the current mirror M0, and also to scale up the current inputted to the current mirror M0, so as to further amplify the output current of the i-th exponential amplification circuit 110.
It should be noted that, in the embodiment of the present application, a specific implementation manner of the ith exponential amplifying circuit 110 is not limited, and the specific implementation manners of the ith exponential amplifying circuit 110 described in the first and second manners are merely examples, and any circuit structure capable of implementing the function of the ith exponential amplifying circuit 110 is applicable to the embodiment of the present application.
Optionally, as shown in fig. 5, the dimming circuit 100 further includes a controller 120, and the controller 120 is connected to the ith first switch S < i >, the ith second switch NS < i >, and the ith third switch R < i >, respectively;
the controller 120 is used for controlling the current I according to the target currentLEDIs largeSmall and the preset current IREFControls the ith first switch S<i>The ith second switch NS<i>And the ith third switch R<i>The state of (1);
wherein the target current ILEDThe size of the light source to be dimmed is determined according to the target brightness to which the light source to be dimmed needs to be adjusted; when the dimming circuit works, the ith first switch S<i>And the ith second switch NS<i>In the opposite state, only one of the N third switches is in a conducting state.
When the dimming circuit 100 is operated, only one of the N third switches is turned on, and if an nth third switch R < N > of the N third switches is turned on, all the third switches except the nth third switch R < N > are turned off, and the nth-1 exponential operation circuit 110 outputs no signal, so that the nth-1 first switch S < N-1> may be turned on or off, and in order to improve the operating efficiency of the dimming circuit 100, the nth-1 first switch S < N-1> may be turned off, where N is 1,2, and … N when the nth third switch R < N > is turned on.
For example, the output current I of the ith exponential amplifying circuitOi＝a f(i)*I INiAnd when the dimming circuit 100 is in operation, the third switch R<3>Conducting, the other third switch (R)<1>、R<2>And R<4>～R<N>) Off, the second first switch S<2>And a fifth first switch S<5>On, the other first switch (S)<1>、S<3>、S<4>And S<6>～S<N-1>) Off, second switch NS<2>And a fifth second switch NS<5>Off, the other second switch (NS)<1>、NS<3>、NS<4>And N S<6>～N S<N-1>) On, the output current I of the dimming circuit 100OThe following were used:
I O＝I O6＝a f(6)*I IN6＝a f(6)*I O5＝a f(6)+f(3)*I IN3＝a f(6)+f(3)*I REF
when the third switch R <3> is turned on, the second switch S <2> can also be turned off.
Further, as shown in fig. 6, the dimming circuit 100 further includes a decoding circuit 130, an input terminal of the decoding circuit 130 is connected to the controller 120, and an output terminal of the decoding circuit 130 is connected to control terminals of the ith first switch S < i >, the ith second NS < i > switch and the ith third switch R < i >, respectively.
Wherein the controller 120 is specifically configured to: according to the target current ILEDAnd the predetermined current IREFTo generate a dimming code. The decoding circuit 130 is configured to generate the ith first switch S according to the dimming code<i>The ith second switch NS<i>And the ith third switch R<i>The corresponding control signal.
In one possible embodiment, the dimming code is an N-bit binary number, and 1 in the dimming code is represented by a first level and 0 is represented by a second level. At this time, the decoding circuit 130 is specifically configured to: using the level corresponding to the (i + 1) th bit from the lower bit in the dimming code as the control signal of the ith first switch S < i >; performing a non-operation on the (i + 1) th bit of the dimming code to obtain a control signal of the ith second switch NS < i >; using the level corresponding to the j-th digit in the dimming code as a control signal of a j-th third switch R < j >, and generating the second level as control signals of other third switches except the j-th third switch R < j >; wherein, the j-th digit is the first 1 from the low order in the dimming code, j is a positive integer, and j is less than or equal to N; the first level is used for controlling the first switch, the second switch and the third switch to be turned on, and the second level is used for controlling the first switch, the second switch and the third switch to be turned off.
The first level is a high level and the second level is a low level, or the first level is a low level and the second level is a high level. When the decoding circuit 130 generates the second level as the control signal of the third switch other than the jth third switch R < j >, the second level may be directly generated as the control signal of the third switch other than the jth third switch R < j >, or the second level may be obtained by performing a logical operation on the first switches S <1> to S < j-1> and the jth bit number of the dimming code from a low bit.
Specifically, as shown in fig. 7, it is assumed that the dimming code is code < N:1>, and the dimming code is code <1>, code <2>, …, and code < N > in sequence from the lower order to the upper order, and at this time, the operation principle of the decoding circuit 130 is as follows: the control signal of the ith first switch S < i > is the level corresponding to the code < i +1> of the (i + 1) th bit of the dimming code < N:1 >. The control signal of the ith second switch NS < i > is the level corresponding to the i +1 bit code < i +1> of the dimming code < N:1> after being subjected to non-operation, namely the result obtained after the i +1 bit code < i +1> of the dimming code < N:1> is input into a non-gate is subjected to non-operation on the control signal of the ith second switch NS < i > to obtain the control signal of the ith first switch S < i >.
The control signal of the first third switch R <1> is the level corresponding to the 1 st bit (lowest bit) code <1> of the dimming code < N:1 >; the control signal of the second third switch R <2> is the result of the non-operation of the control signal of the first switch S <1>, and the result is obtained by the AND operation of the level corresponding to the 2 nd bit code <2> of the dimming code < N:1 >; the control signal of the third switch R <3> is the result SN _1_2 obtained by carrying out NOR operation on the control signal of the first switch S <1> and the control signal of the second switch S <2>, and the result SN _1_2 is obtained by carrying out AND operation on the level corresponding to the 3 rd bit code <3> of the dimming code < N:1 >; the control signal of a fourth third switch R <4> is a result obtained after the SN _1_2 is subjected to non-operation, and is subjected to the non-operation with a third first switch S <3> to obtain a result SN _1_3, and the SN _1_3 is subjected to the and operation with the level corresponding to the 4 th code <4> of the dimming code < N:1 >; the control signal of a fifth third switch R <5> is a result obtained after the SN _1_3 is subjected to the NOT operation, the control signal is subjected to the NOT operation with a fourth first switch S <4> to obtain a result SN _1_4, and the SN _1_4 is subjected to the AND operation with the level corresponding to the 5 th code <5> of the dimming code < N:1 >; in this way, the control signal of the kth third switch R < k > is the result obtained after the SN _1_ k-2 is subjected to the NOT operation, the control signal is subjected to the NOT operation with the kth first switch S < k-1> to obtain a result SN _1_ k-1, the SN _1_ k-1 is subjected to the AND operation with the level corresponding to the kth code < k > of the dimming code < N:1>, wherein k is more than or equal to 4 and less than or equal to N, and k is an integer.
It should be noted that, the decoding circuit 130 decodes and generates the control signals corresponding to the ith first switch, the ith second switch, the ith third switch and the nth third switch according to the received dimming code, which is only an example and is not limited to this application, the number of bits of the dimming code and the meaning of each bit representation of the dimming code are different, the decoding method of the decoding circuit 130 is also different, and all the decoding methods that can decode and generate the control signals corresponding to the ith first switch, the ith second switch, the ith third switch and the nth third switch according to the received dimming code and control one or more of the exponential amplifying circuits 110 in the dimming circuit 100 to realize the exponential dimming are suitable for this application embodiment.
In addition, when the output current I of the ith exponential amplification circuitOiSatisfied formula IOi＝a f(i)*I INiWherein a 2 and f (i) 2(i-1)The dimming circuit 100 can also realize linear dimming. Specifically, when the dimming circuit 100 operates in the linear dimming mode (i.e., a is 2, f (i) is 2)(i-1)In time), N-1 the first switches are all in an off state, N-1 the second switches are all in an on state, and the first switchi third switches R<i>And the Nth third switch R<N>State according to the preset current IREFAnd the target current ILEDN of said third switches may be in a conducting state simultaneously.
By the above scheme, the dimming circuit 100 can enable one or more of the N exponential amplification circuits 110 to be cascaded by changing the states of the switches connected between the N exponential amplification circuits 110 in the dimming circuit, so as to quickly couple the preset current IREFAdjusting the target current I by an exponential proportionality coefficientLEDThe light source to be dimmed is enabled to reach the target brightness, so that the exponential dimming is realized, the realization mode is simple, the dimming circuit is not required to be controlled through complex digital operation, and the cost is low.
In addition, since the N exponential amplifying circuits 110 are cascaded through the switch, the exponential amplifying circuit 110 in the dimming circuit 100 can be according to the target current ILEDThe driving current of the light source to be dimmed is quickly adjusted to the target current by flexibly combining the sizes of the light sources to be dimmed.
The present application also provides another dimming circuit, as shown in fig. 8, the dimming circuit 800 includes: n exponential amplification circuits 810 and a voltage-current conversion circuit 820, wherein the output end of the ith exponential amplification circuit 810 passes through the ith first switch S<i>The output end of the nth exponential amplification circuit 810 is connected with the input end of the voltage-current conversion circuit 820, the output end of the voltage-current conversion circuit 820 is connected with the driving circuit of the light source to be dimmed, and the output end of the ith exponential amplification circuit 810 is further connected with the input end of the (i + 1) th exponential amplification circuit 820 through the ith second switch NS<i>The output end of the (i + 1) th exponential amplification circuit is connected, i is 1,2, … N, and N is a positive integer; the input end of the ith exponential amplifying circuit 810 is also connected with an ith third switch R<i>Is connected for passing through the ith third switch R<i>Obtaining a preset voltage VREF。
The light source to be dimmed may be a light emitting source of a display screen, that is, the dimming circuit 800 may be applied to a display device; alternatively, the light source to be dimmed may be an illumination light source, i.e., the dimming circuit 800 may be applied to an illumination apparatus. The ith first switch S < i >, the ith second switch NS < i >, the ith third switch R < i > and the nth third switch R < N > may be controllable switches formed by semiconductor devices such as BJT or MOS transistors. It should be noted that, in the embodiments of the present application, specific structures of the ith first switch S < i >, the ith second switch NS < i >, the ith third switch R < i >, and the nth third switch R < N > are not limited, and the structures of the ith first switch S < i >, the ith second switch NS < i >, the ith third switch R < i >, and the nth third switch R < N > may be the same or different.
Further, the scaling factor of the ith exponential amplifying circuit is af(i)A is a set positive number, and f (i) is a function value associated with i. I.e. the output voltage V of the i-th exponential amplification circuitOiThe following formula is satisfied:
V Oi＝a f(i)*V INi；
wherein, VINiAnd a is the set positive number, and f (i) is a function value obtained by inputting the value of i into a preset function f. Wherein the preset function f for i can be determined according to the requirements of the actual dimming scenario (e.g. the adjustment speed) and the requirements of the dimming circuit 800 (e.g. the cost). The output voltage of each of the exponential amplifying circuits in the dimming circuit 800 is determined by the input voltage flow of the exponential amplifying circuit and an exponential value (a proportionality coefficient of the exponential amplifying circuit), and the exponential characteristic is accurate.
Specifically, as shown in fig. 9, the preset function f may be f (i) -2(i-1)So that the dimming circuit 800 can realize the preset voltage VREFBase number a, 1 to (2)N-1) ratio of any integer to powerAnd (4) amplification of the coefficient. For example, the dimming circuit 800 may amplify the preset voltage V through the first exponential amplifying circuit 810REFIs amplified to
Figure PCTCN2018109661-APPB-000007
The preset voltage V may be amplified by the second exponential amplifying circuit 810REFIs amplified to
Figure PCTCN2018109661-APPB-000008
The preset voltage V may be amplified by the first and second exponential amplifying circuits 810 and 810REFIs amplified to
Figure PCTCN2018109661-APPB-000009
And so on.
In a specific implementation, the ith exponential amplifying circuit 110 can be implemented by any one of, but not limited to, the following three ways:
mode a, as shown in fig. 10a, the ith exponential amplifying circuit 810 includes a first operational amplifier OP1, a first resistor R21 and a second resistor R22, wherein a non-inverting input terminal of the first operational amplifier OP1 is connected to an output terminal of the ith third switch R < i >, an inverting input terminal of the first operational amplifier OP1 is connected to one end of the first resistor R21 and one end of the second resistor R22, the other end of the first resistor R21 is grounded, and the other end of the second resistor R22 is connected to an output terminal of the first operational amplifier OP 1.
Wherein the content of the first and second substances,
Figure PCTCN2018109661-APPB-000010
R 2iis the resistance value of the second resistor R221iIs the resistance value of the first resistor R21.
Mode B, as shown in fig. 10B, the ith exponential amplifying circuit 810 includes a first operational amplifier OP1, a first resistor R21, a second resistor R22 and a PMOS transistor Q1, and constitutes a source-follower amplifying circuit, wherein an inverting input terminal of the first operational amplifier OP1 is connected to an output terminal of the ith third switch R < i >, a non-inverting input terminal of the first operational amplifier OP1 is connected to one end of the first resistor R21 and one end of the second resistor R22, the other end of the first resistor R21 is grounded, the other end of the second resistor R22 is connected to a drain of the PMOS transistor Q1, an output terminal of the first operational amplifier OP1 is connected to a gate of the PMOS transistor Q1, and a source of the PMOS transistor Q1 is connected to a power supply.
Wherein the content of the first and second substances,
Figure PCTCN2018109661-APPB-000011
R 2iis the resistance value of the second resistor R221iThe PMOS transistor Q1 can also be replaced by a PNP transistor, as shown in fig. 10c, for the resistance of the first resistor R21.
Mode C, as shown in fig. 10d, the ith exponential amplifying circuit 810 includes a first operational amplifier OP1, a first resistor R21, a second resistor R22 and an NMOS transistor Q2, wherein a non-inverting input terminal of the first operational amplifier OP1 is connected to an output terminal of the ith third switch R < i >, an inverting input terminal of the first operational amplifier OP1 is connected to one end of the first resistor R21 and one end of the second resistor R22, the other end of the first resistor R21 is grounded, the other end of the second resistor R22 is connected to a source of the NMOS transistor Q2, an output terminal of the first operational amplifier OP1 is connected to a gate of the NMOS transistor Q2, and a drain of the NMOS transistor Q2 is connected to a power supply.
Wherein the content of the first and second substances,
Figure PCTCN2018109661-APPB-000012
R 2iis the resistance value of the second resistor R221iIs the resistance value of the first resistor R21.
In addition, the NMOS transistor Q2 may be replaced by an NPN transistor, as shown in fig. 10 e.
It should be noted that, in the embodiment of the present application, a specific implementation manner of the ith exponential amplifying circuit 810 is not limited, and the specific implementation manners of the ith exponential amplifying circuit 810 described in the above-mentioned manner a and manner B are merely examples, and any circuit structure capable of implementing the function of the ith exponential amplifying circuit 810 is applicable to the embodiment of the present application.
In one possible embodiment, as shown in fig. 11, the dimming circuit 800 further includes a current-voltage conversion circuit 830, and an input terminal of the current-voltage conversion circuit 830 is used for inputting a preset current IREFThe output terminal of the current-voltage conversion circuit 830 is connected to the ith third switch R<i>And the Nth third switch R<N>The input ends of the two-way valve are connected; the current-voltage conversion circuit 830 is used for converting the preset current IREFIs converted into the preset voltage VREF。
In specific implementation, as shown in fig. 12, the current-voltage conversion circuit 830 includes a third resistor R23, and one end of the third resistor R23 is connected to the ith third switch R<i>And the Nth third switch R<N>Is connected to input the preset current IREFThe other end of the third resistor R23 is grounded.
In one specific embodiment, as shown in fig. 13, the voltage-current conversion circuit 820 includes a second operational amplifier OP2, a fourth resistor R24, an NMOS transistor Q3, and a current mirror M1. A non-inverting input terminal of the second operational amplifier OP2 is connected to an output terminal of the nth exponential amplification circuit 810, an inverting input terminal of the second operational amplifier OP2 and a source of the NMOS transistor are connected to one end of the fourth resistor R24, the other end of the fourth resistor R24 is grounded, a gate of the NMOS transistor Q3 is connected to an output terminal of the second operational amplifier OP2, a drain of the NMOS transistor Q3 is connected to an input terminal of the current mirror M1, an output terminal of the current mirror M1 is connected to a driving circuit of the light source to be dimmed, and a power terminal of the current mirror M1 is connected to a power supply; the input current of the current mirror M1 is opposite in polarity to the output current of the current mirror M1.
The current mirror M1 may be implemented by a triode or a MOS transistor. Further, the current mirror M1 may be used to change the polarity (i.e., the direction of the current) of the current inputted to the current mirror M1, and may also be used to amplify the current inputted to the current mirror M1 in proportion to further amplify the output current of the dimming circuit 800.
Further, when the dimming circuit 800 has the current-voltage conversion circuit 830 shown in fig. 12, the resistance of the third resistor R23 and the resistance of the fourth resistor R24 in the voltage-current conversion circuit 820 satisfy the following formula:
R 3＝M*R 4，
wherein R is3Is the resistance value of the third resistor R23, R4The resistance value of the fourth resistor R24 is M, which is a preset positive number. In this way, the variation of the third resistor R23 and the variation of the fourth resistor R24 caused by the environmental temperature, the processing technique, and the like can be offset, and the precision of the light adjusting circuit 800 can be improved.
In a specific implementation, as shown in fig. 14, the dimming circuit 800 may further include a controller 840, where the controller is connected to control terminals of the ith first switch S < i >, the ith second switch NS < i >, and the ith third switch R < i >, respectively;
the controller 840 is used for controlling the current I according to the target currentLEDAnd the predetermined voltage VREFControls the ith first switch S<i>The ith second switch NS<i>And the ith third switch R<i>The state of (1); the target current is determined according to the target brightness to which the light source to be dimmed needs to be adjusted; when the dimming circuit works, the ith first switch S<i>Is in the state of (a) and the ith second onClose NS<i>In the opposite state, only one of the N third switches is in a conducting state.
Further, when the dimming circuit 800 is operated, since only one of the N third switches is in an on state, if an nth third switch R < N > of the N third switches is turned on, other third switches except for the nth third switch R < N > are all turned off, and the (N-1) th exponential operation circuit 810 does not output a signal, the (N-1) th first switch S < N-1> may be turned on or off, and in order to improve the operating efficiency of the dimming circuit 800, the (N-1) th first switch S < N-1> may be turned off when the nth third switch R < N > is turned on.
For example, the output voltage V of the ith exponential amplifying circuit 810Oi＝a f(i)*V INiWhen the dimming circuit 800 is in operation, if the second third switch R is on<3>Conducting, the other third switch (R)<1>、R<3>And R<4>～R<N>) Off, first switch S<1>And a third first switch S<3>On, the other first switch (S)<2>And S<4>～S<N-1>) Off, first and second switch NS<1>And a third second switch NS<3>Off, the other second switch (NS)<2>And N S<4>～N S<N-1>) Conducting, an input voltage V to said voltage-to-current conversion circuitEXPThe following were used:
V EXP＝V O4＝a f(4)*V IN4＝a f(4)*V O2＝a f(4)+f(2)*V IN2＝a f(6)+f(3)*V REF
when the third switch R <3> is turned on, the second switch S <2> can also be turned off.
In one possible embodiment, as shown in fig. 15, the dimming circuit 800 may further include a decoding circuit 850, an input terminal of the decoding circuit 850 is connected to the controller 840, and an output terminal of the decoding circuit 850 is connected to control terminals of the ith first switch S < i >, the ith second switch NS < i >, and the ith third switch R < i >, respectively.
Wherein the controller is specifically configured to: according to the target current IREFAnd the predetermined voltage VREFTo generate a dimming code. The decoding circuit 850 is used for generating the ith first switch S according to the dimming code<i>The ith second switch NS<i>And the ith third switch R<i>The corresponding control signal.
It should be noted that the operation principle of the decoding circuit 850 is similar to that of the decoding circuit 130, and the specific operation principle of the decoding circuit 850 may refer to the related description of the operation principle of the decoding circuit 130, which is not described herein again.
In addition, when the output voltage V of the ith exponential amplifying circuitOiSatisfied formula VOi＝a f(i)*V INiWherein a 2 and f (i) 2(i-1)The dimming circuit 800 can also implement linear dimming. Specifically, when the dimming circuit 800 operates in the linear dimming mode (i.e., a is 2, f (i) is 2)(i-1)In time), N-1 the first switches are all in off state, N-1 the second switches are all in on state, the ith third switch R<i>And the Nth third switch R<N>State according to the preset current VREFAnd the target current ILEDN of said third switches may be in a conducting state simultaneously.
With the above scheme, the dimming circuit 800 can enable one or more of the N exponential amplification circuits 810 to be cascaded by changing the states of the switches connected between the N exponential amplification circuits 810 in the dimming circuit, so as to quickly couple the preset voltage VREFIs adjusted to the target current I in an exponential amplification modeLEDThe corresponding voltage is used for enabling the brightness of the light source to be dimmed to reach the target brightness, so that the exponential dimming is realized, the realization mode is simple, and the requirement of no light source is metThe dimming circuit is controlled through complex digital operation, and the cost is low.
In addition, since the N exponential amplification circuits 810 are cascaded by a switch, the exponential amplification circuit 810 in the dimming circuit 800 can be according to the target current ILEDIs flexibly combined, and the driving current of the light source to be dimmed is quickly adjusted to the target current ILED。
Based on the above embodiments, the present application further provides an integrated circuit, which includes the dimming circuit 100 described in any one of the above possible embodiments, or the dimming circuit 800 described in any one of the above possible embodiments.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims (21)

  1. A dimming circuit, comprising: the output end of the ith exponential amplification circuit is connected with the input end of an (i + 1) th exponential amplification circuit through an ith first switch, the output end of the Nth exponential amplification circuit is connected with a driving circuit of a light source to be dimmed, the output end of the ith exponential amplification circuit is also connected with the output end of the (i + 1) th exponential amplification circuit through an ith second switch, i is 1,2 and … N, and N is a positive integer;
    the input end of the ith exponential amplification circuit is connected with the ith third switch and used for obtaining preset current through the ith third switch; the ith exponential amplifying circuit is used for amplifying the input current of the ith exponential amplifying circuit.
  2. The dimming circuit of claim 1, wherein the ith exponential amplification circuit has a scaling factor of af(i)Wherein a is a set positive number, f (i) is associated with iAnd (4) function values.
  3. The dimming circuit of claim 2, wherein f (i) 2(i-1)。
  4. The dimming circuit according to claim 2 or 3, wherein the ith exponential amplification circuit comprises a voltage amplification circuit and a voltage-current conversion circuit, the voltage amplification circuit being connected to the voltage-current conversion circuit;
    the voltage amplifying circuit is used for amplifying the voltage IINiIs converted into a first voltage VINiAnd for said VINiAmplifying to obtain a second voltage VOiWherein V isOi＝a f(i)*V INi；
    The voltage-current conversion circuit is used for converting the voltage V into the current VOiIs converted into the IOi。
  5. The dimming circuit of claim 4, wherein the voltage amplification circuit comprises an operational amplifier, a first resistor, and a second resistor; the voltage-current conversion circuit comprises an N-channel metal oxide semiconductor (NMOS) transistor and a current mirror;
    the positive phase input end of the operational amplifier is connected with one end of the first resistor, the inverting input end of the operational amplifier and the source electrode of the NMOS transistor are connected with one end of the second resistor, the inverting input end of the operational amplifier is connected with the grid electrode of the NMOS transistor, the drain electrode of the NMOS transistor is connected with the input end of the current mirror, the output end of the current mirror is connected with the output end of the (i + 1) th exponential amplification circuit, and the power supply end of the current mirror is connected with a power supply; the other end of the first resistor and the other end of the second resistor are both grounded;
    wherein R is2i＝a f(i)*R 1i，R 2iIs the resistance value of the second resistor and is,R 1ithe input current of the current mirror is opposite to the output current of the current mirror in polarity as the resistance value of the first resistor.
  6. The dimming circuit according to any one of claims 1 to 5, further comprising a controller connected to control terminals of the ith first switch, the ith second switch, and the ith third switch, respectively;
    the controller is configured to control states of the ith first switch, the ith second switch, and the ith third switch according to a magnitude of a target current and a magnitude of the preset current;
    the target current is determined according to the target brightness to which the light source to be dimmed needs to be adjusted; when the dimming circuit works, the state of the ith first switch is opposite to that of the ith second switch, and only one of the N third switches is in a conducting state.
  7. The dimming circuit of claim 6, further comprising a decoding circuit, wherein an input terminal of the decoding circuit is connected to the controller, and an output terminal of the decoding circuit is connected to control terminals of the ith first switch, the ith second switch, and the ith third switch, respectively;
    the controller is specifically configured to: generating a dimming code according to the magnitude of the target current and the magnitude of the preset current;
    the decoding circuit is configured to generate control signals corresponding to the ith first switch, the ith second switch, and the ith third switch according to the dimming code.
  8. The dimming circuit of claim 7, wherein the dimming code is an N-bit binary number, wherein a 1 in the dimming code is represented by a first level and a 0 is represented by a second level;
    the decoding circuit is specifically configured to: using the level corresponding to the (i + 1) th bit from the lower bit in the dimming code as a control signal of the ith first switch; performing non-operation on the (i + 1) th bit of the dimming code to obtain a control signal of the ith second switch; using the level corresponding to the jth digit in the dimming code as a control signal of a jth third switch, and generating the second level as control signals of other third switches except the jth third switch;
    wherein, the j-th digit is the first 1 from the low order in the dimming code, j is a positive integer, and j is less than or equal to N; the first level is used for controlling the first switch, the second switch and the third switch to be turned on, and the second level is used for controlling the first switch, the second switch and the third switch to be turned off.
  9. A dimming circuit, comprising: the output end of the ith exponential amplification circuit is connected with the input end of an (i + 1) th exponential amplification circuit through an ith first switch, the output end of the nth exponential amplification circuit is connected with the input end of the voltage-current conversion circuit, the output end of the voltage-current conversion circuit is connected with a driving circuit of a light source to be dimmed, the output end of the ith exponential amplification circuit is also connected with the output end of the (i + 1) th exponential amplification circuit through an ith second switch, and i is 1,2, … N, wherein N is a positive integer;
    the input end of the ith exponential amplification circuit is connected with the ith third switch and used for acquiring a preset voltage through the ith third switch; the ith exponential amplifying circuit is used for amplifying the input voltage of the ith exponential amplifying circuit, and the voltage-current conversion circuit is used for converting the input voltage of the voltage-current conversion circuit into current.
  10. The dimming circuit of claim 9, wherein the i-th exponential amplification circuit has a scaling factor of af(i)A is a set positive number, and f (i) is a function value associated with i.
  11. The dimming circuit of claim 10, wherein f (i) 2(i-1)。
  12. The dimming circuit according to claim 10 or 11, wherein the ith exponential amplification circuit comprises a first operational amplifier, a first resistor, and a second resistor;
    a positive phase input end of the first operational amplifier is connected with an output end of the ith third switch, a negative phase input end of the first operational amplifier is respectively connected with one end of the first resistor and one end of the second resistor, the other end of the first resistor is grounded, and the other end of the second resistor is connected with an output end of the first operational amplifier;
    Figure PCTCN2018109661-APPB-100001
    R 2iis the resistance value, R, of the second resistor1iIs the resistance value of the first resistor.
  13. The dimming circuit of claim 10 or 11, wherein the ith exponential amplification circuit comprises a first operational amplifier, a first resistor, a second resistor, and a P-channel metal-oxide-semiconductor PMOS transistor;
    the inverting input end of the first operational amplifier is connected with the output end of the ith third switch, the non-inverting input end of the first operational amplifier is respectively connected with one end of the first resistor and one end of the second resistor, the other end of the first resistor is grounded, the other end of the second resistor is connected with the drain electrode of the PMOS transistor, the output end of the first operational amplifier is connected with the gate electrode of the PMOS transistor, and the source electrode of the PMOS transistor is connected with the power supply;
    Figure PCTCN2018109661-APPB-100002
    R 2iis the firstResistance value of two resistors, R1iIs the resistance value of the first resistor.
  14. The dimming circuit of any one of claims 9-13, further comprising: the input end of the current-voltage conversion circuit is used for inputting preset current, and the output end of the current-voltage conversion circuit is respectively connected with the input end of the ith third switch and the input end of the Nth third switch;
    the current-voltage conversion circuit is used for converting the preset current into the preset voltage.
  15. The dimming circuit according to claim 14, wherein the current-voltage conversion circuit includes a third resistor, one end of the third resistor is connected to the input terminal of the ith third switch and the input terminal of the nth third switch, respectively, for inputting the preset current, and the other end of the third resistor is grounded.
  16. The dimming circuit according to any one of claims 9 to 14, wherein the voltage-current conversion circuit comprises a second operational amplifier, a fourth resistor, an N-channel metal oxide semiconductor (NMOS) transistor, and a current mirror;
    the positive phase input end of the second operational amplifier is connected with the output end of the Nth exponential amplification circuit, the negative phase input end of the second operational amplifier and the source electrode of the NMOS transistor are connected with one end of the fourth resistor, the other end of the fourth resistor is grounded, the grid electrode of the NMOS transistor is connected with the output end of the second operational amplifier, the drain electrode of the NMOS transistor is connected with the input end of the current mirror, the output end of the current mirror is connected with the driving circuit of the light source to be dimmed, and the power supply end of the current mirror is connected with the power supply; the input current of the current mirror is opposite in polarity to the output current of the current mirror.
  17. The dimming circuit of claim 15, wherein the voltage-to-current conversion circuit comprises a second operational amplifier, a fourth resistor, an N-channel metal oxide semiconductor (NMOS) transistor, and a current mirror;
    the positive phase input end of the second operational amplifier is connected with the output end of the Nth exponential amplification circuit, the negative phase input end of the second operational amplifier and the source electrode of the NMOS transistor are connected with one end of the fourth resistor, the other end of the fourth resistor is grounded, the grid electrode of the NMOS transistor is connected with the output end of the second operational amplifier, the drain electrode of the NMOS transistor is connected with the input end of the current mirror, the output end of the current mirror is connected with the driving circuit of the light source to be dimmed, and the power supply end of the current mirror is connected with the power supply;
    wherein R is3＝M*R 4，R 3Is the resistance value, R, of the third resistor4And the resistance value of the fourth resistor is M, the resistance value of the fourth resistor is a preset positive number, and the polarity of the input current of the current mirror is opposite to that of the output current of the current mirror.
  18. The dimming circuit according to any one of claims 9 to 17, further comprising a controller connected to control terminals of the ith first switch, the ith second switch, and the ith third switch, respectively;
    the controller is used for controlling the states of the ith first switch, the ith second switch and the ith third switch according to the magnitude of target current and the magnitude of the preset voltage;
    the target current is determined according to the target brightness to which the light source to be dimmed needs to be adjusted; when the dimming circuit works, the state of the ith first switch is opposite to that of the ith second switch, and only one of the N third switches is in a conducting state.
  19. The dimming circuit of claim 18, further comprising a decoding circuit, wherein an input terminal of the decoding circuit is connected to the controller, and an output terminal of the decoding circuit is connected to control terminals of the ith first switch, the ith second switch, and the ith third switch, respectively;
    the controller is specifically configured to: the dimming code generates a dimming code according to the magnitude of the target current and the magnitude of the preset voltage;
    the decoding circuit is configured to generate control signals corresponding to the ith first switch, the ith second switch, and the ith third switch according to the dimming code.
  20. The dimming circuit of claim 19, wherein the dimming code is an N-bit binary number, wherein a 1 in the dimming code is represented by a first level and a 0 is represented by a second level;
    the decoding circuit is specifically configured to use a level corresponding to an i +1 th bit from a lower bit in the dimming code as a control signal of the i-th first switch; performing non-operation on the (i + 1) th bit of the dimming code to obtain a control signal of the ith second switch; using the level corresponding to the jth digit in the dimming code as a control signal of a jth third switch, and generating the second level as control signals of other third switches except the jth third switch;
    wherein, the j-th digit is the first 1 from the low order in the dimming code, j is a positive integer, and j is not more than N; the first level is used for controlling the first switch, the second switch and the third switch to be turned on, and the second level is used for controlling the first switch, the second switch and the third switch to be turned off.
  21. An integrated circuit comprising a dimming circuit as claimed in any one of claims 1 to 20.
CN201880098203.5A 2018-10-10 2018-10-10 Dimming circuit and integrated circuit Active CN112823569B (en)

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