CN112819799A - Target defect detection method, device, system, electronic equipment and storage medium - Google Patents
Target defect detection method, device, system, electronic equipment and storage medium Download PDFInfo
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- G06T2207/30148—Semiconductor; IC; Wafer
Abstract
The invention relates to a method for detecting target defects on a wafer, which comprises the steps of carrying out edge extraction on a to-be-detected defect image to obtain an edge graph of at least one to-be-identified target, matching the edge graph with a reference graph prestored in a database, and judging the to-be-identified target as the wafer defect if the matching is unsuccessful. The wafer defect can be identified only after the edge extraction is carried out on the wafer defect image, manual screening is not needed, and the detection efficiency is improved; and when wafer defect identification is carried out, a comparison template image is not required to be provided, and two images are not required to be processed naturally, so that the calculation amount of a computer is reduced, and the calculation efficiency of the computer is improved. Correspondingly, the invention also provides a device and a system for detecting the target defect, electronic equipment and a computer readable storage medium.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method, a device and a system for detecting target defects on a wafer, electronic equipment and a computer readable storage medium.
Background
During the chip manufacturing process, the processing of the wafer by each process flow may result in some undesired structures, which may cause the on-chip circuits to fail, called wafer defects or target defects. Therefore, wafer defect inspection is usually performed after a plurality of critical processes in the chip manufacturing process to monitor the critical processes to ensure their correctness.
Currently, methods for detecting wafer defects in the semiconductor industry include Automatic Optical Inspection (AOI), X-ray Inspection, Scanning Electron Microscope (SEM), Focused Ion Beam (FIB), or Transmission Electron Microscope (TEM). Generally, AOI is adopted to scan the surface of a wafer in a full range to obtain coordinates of suspected defects, and then SEM is used to shoot at a specified position to finally determine whether the position has defects.
The method for determining whether the wafer has defects by using SEM mainly includes two methods: one is to use the layout as a comparison template, namely to detect defects by comparing the difference between the layout and the SEM image; one is to use the SEM image as a comparison template, i.e. to obtain multiple SEM images with the same pattern by multiple scanning and averaging to obtain the SEM image template. For the first, because the layout and the SEM image cannot be directly compared, a model needs to be established in advance, the layout is converted into a standard SEM image template, and then the SEM image to be detected is compared with the SEM image template, which increases the amount of computation and power consumption of the computer. For the second, since a plurality of SEM images are required to obtain the SEM template on average, the workload is increased, and the calculation amount and power consumption of the computer are also increased.
In both of the above two ways, the SEM image to be detected needs to be compared with the template image (i.e. the image without defects), and the acquisition of the template image will increase the workload and the calculation amount and power consumption of the device. Therefore, there is a need for a method for detecting defects on a wafer based on an image to be detected without using an image template.
Disclosure of Invention
To partially solve the above problems, the present invention provides a method and apparatus for detecting a target defect on a wafer, a system, an electronic device, and a storage medium.
In a first aspect of the present invention, a method for detecting a target defect on a wafer is provided, which comprises the steps of:
acquiring at least one pre-collected defect image to be detected;
performing edge extraction on the to-be-detected defect image to obtain an edge graph corresponding to each to-be-identified target;
matching the edge graph of the target to be identified with a reference graph prestored in a database, and if the matching is unsuccessful, judging the target to be identified corresponding to the edge graph as a target defect;
the reference pattern comprises an edge pattern corresponding to an industry general circuit and a pre-defined edge pattern.
In an exemplary embodiment of the present invention, the step of dividing the reference pattern in the database into a plurality of matching priorities in advance, and correspondingly matching the target to be recognized with the reference pattern specifically includes:
and starting from the reference pattern which is marked as the first matching priority in advance, matching the edge pattern of the target to be recognized with the reference pattern with the corresponding priority step by step, and matching the target to be recognized with the reference pattern which is marked as the next matching priority in advance until the last bit matches the priority when the edge pattern of the target to be recognized is not matched with the reference pattern with the corresponding priority.
In an exemplary embodiment of the present invention, before the step of performing the edge extraction, the method further includes the steps of: and preprocessing the image of the defect to be detected so as to improve the resolution of the image of the defect to be detected.
In an exemplary embodiment of the present invention, the step of preprocessing the image of the defect to be detected specifically includes: and carrying out image sharpening on the to-be-detected defect image.
In an exemplary embodiment of the present invention, after the step of determining the edge pattern to be identified as a wafer defect, the method further includes the steps of:
correcting the target defect appointed by the user into a circuit graph according to a correction operation instruction input by the user;
the correcting operation instruction comprises: and correcting the target to be identified which is specified by the user and is currently determined as the target defect into a control instruction of the circuit.
In an exemplary embodiment of the invention, the method further comprises the steps of: and updating the target defect specified by the user into the database and using the target defect as a new reference graph.
In an exemplary embodiment of the present invention, the edge pattern includes a regular pattern and an irregular pattern; and/or the reference graphs are regular graphs.
In a second aspect of the present invention, an apparatus for detecting a target defect on a wafer is provided, which includes: the database is used for prestoring a plurality of reference graphs; the reference graph comprises an edge graph corresponding to an industry general circuit and/or an edge graph customized by a user; the data acquisition module is used for acquiring a pre-collected defect image to be detected; the image processing module is used for performing edge extraction on the to-be-detected defect image acquired by the data acquisition module to obtain an edge graph of each to-be-identified target on the wafer; and the defect detection module is used for matching the edge graph obtained by the image processing module with a reference graph prestored in a database, and if the edge graph is not matched with the reference graph, judging the target to be identified corresponding to the edge graph as a target defect.
In an exemplary embodiment of the present invention, the reference pattern in the database is pre-divided into a plurality of matching priorities, and accordingly, the defect detection module is specifically configured to, starting from the reference pattern pre-marked as a first matching priority, match the edge pattern corresponding to the target to be identified with the reference pattern of the corresponding priority step by step, and when the corresponding reference pattern is not matched, match the edge pattern with the reference pattern of the next matching priority until the last matching priority; and when the corresponding reference pattern is not matched in the last bit priority, judging the target to be identified as the target defect.
In an exemplary embodiment of the invention, the apparatus further comprises: and the image preprocessing module is used for preprocessing the defect image to be detected acquired by the data acquisition module and then sending the preprocessed defect image to be detected to the image processing module for edge extraction.
In an exemplary embodiment of the present invention, the image preprocessing module is specifically configured to perform image sharpening on the to-be-detected defect image.
In an exemplary embodiment of the invention, the apparatus further comprises: the input module is used for inputting a corresponding operation instruction by a user; the operation instruction comprises a control instruction for correcting the target to be identified, which is specified by the user and is currently determined as the target defect, into a circuit; and the correcting module is used for correcting the target to be recognized appointed by the user into a circuit according to the control instruction.
In an exemplary embodiment of the invention, the apparatus further comprises: and the database updating module is used for responding to the operation instruction and adding the edge graph corresponding to the target to be identified, which is specified by the user, into the database to be used as a new reference graph.
In a third aspect of the present invention, a wafer defect detecting system is provided, which includes: the wafer defect image acquisition device is in data communication with the wafer defect detection device according to any one of the wafer defect detection devices.
In an exemplary embodiment of the invention, the wafer defect image collecting device is a scanning electron microscope.
A fourth aspect of the present invention is to provide an electronic device, comprising at least one processor, at least one memory, a communication interface and a bus; the processor, the memory and the communication interface complete mutual communication through the bus; the memory is used for storing a program for executing the method; the processor is configured to execute programs stored in the memory.
A fifth aspect of the present invention provides a computer-readable storage medium, storing a computer program, which, when executed by a processor, controls an apparatus in which the storage medium is located to perform any of the above method steps.
Has the advantages that:
according to the detection method, the device and the system, the wafer defect can be identified only after the edge of the wafer defect image is extracted, manual screening is not needed, and the detection efficiency is improved; and when wafer defect identification is carried out, a comparison template image is not required to be provided, and two images are not required to be processed naturally, so that the calculation amount of a computer is reduced, and the calculation efficiency of the computer is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale. It is obvious that the drawings in the following description are some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive exercise.
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a method for detecting a target defect on a wafer according to an exemplary embodiment of the present invention;
FIG. 2 is a schematic flow chart diagram illustrating an embodiment of a method for detecting a target defect on a wafer in accordance with yet another exemplary embodiment of the present invention;
FIG. 3 is a block diagram of an embodiment of an apparatus for detecting a target defect on a wafer in accordance with an exemplary embodiment of the present invention;
fig. 4 is a block diagram of an electronic device according to an exemplary embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Herein, suffixes such as "module", "part", or "unit" used to denote elements are used only for facilitating the description of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.
The term is defined as:
defect pattern: generally, various circuits, such as a regulator circuit or an amplifier circuit, are integrated on a wafer, and when the wafer integrated with the various circuits is scanned or photographed on a corresponding inspection apparatus, a wafer pattern is obtained. During the fabrication process of the integrated circuit, various defects are inevitably formed on the wafer, and therefore, the wafer image is also called a defect image. The image formed on the defect image by each circuit integrated on the wafer is a circuit image, and correspondingly, the image formed on the defect image by each defect on the wafer is a defect image, and the defect image (i.e. the object to be identified) and the circuit image (i.e. the object to be identified) are respectively the sameThe edge profile/edge shape is an edge pattern。
Reference pattern: the term "reference pattern" as used herein refers to an edge pattern, such as a square, a rectangle, a rounded rectangle, an L-shape, an H-shape, etc., corresponding to each of various circuits, which is pre-entered into a database by a worker, and may be used as a reference object for identifying a target defect or a comparison object in performing defect detection. The reference patterns in the database include edge patterns (predefined by those skilled in the art or experts) corresponding to general circuits (such as voltage regulator circuits, amplifier circuits, etc.) in the integrated circuit industry, edge patterns customized by users, and respective characteristic parameters of each reference pattern, such as corresponding circuit name or circuit type, size, etc.
Example one
Referring to fig. 1, a schematic flowchart of an embodiment of a method for detecting a target defect on a wafer according to an exemplary embodiment of the present invention is shown, and specifically, the method includes the steps of:
s101, acquiring at least one pre-collected defect image to be detected.
In some embodiments, the entire wafer may be scanned or photographed by an image capture device, for example, by scanning the entire wafer through an SEM to obtain an image of the defect to be detected, and then acquiring the image of the defect to be detected from the SEM. Of course, other devices may be used to acquire the wafer defect image, such as AOI and TEM.
And S103, performing edge extraction on the to-be-detected defect image acquired in the step S101 to obtain an edge graph corresponding to each to-be-identified target in the wafer.
In some embodiments, before performing the edge extraction, the to-be-detected defect image needs to be preprocessed to improve the resolution of the to-be-detected defect image, so as to improve the accuracy of the edge extraction, for example, the to-be-detected defect image is sharpened to increase edges; or image enhancement such as image binarization processing and the like is performed.
In some embodiments, the edge extraction refers to extracting edge patterns of all objects to be identified appearing in a defect map to be detected, and specifically, the edge extraction may be performed by using methods such as a Sobel operator, a Laplacian operator, a Canny operator, and the like, so that the obtained edge patterns include edge patterns corresponding to each circuit on a wafer and edge patterns corresponding to each defect on the wafer.
Of course, the extracted feature parameters include not only the edge pattern itself, but also the feature parameters of the edge pattern, such as a corresponding defect number (which may be automatically generated when the defect image is obtained, or may be pre-programmed by a worker), and a position/coordinate, a size, and the like of the edge pattern in the defect image. Generally, the extracted edge patterns include regular patterns (i.e., regularly shaped patterns such as squares, rectangles, etc.) and irregular patterns (i.e., irregularly shaped patterns).
And S105, matching the edge graph obtained in the step S103 with a reference graph prestored in a database, if the edge graph is matched with the reference graph, executing the step S107, and otherwise, executing the step S109.
In some embodiments, the defect detection is performed in the subsequent steps by constructing a database in advance to store the edge patterns corresponding to various common circuits known in the industry, which are entered by experts or technicians in the field, as the reference pattern.
Due to the normative nature of integrated circuit design, the edge patterns of the circuit are well-defined and known to those skilled in the art, and are regular patterns, such as square, rectangular, rounded rectangular, L-shaped, H-shaped, etc. That is, the reference pattern in the database includes regular edge patterns corresponding to various circuits.
Furthermore, the user can customize some edge graphs in the database according to the specific circuit designed by the user. As such, the database may include edge graphics for industry-generic circuits, as well as user-customized edge graphics.
Further, the user may mark the priority of each reference pattern in the database according to the actual situation in advance, so that when defect identification is performed, starting from the reference pattern marked as the first matching priority, the edge pattern of the target to be identified is matched with each reference pattern of each priority one by one, if the corresponding reference pattern is matched, the edge pattern is not matched with the reference pattern of the next priority, if the corresponding reference pattern is not matched, the edge pattern is matched with the reference pattern of the next priority until the edge pattern is marked as the reference pattern of the last matching priority, and if the corresponding reference pattern is not matched in the priority of the last matching, the edge pattern is determined as the target defect.
In a specific embodiment, the edge graph corresponding to the circuit frequently used by the user is marked as a first matching priority, the edge graph defined by the user is marked as a second matching priority, and the rest is a third matching priority, when the method is specifically implemented, the edge graph of the target to be identified is matched with the reference graph of the first matching priority, and if the corresponding reference graph is matched, the target to be identified is determined as the circuit; if the corresponding reference pattern is not matched, matching the target to be recognized with the reference pattern with the second matching priority, and if the corresponding reference pattern is matched, judging the target to be recognized as the circuit; if the corresponding reference pattern is not matched, matching the target to be recognized with the reference pattern with the third matching priority, and correspondingly, if the corresponding reference pattern is matched, judging the target to be recognized as the circuit; and if the corresponding reference pattern is not matched, judging the target to be identified as the target defect.
In some embodiments, matching the target to be recognized with the reference pattern refers to comparing a plurality of edge patterns obtained by edge extraction with the reference pattern in the database, and if the shapes are the same and the sizes of the patterns are the same or close, the two patterns are considered to be matched, otherwise, the two patterns are considered to be not matched.
Further, in order to improve the accuracy of the detection, it is necessary to ensure that the edge pattern in the database is consistent or nearly the same as the edge profile of the circuit image formed by each integrated circuit on the wafer in the wafer image.
And S107, determining the target to be identified as a circuit, and ending.
In some embodiments, if the corresponding reference pattern is matched in the database, it indicates that the target to be identified in the wafer is actually a circuit, and therefore, the edge pattern in the wafer image thereof can be matched to the corresponding reference pattern.
And S109, judging the target to be identified as a target defect, and ending.
In some embodiments, if the corresponding reference pattern is not matched in the database, it indicates that the defect formed in the wafer during the actual generation process of the target to be identified is a defect, and therefore, the edge pattern in the wafer image cannot find the corresponding reference pattern in the database.
In other embodiments, when a part of circuits integrated on a wafer is a new circuit designed by a user (i.e. not an industry-universal circuit) and the user does not add an edge pattern of a circuit image corresponding to the new circuit to the database as a reference pattern, the step S105 is executed, since the corresponding reference pattern is not matched in the database, the part of circuits is determined as a target defect, and therefore, in order to avoid this phenomenon, referring to fig. 2, the detection method according to an exemplary embodiment of the present invention further includes the steps of:
and S111, in response to the operation instruction of the user, correcting the target defect specified by the user into a circuit pattern, and adding the circuit pattern into the database to serve as a new reference pattern.
In some embodiments, the operation instruction refers to a control instruction input by an input device to correct the target to be identified (i.e., the target defect specified by the user) which is currently determined as the target defect by mistake as the circuit when the user reviews and finds that part of the target defect obtained in step S109 is actually the circuit. Of course, some custom parameters input by the user may also be included, such as the position/coordinates of the edge pattern, the name of the corresponding circuit, or a shape description.
In other embodiments, when the user inputs an operation instruction indicating that the specified target defect corresponding edge pattern is added as a new reference pattern to the database update database, the edge pattern of the target to be identified (actually, the circuit) currently determined as the target defect is added as the new reference pattern to the database.
Example two
Fig. 3 is a schematic structural diagram of a wafer defect inspection apparatus according to an exemplary embodiment of the invention. Specifically, the wafer defect detecting apparatus includes:
a database 10 for prestoring a plurality of reference patterns;
the data acquisition module 11 is used for acquiring a pre-collected defect image to be detected;
the image processing module 12 is configured to perform edge extraction on the to-be-detected defect image acquired by the data acquisition module 11 to obtain an edge graph corresponding to each to-be-identified target on the wafer;
the defect detection module 13 is configured to match an edge pattern of each target to be identified in the image processing module 12 with a pre-stored reference pattern; if not, judging the corresponding target to be identified as a target defect; and if so, judging the target to be identified as the circuit.
In some embodiments, the reference patterns in the database include edge profiles/edge patterns of circuit patterns obtained after scanning of various industry-common circuits pre-entered by experts or technicians in the field, and edge patterns customized by users.
In some embodiments, the data acquiring module 11 may perform data communication with various defect image acquiring devices, such as an SEM, so that a defect image to be detected acquired in advance can be directly acquired from the defect image acquiring device.
In some embodiments, the wafer defect detecting apparatus further includes: the image preprocessing module 14 is configured to preprocess the defect image to be detected before the image processing module 13 performs edge extraction on the defect image to be detected, so as to improve the resolution of the defect image to be detected, and then send the preprocessed defect image to be detected to the image processing module 13 for edge extraction. Specifically, the image preprocessing module 14 performs edge sharpening, image enhancement (such as image binarization), or the like on the defect image to be detected.
In other embodiments, referring to fig. 3, the wafer defect detecting apparatus further includes:
the input module 15 is used for inputting corresponding operation instructions by a user;
a correction module 16 for correcting a specified target defect to a circuit when the user inputs an operation instruction indicating that the target defect is corrected to the circuit through the input module 15;
and the database updating module 17 is used for updating the edge graph corresponding to the specified target defect into the database as a new reference graph when the correcting module 16 performs updating according to the operation instruction input by the user.
EXAMPLE III
In a third aspect of the present invention, there is provided a target defect detection system, comprising: defect image acquisition equipment and the target defect detection device of the embodiment. The defect image acquisition equipment can adopt various existing acquisition equipment such as SEM.
In a fourth aspect of the invention, an electronic device is provided, comprising a memory 502, a processor 501 and a computer program stored on the memory 502 and executable on the processor 501, wherein the processor 501 executes the program to implement the steps of the method as described above. For convenience of explanation, only the parts related to the embodiments of the present specification are shown, and specific technical details are not disclosed, so that reference is made to the method parts of the embodiments of the present specification. The electronic device may be any electronic device including various electronic devices, a PC computer, a network cloud server, and even a mobile phone, a tablet computer, a PDA (Personal Digital Assistant), a POS (Point of Sales), a vehicle-mounted computer, a desktop computer, and the like.
Specifically, the electronic device shown in fig. 4 in connection with the solution provided by the embodiments of the present description constitutes a block diagram, and the bus 500 may include any number of interconnected buses and bridges that link together various circuits including one or more processors represented by the processor 501 and a memory represented by the memory 502. The bus 500 may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A communication interface 503 provides an interface between the bus 500 and the receiver and/or transmitter 504, and the receiver and/or transmitter 504 may be a separate independent receiver or transmitter or may be the same element, such as a transceiver, providing a means for communicating with various other apparatus over a transmission medium. The processor 501 is responsible for managing the bus 500 and general processing, and the memory 502 may be used for storing data used by the processor 501 in performing operations.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a computer-readable storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, or a network device, etc.) to execute the above method according to the embodiments of the present disclosure.
The computer readable storage medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable storage medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations for the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).
The computer readable medium carries one or more programs which, when executed by a device, cause the computer readable medium to perform the functions of: acquiring at least one pre-collected defect image to be detected; performing edge extraction on the to-be-detected defect image to obtain an edge graph of each to-be-identified target; and matching the edge graph with a reference graph prestored in a database, and judging the target to be identified as a target defect if the matching is unsuccessful.
Those skilled in the art will appreciate that the modules described above may be distributed in the apparatus according to the description of the embodiments, or may be modified accordingly in one or more apparatuses unique from the embodiments. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a computer terminal (such as a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of detecting a target defect on a wafer, comprising the steps of:
acquiring at least one pre-collected defect image to be detected;
performing edge extraction on the to-be-detected defect image to obtain an edge graph corresponding to each to-be-identified target;
matching the edge graph of the target to be identified with a reference graph prestored in a database, and if the matching is unsuccessful, judging the target to be identified corresponding to the edge graph as a target defect;
the reference pattern comprises an edge pattern corresponding to an industry general circuit and a pre-defined edge pattern.
2. The method according to claim 1, wherein the reference pattern in the database is pre-divided into a plurality of matching priorities, and accordingly, the step of matching the target to be recognized with the reference pattern specifically comprises:
and starting from the reference pattern which is marked as the first matching priority in advance, matching the edge pattern of the target to be recognized with the reference pattern with the corresponding priority step by step, and matching the target to be recognized with the reference pattern which is marked as the next matching priority in advance until the last bit matches the priority when the edge pattern of the target to be recognized is not matched with the reference pattern with the corresponding priority.
3. The method of claim 2, wherein the step of performing edge extraction is preceded by the step of: and preprocessing the image of the defect to be detected so as to improve the resolution of the image of the defect to be detected.
4. The method according to claim 3, wherein the step of preprocessing the image of the defect to be detected comprises in particular: and carrying out image sharpening on the to-be-detected defect image.
5. The method according to claim 1, wherein after the step of determining the edge pattern to be identified as a wafer defect, further comprising the steps of:
correcting the target defect appointed by the user into a circuit graph according to a correction operation instruction input by the user;
the correcting operation instruction comprises: and correcting the target to be identified which is specified by the user and is currently determined as the target defect into a control instruction of the circuit.
6. The method of claim 5, further comprising the step of: and updating the target defect specified by the user into the database and using the target defect as a new reference graph.
7. An apparatus for detecting a target defect on a wafer, comprising:
the database is used for prestoring a plurality of reference graphs; the reference graph comprises an edge graph corresponding to an industry general circuit and/or an edge graph customized by a user;
the data acquisition module is used for acquiring a pre-collected defect image to be detected;
the image processing module is used for performing edge extraction on the to-be-detected defect image acquired by the data acquisition module to obtain an edge graph of each to-be-identified target on the wafer;
and the defect detection module is used for matching the edge graph obtained by the image processing module with a reference graph prestored in a database, and if the edge graph is not matched with the reference graph, judging the target to be identified corresponding to the edge graph as a target defect.
8. A wafer defect detection system, comprising: a wafer defect image acquisition device in data communication with the wafer defect detection device, and the wafer defect detection device of claim 7.
9. An electronic device comprising at least one processor, at least one memory, a communication interface, and a bus; the processor, the memory and the communication interface complete mutual communication through the bus;
the memory is used for storing a program for executing the method of any one of claims 1 to 6;
the processor is configured to execute programs stored in the memory.
10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, controls an apparatus of the storage medium to carry out the steps of the method according to any one of claims 1 to 6.
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