CN112817527B - Power-down data storage method, singlechip and computer-readable storage medium - Google Patents
Power-down data storage method, singlechip and computer-readable storage medium Download PDFInfo
- Publication number
- CN112817527B CN112817527B CN202110078948.9A CN202110078948A CN112817527B CN 112817527 B CN112817527 B CN 112817527B CN 202110078948 A CN202110078948 A CN 202110078948A CN 112817527 B CN112817527 B CN 112817527B
- Authority
- CN
- China
- Prior art keywords
- sector
- data area
- data
- area
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000013500 data storage Methods 0.000 title claims abstract description 41
- 238000004590 computer program Methods 0.000 claims description 6
- 230000002035 prolonged effect Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 238000012827 research and development Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The application discloses a power-down data storage method, a singlechip and a computer-readable storage medium, wherein the power-down data storage method comprises the following steps: dividing a storage module to obtain a first sector and a second sector; dividing the first sector and the second sector into a plurality of data areas; each data area comprises a writing area for writing data and a full area for writing data; receiving a power-down signal; determining a target write data area from the write area according to the power-down signal; wherein the target write data area is one of the write areas; and writing the backup data into the target writing data area, modifying the flag bit of the target writing data area, erasing the sector once without storing data once, and erasing the sector until all the data areas in the sector are fully stored, thereby prolonging the service life of the F l ash memory of the singlechip.
Description
Technical Field
The application relates to the technical field of data reading and writing, in particular to a power-down data storage method, a singlechip and a computer readable storage medium.
Background
In the singlechip system, user data may change in different time along with different application scenes, and the singlechip system is required to store the changed data in time. At present, when the singlechip uses a Flash nonvolatile medium for data storage, the power supply condition of the equipment can be judged by monitoring the power supply state, when power failure occurs, the power consumption of the singlechip equipment is reduced to the minimum, and the microcontroller is maintained to work for a short period of time by means of a capacitor so as to store user data in a RAM (random access memory) into the Flash. The step of storing data in Flash generally includes the steps of first reading data in RAM memory to find a sector stored in Flash, second erasing the sector of Flash, and third writing data to be stored from RAM into the sector of Flash. When writing data, the original whole data of the target sector needing to be written with the data must be erased before the data can be written. Therefore, when only a few bytes of data need to be written, the whole sector can be erased, the size of the sector is different from 16KB to 128KB, but the erasing and writing times of FLASH are limited, generally more than ten thousand times, and the FLASH memory of the singlechip is prolonged by repeated erasing for many times.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides a power-down data storage method, a singlechip and a computer-readable storage medium, and the service life of a Flash memory of the singlechip is prolonged.
In a first aspect, an embodiment of the present application provides a power-down data storage method, including:
Dividing a storage module to obtain a first sector and a second sector;
Dividing the first sector and the second sector into a plurality of data areas; each data area comprises a writing area for writing data and a full area for writing data;
Receiving a power-down signal;
determining a target write data area from the write area according to the power-down signal; wherein the target write data area is one of the write areas;
And writing the backup data into the target writing data area, and modifying the flag bit of the target writing data area.
The power-down data storage method according to the embodiment of the first aspect of the application has at least the following beneficial effects: the Flash memory is divided into a first sector and a second sector which are used for data storage, the first sector and the second sector are divided into a plurality of data areas, the two sectors can ensure that one correct data is reserved in the other sector when one sector is erased, the two sectors can play a role in backup protection, the error deletion of the correct data when the sectors are erased is avoided, each data area is provided with the identification of written data and unwritten data, the backup data is written into the unwritten data area in the first sector or the second sector when the power is turned off each time, mark change is made on the written data area, one sector can store a plurality of data in different data areas, the Flash space utilization rate is improved, the sectors are erased once without storing the data, the sectors are erased until all the data areas in the sectors are full, and the service life of the Flash memory of the singlechip is prolonged.
According to some embodiments of the first aspect of the present application, the determining a target write data area from the write area according to the power-down signal includes: determining a first lowest data area in the writing area of the first sector and a second lowest data area in the writing area of the second sector according to the power-down signal; and determining the target writing data area according to the first lowest data area and the second lowest data area.
According to some embodiments of the first aspect of the present application, the determining the target write data area according to the first lowest data area and the second lowest data area includes: judging the size relation between the first lowest data area and the second lowest data area, and if the first lowest data area is lower than or equal to the second lowest data area, setting the first lowest data area as the target writing data area; and if the first lowest data area is higher than the second lowest data area, setting the second lowest data area as the target writing data area.
According to some embodiments of the first aspect of the present application, the determining the determination target writing data area from the writing area according to the power-down signal further includes: determining storage states of the first sector and the second sector; the storage state comprises a full storage state and an unfilled storage state; if the first sector and the second sector are in a full state and the second sector comprises correct data, the first sector is erased and the lowest data area of the first sector is set as the target writing data area; and if the first sector and the second sector are in a full state and the second sector does not comprise correct data, the second sector is erased, the highest data area of the second sector is set as the target writing data area, and the non-highest data area of the second sector is set as a full area.
According to some embodiments of the first aspect of the present application, the determining the determination target writing data area from the writing area according to the power-down signal further includes: if the second sector is in a full state and the first sector is in an unfilled state and the first sector comprises correct data, the second sector is erased and the lowest data area of the second sector is set as the target writing data area; and if the second sector is in an unfilled state and the first sector does not comprise correct data, the first sector is erased and the lowest data area of the first sector is set as the target writing data area.
According to some embodiments of the first aspect of the application, further comprising: inquiring the latest correct data area in the full area of the first sector and the second sector; and updating the data of the latest correct data area into a memory.
According to some embodiments of the first aspect of the present application, the querying the latest correct data area in the full area of the first sector and the second sector includes: querying and checking all full areas of the first sector with correct data, and determining a first highest data area in the full areas of the first sector; and inquiring and checking all full areas of the second sector with correct data, and determining a second highest data area in the full areas of the second sector.
According to some embodiments of the first aspect of the present application, the updating the data of the latest correct data area into the memory includes: judging the size relation between the first highest data area and the second highest data area, and if the second highest data area is higher than or equal to the first highest data area, updating the data of the second highest data area into a memory; and if the second highest data area is lower than the first highest data area, updating the data of the first highest data area into a memory.
In a second aspect, an embodiment of the present application provides a single chip microcomputer, including: a processor, a memory and a computer program stored in the memory and executable on the processor, wherein the processor implements the power-down data storage method according to any one of the embodiments of the first aspect of the application when the computer program is executed.
In a third aspect, an embodiment of the present application provides a computer readable storage medium, where computer executable instructions are stored, where the computer executable instructions are configured to cause a computer to perform the power-down data storage method according to any one of the embodiments of the first aspect of the present application.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
Additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a flow chart of a method for power down data storage provided by one embodiment of the application;
FIG. 2 is a flow chart of a method for power down data storage provided in another embodiment of the application;
FIG. 3 is a flow chart of a method for power down data storage provided by another embodiment of the present application;
FIG. 4 is a flow chart of a method for power down data storage provided by another embodiment of the present application;
FIG. 5 is a flow chart of a method for power down data storage provided in another embodiment of the present application;
FIG. 6 is a flow chart of a method for power down data storage provided by another embodiment of the present application;
FIG. 7 is a flow chart of a method for power down data storage provided by another embodiment of the present application;
FIG. 8 is a flow chart of a method for power down data storage provided by another embodiment of the present application;
fig. 9 is a schematic structural diagram of a single chip microcomputer according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
In the description of the present application, the description of the first and second is only for the purpose of distinguishing technical features, and should not be construed as indicating or implying relative importance or implying the number of technical features indicated or the precedence of the technical features indicated.
Embodiments of the present invention will be further described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a flowchart of a power-down data storage method according to an embodiment of the present application. The power-down data storage method includes, but is not limited to, step S110, step S120, step S130, step S140, and step S150.
Step S110, dividing a storage module to obtain a first sector and a second sector;
Step S120, dividing the first sector and the second sector into a plurality of data areas; each data area includes a writing area for writing data and a full area where data has been written;
step S130, receiving a power-down signal;
Step S140, determining a target writing data area from the writing area according to the power-down signal; wherein the target write data area is one of the write areas.
Step S150, the backup data is written into the target writing data area, and the flag bit of the target writing data area is modified.
It should be noted that, when the backup data is written into the writing area so that the data area has the backup data, the area is a full data area of the written data.
It can be understood that the Flash memory is reserved with the first sector and the second sector for data storage, the first sector and the second sector are divided into a plurality of data areas, two sectors can ensure that one sector still has a correct data when one sector is erased, the two sectors can play a role of backup protection, the correct data are prevented from being deleted by mistake when the sectors are erased, each data area is provided with the identifications of written data and unwritten data, the backup data are written into the unwritten data area in the first sector or the second sector when the power is turned off each time, the written data areas are subjected to sign change, one sector can store a plurality of data in different data areas, the Flash space utilization rate is improved, the sectors are erased once without storing data, the sectors are erased until all the data areas in the sectors are fully stored, and the service life of the Flash memory of the singlechip is prolonged.
Specifically, for example, the Flash memory is provided with a first sector and a second sector for power-down backup data storage, the storage size of the first sector and the second sector is 128KB, the first sector and the second sector are equally divided into 8 data areas, the storage size of each data area is 16KB, a specific byte in each data area is used as a data flag bit, 1 represents unwritten, 0 represents written, each data area can store data smaller than 16KB, when a power-down signal is received, the singlechip system detects the data areas with flag bits of 1 in the first sector and the second sector and determines the data areas as determined target writing data areas, the data is written into the determined target writing data areas, after the data is written into the determined target writing data areas, the flag bits are rewritten from 1 to 0, only one data bit of one sector is selected for each writing, and Flash is erased after 8 data bits of one sector are written, so that the Flash is improved in utilization ratio of the Flash memory is improved, the time of erasing is prolonged, and the use of the time of the singlechip is prolonged.
Referring to fig. 2, fig. 2 is a flowchart of a power-down data storage method according to another embodiment of the present application, and step S140 may include, but is not limited to, the following steps:
step S210: a first lowest data area in a write area of the first sector and a second lowest data area in a write area of the second sector are determined based on the power down signal.
Specifically, for example, when the flag bit of the first sector is detected to be written as binary "11111100", the third to eighth data areas in the first sector are data areas where no data is written, wherein the third data area is the first lowest data area, and for example, when the flag bit of the second sector is detected to be written as binary "11111110", the second to eighth data areas in the second sector are data areas where no data is written, wherein the second data area is the second lowest data area.
Step S220: and determining a target writing data area according to the first lowest data area and the second lowest data area.
Referring to fig. 3, fig. 3 is a flowchart of a power-down data storage method according to another embodiment of the present application, and step S220 may include, but is not limited to, the following steps:
In step S310, a size relationship between the first lowest data area and the second lowest data area is determined.
In step S320, if the first lowest data area is lower than or equal to the second lowest data area, the first lowest data area is set as the target writing data area.
Specifically, for example, when the first lowest data area is the third data area, the second lowest data area is also the third data area, and the first lowest data area is equal to the second lowest data area, the target writing data area is the third data area of the first sector, that is, the position of the next writing of data is the third data area of the first sector.
In step S330, if the first lowest data area is higher than the second lowest data area, the second lowest data area is set as the target writing data area.
Specifically, for example, when the first lowest data area is the third data area, the second lowest data area is also the second data area, and the first lowest data area is higher than the second lowest data area, the target writing data area is the second data area of the second sector, that is, the position of the next data writing is the second data area of the second sector.
It will be appreciated that the target write data area is always written from the lower data area and always written preferentially to the first sector, so that the two sectors can be written alternately from the lower data area.
Referring to fig. 4, fig. 4 is a flowchart of a power-down data storage method according to another embodiment of the present application, and step S220 may include, but is not limited to, the following steps:
step S410: determining the storage states of the first sector and the second sector; the storage states include a full state and an unfilled state.
Step S420: if the first sector and the second sector are both full and the second sector includes correct data, the first sector is erased and the lowest data area of the first sector is set as the target write data area.
Step S430: and if the first sector and the second sector are in a full state and the second sector does not comprise correct data, the second sector is erased, the highest data area of the second sector is set as a target writing data area, and the non-highest data area of the second sector is set as a full area.
When the data is stored, the full state refers to that all data is the full area, namely the full data is stored.
Specifically, writing into the first sector is always prioritized during writing, after writing 16 times, the flag bit of the first sector becomes binary "00000000", and similarly, the flag bit of the second sector also becomes binary "00000000", at this time, it is required to check whether at least one correct data exists in the second sector, if the correct data exists, the first sector is erased, and the lowest data area of the first sector is set as the target writing data area, that is, the first data area of the first sector is set as the target writing data area, and the flag bit of the first sector becomes binary "11111111"; if the correct data does not exist in the second sector, the second sector is erased, the highest data area of the second sector is set as a writing area, other data areas are set as full areas, the highest data area of the second sector is set as a target writing data area, namely, the eighth data area of the second sector is set as a target writing data area, the flag bit of the second sector becomes binary '10000000', the next data is ensured to be written into the eighth data area of the second sector, and the binary numbers of the first sector and the second sector are both '00000000' in the next flag bit detection.
Referring to fig. 5, fig. 5 is a flowchart of a power-down data storage method according to another embodiment of the present application, and step S220 may include, but is not limited to, the following steps:
In step S510, if the second sector is in the full state and the first sector is in the unfilled state and the first sector includes correct data, the second sector is erased and the lowest data area of the second sector is set as the target writing data area.
In step S520, if the second sector is not full and the first sector does not include correct data, the first sector is erased and the lowest data area of the first sector is set as the target writing data area.
Specifically, after 16 times of data are written, the flag bit of the first sector becomes binary "00000000", likewise, the flag bit of the second sector also becomes binary "00000000", at least one part of correct data exists in the second sector, the first sector is erased, the lowest data area of the first sector is set as a target writing data area, namely the first data area of the first sector is set as a target writing data area, after the data are written in the first data area of the first sector, the flag bit of the first sector becomes binary "11111110", the flag bit of the second sector is binary "00000000", when the second sector is detected, and the writing area exists in the first sector, the data of the lowest data area of the first sector is correct, the second sector is erased, the lowest data area of the second sector is set as a target writing data area, namely the first data area of the second sector is set as a target writing data area, and the flag bit of the second sector becomes binary "11111", so as to achieve the purposes of alternately writing the first sector and the second sector; when the data area of the second sector is detected to be the full area, the writing area of the first sector is detected, the data error of the lowest bit data area of the first sector is detected, the first sector is erased, the lowest data area of the first sector is set as a target writing data area, namely the first data area of the first sector is set as a target writing data area, the flag bit of the first sector becomes binary '11111111', and at least one piece of correct data of the Flash memory is ensured to be remained in the second sector.
It will be appreciated that when all data areas of a certain sector are fully written, the erase operation cannot always be performed directly, and it needs to be considered whether at least one correct piece of data is reserved in another sector.
The power down data storage method may further include, but is not limited to, the steps of: and after the written data are protected at time intervals, detecting the power-down signal.
Specifically, the Flash needs to be erased and written for a long time, and the erasing times are limited, so a protection interval is added in the process to prevent the written data from being lost due to the too frequent erasing operation, the protection interval can be set to 40s, 60s, etc., and can be set to other different time intervals, which is not limited in the application.
Referring to fig. 6, fig. 6 is a flowchart of a power-down data storage method according to another embodiment of the present application. The power down data storage method further includes, but is not limited to, the steps of:
step S610: inquiring the latest correct data area in the full area of the first sector and the second sector;
Step S620: and updating the data of the latest correct data area into the memory.
It can be understood that after the system is powered up, the system will restore the latest data backup at the last power-down, query the latest correct data from the first sector and the second sector, and restore the latest correct data to the memory, for example, query that the latest correct data is in the seventh data area of the first sector, and restore the backup data of the seventh data area of the first sector.
It should be noted that, a common method used in the single chip microcomputer for checking the correctness of the data is crc (Cyclic Redundancy Check, cyclic redundancy check code) checking. For example, the crc code and the length can be always placed at the beginning of the data area, then, whether the data stored in the data area is consistent with the crc code at the beginning is calculated, if so, the method is correct, and the method is not limited in the application, so that the method is selected and designed by a person skilled in the art according to specific practical application.
Referring to fig. 7, fig. 7 is a flowchart of a power-down data storage method according to another embodiment of the present application, and step S610 may include, but is not limited to, the following steps:
Step S710: inquiring and checking all full areas of the first sector with correct data, and determining a first highest data area in the full areas of the first sector;
Specifically, all the data areas of the first sector where the data is correct are detected and checked, for example, the binary number of the flag bit of the first sector is "11100000", the data areas where the data is written have the first data area to the fifth data area, and then the data of the fifth data area is checked, if the data of the fifth data area is correct, the fifth data area of the first sector is the first highest data area.
Step S720: and inquiring and checking all full areas of the second sector with correct data, and determining a second highest data area in the full areas of the second sector.
Specifically, all the data areas of the first sector where the data is correct are detected and checked, for example, the binary system of the flag bit of the second sector is '11111000', the data areas where the data is written have the first data area to the third data area, and then the data of the third data area is checked, if the data of the third data area is wrong, the data of the second data area is checked continuously, and if the data of the second data area is correct, the second data area of the second sector is the second highest data area.
Referring to fig. 8, fig. 8 is a flowchart of a power-down data storage method according to another embodiment of the present application, and step S620 may include, but is not limited to, the following steps:
Step S810: and judging the size relation between the first highest data area and the second highest data area.
Step S820: if the second highest data area is higher than or equal to the first highest data area, updating the data of the second highest data area into the memory.
Specifically, for example, the second highest data area is the seventh data area of the second sector, the first highest data area is the seventh data area of the first sector, and the second highest data area is equal to the first highest data area, and then the data of the second highest data area is restored to the memory, that is, the data of the seventh data area of the second sector is restored.
Step S830: and if the second highest data area is lower than the first highest data area, restoring the data of the first highest data area to the memory.
Specifically, for example, the second highest data area is a seventh data area of the second sector, the first highest data area is an eighth data area of the first sector, and the second highest data area is lower than the first highest data area, and then the data of the first highest data area is restored to the memory, that is, the data of the eighth data area of the first sector is restored.
It is understood that the flag bit is the last byte of the data area, but the flag bit may be a byte of other places of the data area, which is not limited in the present application.
In a second aspect, referring to fig. 9, the present application further proposes a single chip microcomputer, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, where the processor implements the power-down data storage method according to any one of the embodiments of the first aspect when executing the computer program.
The processor and the memory may be connected by a bus or other means.
The memory is used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs and signals, such as program instructions/signals corresponding to the enterprise research and development investment potential evaluation system in the embodiment of the application. The processor executes various functional applications and data processing by running non-transitory software programs, instructions and signals stored in the memory, i.e., the enterprise research and development investment potential evaluation method implementing the above-described method embodiments.
The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area can store relevant data and the like of the enterprise research and development investment potential evaluation method. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located with respect to the processor, the remote memory being connectable to the enterprise development investment potential assessment system via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The one or more signals are stored in the memory that, when executed by the one or more processors, perform the power down data storage method of any of the method embodiments described above. For example, the above-described method steps S110 to S150 in fig. 1, the method steps S210 to S220 in fig. 2, the method steps S310 to S330 in fig. 3, the method steps S410 to S430 in fig. 4, the method steps S510 to S520 in fig. 5, the method steps S610 to S620 in fig. 6, the method steps S710 to S720 in fig. 7, and the method steps S810 to S830 in fig. 8 are performed.
In a third aspect, another embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or controller, for example, by one of the processors in the above-described single-chip embodiment, which may cause the processor to perform the power-down data storage method in the above-described embodiment, for example, performing the method steps S110 to S150 in fig. 1, the method steps S210 to S220 in fig. 2, the method steps S310 to S330 in fig. 3, the method steps S410 to S430 in fig. 4, the method steps S510 to S520 in fig. 5, the method steps S610 to S620 in fig. 6, the method steps S710 to S720 in fig. 7, and the method steps S810 to S830 in fig. 8 described above.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
The embodiments of the present application have been described in detail with reference to the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present application.
Claims (8)
1. A power down data storage method, comprising:
Dividing a storage module to obtain a first sector and a second sector;
Dividing the first sector and the second sector into a plurality of data areas; each data area comprises a writing area for writing data and a full area for writing data;
Receiving a power-down signal;
determining a target writing data area from the writing area according to the power-down signal; wherein the target write data area is one of the write areas;
writing backup data into the target writing data area, and modifying the flag bit of the target writing data area;
wherein the determining the target writing data area from the writing area according to the power-down signal includes:
determining storage states of the first sector and the second sector; the storage state comprises a full storage state and an unfilled storage state;
If the first sector and the second sector are in a full state and the second sector comprises correct data, the first sector is erased and the lowest data area of the first sector is set as the target writing data area;
If the first sector and the second sector are in a full state and the second sector does not comprise correct data, the second sector is erased, the highest data area of the second sector is set as the target writing data area, and the non-highest data area of the second sector is set as a full area;
if the second sector is in a full state and the first sector is in an unfilled state and the first sector comprises correct data, the second sector is erased and the lowest data area of the second sector is set as the target writing data area;
And if the second sector is in a full state and the first sector is in an unfilled state and the first sector does not comprise correct data, the first sector is erased and the lowest data area of the first sector is set as the target writing data area.
2. The method of claim 1, wherein determining a target write data area from the write area based on the power down signal comprises:
Determining a first lowest data area in the writing area of the first sector and a second lowest data area in the writing area of the second sector according to the power-down signal;
And determining the target writing data area according to the first lowest data area and the second lowest data area.
3. The power down data storage method of claim 2, wherein the determining the target write data area from the first lowest data area and the second lowest data area comprises:
determining a size relationship between the first lowest data area and the second lowest data area,
If the first lowest data area is lower than or equal to the second lowest data area, setting the first lowest data area as the target writing data area;
And if the first lowest data area is higher than the second lowest data area, setting the second lowest data area as the target writing data area.
4. The power down data storage method of claim 1, further comprising:
inquiring the latest correct data area in the full area of the first sector and the second sector;
and updating the data of the latest correct data area into a memory.
5. The method of claim 4, wherein the querying the latest correct data area in the full area of the first sector and the second sector comprises:
Querying and checking all full areas of the first sector with correct data, and determining a first highest data area in the full areas of the first sector;
and inquiring and checking all full areas of the second sector with correct data, and determining a second highest data area in the full areas of the second sector.
6. The method for storing power-down data according to claim 5, wherein updating the data of the latest correct data area into the memory comprises:
determining a size relationship between the first highest data area and the second highest data area,
If the second highest data area is higher than or equal to the first highest data area, updating the data of the second highest data area into a memory;
And if the second highest data area is lower than the first highest data area, updating the data of the first highest data area into a memory.
7. The utility model provides a singlechip which characterized in that includes: a processor, a memory and a computer program stored on the memory and executable on the processor, the processor implementing the power down data storage method as claimed in any one of claims 1 to 6 when the computer program is executed.
8. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the power-down data storage method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110078948.9A CN112817527B (en) | 2021-01-21 | 2021-01-21 | Power-down data storage method, singlechip and computer-readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110078948.9A CN112817527B (en) | 2021-01-21 | 2021-01-21 | Power-down data storage method, singlechip and computer-readable storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112817527A CN112817527A (en) | 2021-05-18 |
| CN112817527B true CN112817527B (en) | 2024-06-04 |
Family
ID=75858918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110078948.9A Active CN112817527B (en) | 2021-01-21 | 2021-01-21 | Power-down data storage method, singlechip and computer-readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112817527B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113568579B (en) * | 2021-07-28 | 2022-05-03 | 深圳市高川自动化技术有限公司 | Memory, data storage method and data reading method |
| CN114242125B (en) * | 2021-11-15 | 2022-11-08 | 珠海妙存科技有限公司 | Power-down protection method, device and medium for NAND FLASH data |
| CN114428588A (en) * | 2021-12-17 | 2022-05-03 | 深圳市拔超科技股份有限公司 | Flash power-down data storage method and system |
| CN114385082A (en) * | 2021-12-31 | 2022-04-22 | 北京得瑞领新科技有限公司 | Data processing method of NOR flash memory, storage medium and SSD device |
| CN114816833B (en) * | 2022-04-15 | 2023-07-18 | 巨翊科技（上海）有限公司 | Writing method, device and system of flash data |
| CN115048050A (en) * | 2022-06-11 | 2022-09-13 | 杭州明特科技有限公司 | Intelligent electric meter data storage method, system and medium |
| CN115509465B (en) * | 2022-11-21 | 2023-03-28 | 杭州字节方舟科技有限公司 | Sector management method and device, electronic equipment and storage medium |
| CN117420962B (en) * | 2023-12-14 | 2024-05-14 | 深圳市德兰明海新能源股份有限公司 | Data access management method, single chip microcomputer product and storage medium |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07160597A (en) * | 1993-12-02 | 1995-06-23 | Fujitsu Ltd | Controller for flash memory |
| US6154808A (en) * | 1997-10-31 | 2000-11-28 | Fujitsu Limited | Method and apparatus for controlling data erase operations of a non-volatile memory device |
| JP2006155144A (en) * | 2004-11-29 | 2006-06-15 | Sony Ericsson Mobilecommunications Japan Inc | Data storage method for nonvolatile memory, computer program and portable terminal |
| JP2007164364A (en) * | 2005-12-12 | 2007-06-28 | Mitsubishi Electric Corp | Information recording/reading device |
| CN102063379A (en) * | 2010-12-28 | 2011-05-18 | 天津市亚安科技电子有限公司 | Data storage method of FLASH memory |
| CN105760112A (en) * | 2016-02-01 | 2016-07-13 | 惠州市蓝微新源技术有限公司 | Data storage method, reading method and systems for prolonging service life of memory |
| CN105988722A (en) * | 2015-01-27 | 2016-10-05 | 纬创资通股份有限公司 | Data storage method and embedded system |
| CN107256197A (en) * | 2017-05-18 | 2017-10-17 | 深圳市晟碟半导体有限公司 | A kind of date storage method, storage device and intelligent terminal |
| CN107479834A (en) * | 2017-08-28 | 2017-12-15 | 北京智芯微电子科技有限公司 | A kind of file memory method and device based on COS |
| CN107797765A (en) * | 2017-09-26 | 2018-03-13 | 昆明理工大学 | A kind of method for extending electric erasable memory element service life |
| CN109947369A (en) * | 2019-03-22 | 2019-06-28 | 河南卓正电子科技有限公司 | Date storage method and device |
| CN109947364A (en) * | 2019-02-01 | 2019-06-28 | 浙江蓝点动力科技有限公司 | A kind of method for storing real-time data in FLASH/EEPROM |
| CN110968268A (en) * | 2019-11-15 | 2020-04-07 | 成都智邦科技有限公司 | Storage management method and storage structure based on spiflash |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3188021A1 (en) * | 2015-12-30 | 2017-07-05 | Thomson Licensing | Method and device for saving data |
| CN107704200A (en) * | 2017-09-08 | 2018-02-16 | 晶晨半导体(上海)股份有限公司 | A kind of data deposit method |
-
2021
- 2021-01-21 CN CN202110078948.9A patent/CN112817527B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07160597A (en) * | 1993-12-02 | 1995-06-23 | Fujitsu Ltd | Controller for flash memory |
| US6154808A (en) * | 1997-10-31 | 2000-11-28 | Fujitsu Limited | Method and apparatus for controlling data erase operations of a non-volatile memory device |
| JP2006155144A (en) * | 2004-11-29 | 2006-06-15 | Sony Ericsson Mobilecommunications Japan Inc | Data storage method for nonvolatile memory, computer program and portable terminal |
| JP2007164364A (en) * | 2005-12-12 | 2007-06-28 | Mitsubishi Electric Corp | Information recording/reading device |
| CN102063379A (en) * | 2010-12-28 | 2011-05-18 | 天津市亚安科技电子有限公司 | Data storage method of FLASH memory |
| CN105988722A (en) * | 2015-01-27 | 2016-10-05 | 纬创资通股份有限公司 | Data storage method and embedded system |
| CN105760112A (en) * | 2016-02-01 | 2016-07-13 | 惠州市蓝微新源技术有限公司 | Data storage method, reading method and systems for prolonging service life of memory |
| CN107256197A (en) * | 2017-05-18 | 2017-10-17 | 深圳市晟碟半导体有限公司 | A kind of date storage method, storage device and intelligent terminal |
| CN107479834A (en) * | 2017-08-28 | 2017-12-15 | 北京智芯微电子科技有限公司 | A kind of file memory method and device based on COS |
| CN107797765A (en) * | 2017-09-26 | 2018-03-13 | 昆明理工大学 | A kind of method for extending electric erasable memory element service life |
| CN109947364A (en) * | 2019-02-01 | 2019-06-28 | 浙江蓝点动力科技有限公司 | A kind of method for storing real-time data in FLASH/EEPROM |
| CN109947369A (en) * | 2019-03-22 | 2019-06-28 | 河南卓正电子科技有限公司 | Date storage method and device |
| CN110968268A (en) * | 2019-11-15 | 2020-04-07 | 成都智邦科技有限公司 | Storage management method and storage structure based on spiflash |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112817527A (en) | 2021-05-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112817527B (en) | Power-down data storage method, singlechip and computer-readable storage medium | |
| CN106407050B (en) | Data storage method | |
| CN112631628B (en) | Singlechip upgrading method, singlechip and storage medium | |
| CN108170495B (en) | BIOS upgrading method, system, equipment and computer readable storage medium | |
| US20050036390A1 (en) | Non-volatile memory and non-volatile memory data rewriting method | |
| CN101681281A (en) | Emerging bad block detection | |
| CN106021002B (en) | Data reading and writing method and device for embedded equipment | |
| CN112397128B (en) | Control method and device of Flash memory | |
| CN104282342A (en) | Flash memory device, memory controller and control method of flash memory | |
| CN110704257A (en) | Solid state disk, quality monitoring method and device thereof and computer readable storage medium | |
| CN112068772B (en) | Data storage method, data storage device and storage device | |
| CN114237984A (en) | Recovery method and system of Trim data under abnormal power failure and solid state disk | |
| CN107992268B (en) | Bad block marking method and related device | |
| CN114089915B (en) | File additional writing operation method and device based on FLASH memory | |
| JP2019096281A (en) | Data storage device and associated operating method | |
| CN117742588B (en) | Data storage method and system using Flash simulation EEPROM | |
| CN107329850B (en) | Memory satisfying mass read-write frequency operation and data storage method | |
| CN112527207A (en) | Method and device for storing data in EEPROM | |
| CN112908390B (en) | Data storage method, device, electronic equipment and storage medium | |
| EP3468261A1 (en) | Control method and apparatus for smart card, terminal device, and smart card | |
| JP2003196165A (en) | Nonvolatile memory and data updating method therefor | |
| CN115167761A (en) | Intelligent water affair terminal data protection method and system | |
| CN111258498B (en) | FLASH memory management method | |
| CN113254364B (en) | Information storage device for embedded system | |
| CN116610269B (en) | Data storage method, device, storage medium and controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |