CN1128070A - 带有区域和通用信号线路的可编程逻辑装置 - Google Patents
带有区域和通用信号线路的可编程逻辑装置 Download PDFInfo
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Abstract
可编程逻辑装置具有一组分组排列的逻辑单元,局部和多区域总线,交叉点开关矩阵电路(37),它仅从总线(391-39J)和(401-40L)向逻辑单元(311-31J)的输入端发送信号,没有逻辑连接两个或更多的总线信号,即,没形成乘积项。每一个逻辑单元(311-31J)向一个通用总线(191)供给一个逻辑反馈信号(411-41J),并且能向一个通用总线反馈另外的逻辑信号通过它的通用开关矩阵电路,这个矩阵电路把一组附属的区域反馈信号和通用总线连接起来。
Description
技术领域
本发明涉及被称为可编程逻辑装置类型的集成电路,特别地,本发明涉及改善这种装置整体功能适应性的互联方案或设计。
背景技术
在Gudger等人的5,079,451号美国专利中,描述了具有全局和局部总线的可编程逻辑装置(PLD),其中那些总线向逻辑单元提供乘积项。全局总线可与所有逻辑单元进行通讯,而每个局部总线只能与该装置中的某些逻辑单元进行通讯。全局和局部乘积项信号由AND矩阵产生,该矩阵电路在结构上与该总线集成在一起。也就是说,可编程AND矩阵电路以一组可编程互联而出现,该互联位于乘积项线路(逻辑单元输入)与全局和局部总线中信息传输线路相交叉处。因此,由该信息传输线路,逻辑单元以及可编程互联而构成的交叉点矩阵电路是一个逻辑组合单元,从根本上讲是一组宽扇入AND门,其中该信息传输线路均成门输入,而该逻辑单元输入则构成门输出。逻辑单元构成产生乘积和项的第二逻辑电平,其中该逻辑单元的OR门接收由逻辑输入上而产生的乘积项信号。
典型的场可编程门阵列(FPGAs)具有这样的布局,其中逻辑块被排列成包含行和列逻辑块的二维阵列,且其中互联资源占据行与列之间的空间。这些互联构成交叉点开关矩阵电路,该矩阵电路的作用是将信号从逻辑块输出引向逻辑块输入。该互联矩阵电路通常被构造得使信号可基本上能够引向装置中所有的逻辑块。然而,每个逻辑块输入各自只与互联结构中的一条信息传输线路相连。
在Ebeling等人的5,208,491号美国专利中,描述了具有相互衔接的正向传输和反向传输通信及逻辑块(FPRLBs和BPRLBs)镶嵌阵列的FPGA。一组正向传输和反向传输垂直分设通信通道(FPSRCs和BPSRCs)作为相邻RLBs列之间的信号总线。各个FPRLB(或BPRLB)接收来自一个垂直通道中直接相邻的FPSRC(或BPSRC)的输入信号并向相对垂直通道中另一直接相邻的FPSRC(或BPSRC)输送输出信号。FPSRCs和BPSRCs中各自的数据总线被分割成不同长度,以允许同FPRLBs和BPRLBs进行短距、中距和远距通讯。
本发明之概述
本发明的目的在于利用引入目前只在FPGAs中发现的某些互联特性而改善可编程逻辑装置(PLDs)的功能灵活性。
上述目的在如下的可编程逻辑装置中得到了实现,该可编程装置具有一组排列在分离逻辑区域内的逻辑单元,一组包括局部和多区域总线的总线,并具有一交叉点开关矩阵电路,该矩阵电路只起将来自总线的信号引向逻辑单元输入端的作用,而不对该总线信号进行逻辑结合以形成在那些输入端处的乘积项。在PLD的开关矩阵电路中,每条总线可与一个以上逻辑单元输入端相接,但每个逻辑单元输入端在不短路的情况下只能与一条总线进行有意义的连接。在优选方案中,每个逻辑单元可反馈一个逻辑信号到一条局部总线并可潜在地通过一通用选择矩阵电路向多区域总线或通用总线反馈另一逻辑信号。对于每个逻辑单元区域提供了一个通用选择矩阵电路以选择用于连接通用总线的潜在反馈信号子集。
附图简要说明
图1给出了本发明超可编程逻辑装置(超PLD)芯片级方案的框图。
图2给出了图1超PLD中逻辑区域之一的细节的框图。
图3a和3b给出了图2逻辑区域中逻辑单元之一的门级结构的框图。图3b为该逻辑单元的反馈选择部分,它被连接于图3a中组合信号线路E、寄存器输出Q和I/O引线。
图4为图1超PLD交叉点开关矩阵电路的局部简化示图,该矩阵电路与图3逻辑单元中的通用逻辑门(ULGs)相接。
图5为图4矩阵电路中交叉点开关之一的电路示意图。
实施本发明之最佳方式
参考图1,本发明的超可编程逻辑装(超PLD)以其最上层芯片级方案给出,该装置包括一组N个独立的逻辑区域111-11N,这些逻辑区域通过公共的通用信号总线13相互连接在一起。典型地,该超PLD具有4至8个逻辑区域(4≤N≤8),但该逻辑区域数N并非一定要那样严格限定。接下来,每个逻辑区域具有一组逻辑单元151-15N、用于产生局部控制信号的电路块171-17N以及局部信号总线191-19N。每组单元151-15N中逻辑单元数J、K等等,即各个逻辑区域111-11N中的逻辑单元数的典型值约为20,但这个数值并不是限定的,并且在给定的装置中,对于每个逻辑区域而言,这个数目也不必相同。例如,逻辑区域111中逻辑单元151的数目J可能为20(J=20),而逻辑区域11N中逻辑单元15N的数目K则可能为24(K=24),进而其它各逻辑区域中的各组逻辑单元数可能为15、16、18或其它某个数值。在某些装置中,该装置的每个逻辑单元或给定区域中的每个逻辑单元为与特定I/O连线21相连的输入/输出(I/O)型宏单元,而在其它的装置中,区域111-11N的至少一个区域中,某些逻辑单元可能被埋没而与I/O连接无任何联系。在所有的情况下,各个逻辑区域111-11N中I/O连线21的数目均等于在该区域中的I/O型宏单元数且绝不能超过该区域所有逻辑单元151-15N的总数。因此,具有J个逻辑单元的逻辑区域111最多具有J个与之相关联的I/O连线21,这个数目等于该区域逻辑单元组151中的I/O型宏单元数。各个局部控制信号生成电路块171-17N提供若干控制信号(例如输出起动及异步复位信号),经局部控制线181-18N,传送给特定区域111-11N的逻辑单元151-15N。其它控制信号(如局部时钟信号)可以由专用时钟连线221-22N提供。
通用信号总线13从各个逻辑区域111-11N的逻辑单元151-15N经线路23接收一组反馈信号并利用输入线路25向所有区域111-11N的逻辑单元151-15N和控制信号生成电路块171-17N提供公用输入信号。只输入连线30也可以向通用总线13提供信号。N个独立的局部信号总线191-19N从相应逻辑区域111-11N的逻辑单元151-15N经局部反馈线路271-27N接收局部反馈信号并利用输入线路291-29N向相应逻辑区域111-11N的逻辑单元151-15N和控制信号生成电路块171-17N分别提供一组局部输入信号。应当注意,尽管通用和局部反馈线路23和271-27N在通常情况下各自完全不同,但输入线路25和291-29N可与通用总线13或任一条局部总线191-19N编程相连。因此,输入线路或传输来自通用总线13的公用输入信号并因此可被认为是通用输入线路25,或传输来自局部总线191-19N的局部输入信号并因此可被认为是局部输入线路291-29N,这要依据特定装置中的实际编程连接而定。
参考图2,典型的逻辑区域(例如图中给出的是图1的逻辑区域111)具有排列成一组151的J个逻辑单元311-31J、至少与逻辑单元311-31J中的某些相连的输入/输出连线21、用于向区域111的151组逻辑单元311-31J经线路181提供局部控制信号的单个控制信号生成电路块171、以及局部信号总线191。典型地,在一个逻辑区域中约有20个逻辑单元311-31J。某些逻辑单元为具有相关I/O连线21的输入/输出(I/O)型宏单元,而另外的逻辑单元可能被埋没。除了这个差别以外,典型的逻辑单元311-31J在结构上相互基本一样。每个逻辑单元311-31J具有若干与输入线路311-31J相接的输入端(其典型值为每个逻辑单元约有10个),用于接收来自局部和通用总线191和13的相应数目的输入信号。控制信号生成电路块171同样具有若干与输入线路35相接的输入端(其典型值约为6个),用于接收来自局部和通用总线191和13的相应数目的附加输入信号。这样,一个典型的、具有20个逻辑单元的逻辑区域将拥有约206条输入线路331-33J和35。
交叉点开关矩阵电路37为每个逻辑区域选择总线391-39J和401-40L(包括总线40i)中的某一条与输入线路331-33J和35中的某一条相连接。交叉点开关矩阵电路37允许任意总线(包括局部总线191和通用总线13)中的任何信号与输入线路331-33J和35中的任意线路相连接。然而,尽管相同的总线可以与多个输入线路相接,但每个输入线路可允许只与一条总线连接。将一条输入线路与多于一条总线相接将短路受损害的线路并导致不确定的信号电平。另外,尽管通用总线13中的信号可提供给所有区域111-11N中的输入线路,但局部总线191中的信号则只能提供给该特定逻辑区域111中的逻辑单元311-31J和控制信号电路块171。在其它局部总线192-19N中的信中不能供给逻辑区域111,而只能提供给与它们相关联的区域。
逻辑区域中的各个逻辑单元311-31J经局部反馈线路411-41J将一个反馈信号直接引向局部总线191,其中各个反馈线路411-41J以一一对应的方式与特定的局部总线391-39J固定相连。除了由J个逻辑单元提供的J个局部总线信号之外,每个区域的逻辑单元组151还产生若干通用反馈信号,这些信号经通用反馈线路43被引至通用总线13。每束反馈线路43与通用总线13中的相应总线40i束相连,其中一条反馈线路与一条总线以一一对应的方式固定地相连。为产生这些通用总线信号,区域中逻辑单元311-31J的每一个均经线路451-45J向通用开关矩阵电路(USM)47馈送一个信号。然后,该区域的USM选择来自逻辑单元311-31J的信号子集,用以与通用总线13相连。典型地,大约40%的接收信号被选择,从而对于具有20个逻辑单元的区域,其典型USM将向通用总线13输送信号中的8个信号。从具有15或16个逻辑单元的区域中可选择6个信号,从具有18或20个逻辑单元的区域可选择8个信号,而从具有24个逻辑单元的区域可选择10个信号。然而,选择用以与通用总线13相连信号的百分比并非绝对限定,只需注意,对于一个特定的USM,在正常情况下其所选择的接收信号的比例不应超过约75%,除非在区域中逻辑单元的总数很小(12个或更少)时可超过上述值。
参考图3a和3b,各个逻辑单元或为I/O型宏单元(如图3a所示的逻辑单元312),或为隐埋宏单元。隐埋宏单元与图3a和3b中所描绘的I/O型宏单元类似,只不过它们不具备相关联的I/O连线21。在隐埋宏单元中,还缺少与连线上输出信号或来自I/O连线的接收输入信号相关的电路元件。在某些超PLDs或这种装置的某些区域中,所有逻辑单元均为具有相关I/O连线的I/O型宏单元,而本发明的其它PLDs既具有I/O型宏单元又具有隐埋宏单元。
如图3a所示,该优选装置的各个逻辑单元312包括4个四输入通用逻辑门电路(ULGs)51-54和两个二输入ULGs55和56。四输入ULGs中的两个51和53共用来自交叉点开关矩阵电路37的4条输入线路331(1-4),另两个四输入ULGs52和54共用另外4条输入线路331(5-8),而两个二输AULGs55和56则共用最后剩下的两条输入线路331(9-10)。每个四输入ULGs51-54可独立编程以生成其4个输入端的216个布尔逻辑函数中的任一个。同样,每个二输入ULGs55和56也可独立编程以生成其两个输入端的16种可能的布尔逻辑函数中的任一个。
4个四输入ULG输出57-60被用作两个逻辑门电路对63和64的输入。这些门电路对63和64可通过编程进行配置以作为AND门电路或作为OR门电路。门电路对63和64之后是一个四输入OR门电路65。该OR门电路65的一个输入端68与门电路对63的输出端相连。该OR门电路65的另一个输入端69可经过可编程开关电路74与另一门电路对64的输出端71相连。因此,OR门电路65可使得两门电路对的输出相互进行逻辑组合(″求和″或″取或″运算)。来自邻近逻辑单元的门电路对输出也可提供给OR门电路65的输入端67和70。同样,门电路对63和64的输出也可通过可编程开关电路73和75被传送给邻近的逻辑单元。这样,相邻的逻辑单元可相互共用或盗取门电路对的输出。
每个逻辑单元具有一个触发电路77,该触发电路可通过其中的可编程配置位(图中未示出)进行配置,以作为D型寄存器、T型寄存器或锁存器。对触发电路77的数据输入端78被接于具有4个输入端的倍频器79的输出端上。利用该倍频器79,对触发电路77的输入端78可以被选作OR门电路65的输出结点E、E结点的互补及门电路对64的输出结点B,或在I/O型宏单元的情况下被选作I/O连线21处所接收信号的互补。每个触发电路77具有两个时钟选择,它们可利用可配置的倍频器81进行选择。在一种选择下,时钟可以是逻辑单元自身时钟信号CK,它在该逻辑单元之内由二输入ULG56生成并经时钟线路83传向倍频器81的输入端。换句话说,该时钟可选为内部生成时钟信号CK与该区域在分派给它的外部时钟连线(图2中连线221)处接收的同步时钟信号RCK的逻辑积(AND门电路85的输出),从而允许门控制连线进行时钟操作。同样,利用对时钟生成ULG56进行编程以至总输出逻辑1(二输入ULG的16种可能的布尔函数之一),则可进行简单连线控制的时钟操作。触发电路77利用两局部异步复位控制信号RAR1和RAR2中的任一个,这是通过对可配置倍频器87进行编程而选择的。在每个区域中提供两个异步复位信号RAR1和RAR2允许一个区域内的逻辑单元分成两个子组合,该子组合中的触发电路由不同的信号进行复位。
在I/O型宏单元的情况下,逻辑单元还可借助另一倍频器89进行配置,以便输出结点E的组合信号,并输出来自触发电路77的寄存器输出Q,或输这两个信号中任一个的互补信号。每个I/O型宏单元还具有由线路93上的输出起动信号控制的三稳态输出缓冲器91。逻辑单元可利用相同的两个输入端331(9-10)作为时钟发生器56,选择由二输入ULG55生成的自身内部输出起动信号OE,或该信号OE可通过OR门电路95与图2中控制信号电路块171产生的局部输出起动信号ROE进行逻辑组合并作为该区域中所有I/O型宏单元的公用信号。信号OE或组合信号(OE+ROE)的选择可通过可配置倍频器97进行。
图2中控制信号生成电路块171利用三个独立的二输入ULGs产生控制信号RAR1和RAR2(异步复位信号)以及ROE(输出起动信号),其中每个二输入ULG经输入线路35接收两个不同的、来自交叉点矩阵电路37的输入信号。
如图3b所示,逻辑单元的反馈选择部分包括倍频器101,该倍频器的一个输入端与OR门电路65输出端的结点E相连以接收组合信号,而其另一个输入端则与触发电路77的输出端Q相连以接收寄存信号。倍频器101选择该组合信号或该寄存信号,并将此初始选择送至其输出端103以便用于向通用和局部总线进行可能的反馈。第二倍频器105的一个输入端与I/O连线21相接以接收连线信号,其另一个输入端与第一倍频器101的输出端103相接以接收所选择的组合或寄存反馈信号。该第二倍频器105将这两个信号中的一个传送给接于局部总线的局部反馈线路411,并将这两个信号的另一个经线路451提供给图2中通用选择矩阵电路(USM)47以便与通用总线进行可能的连接。因此,逻辑单元同时给出了局部和通用反馈两种选择。线路411上的局部反馈信号可通过编程作为E结点的组合信号以及触发电路输出端Q的存储信号,或在I/O型宏单元情况下作为连线信号。同样,从每个逻辑单元中选择一个信号作为线路451上的潜在通用反馈信号。象局部反馈一样,该潜在通用反馈信号的选择可通过I/O连线信号进行,也可通过由倍频器101初始选定的组合或寄存信号进行。然而,在本优选方案中,组合信号与存储信号不能同时用作来自给定逻辑单元的反馈信号。如图2所示,选定的潜在通用反馈信号进入该区域的USM47,且如前所述,该USM将其输入信号的子集(例如20个信号中的8个)映射到其通用总线上。
参考图4,交叉点开关矩阵电路37将局部和通用总线391-39J和401-40L(图中以水平线表示)与输入线路(图中以对应于输入线路中的8条311(1-8)的垂直线表示)相连接。在该图的顶部可见一个逻辑单元中的两个通用逻辑门电路51和52,这两个门电路各自与4条输入线路331(1-4)和331(5-8)相接。在每条总线与逻辑单元输入线路的交叉点有交叉点开关电路111,该开关电路可通过编程对这两条线路进行连接,从而允许总线信号被传送到相应输入线路之上。每条总线391-39J和401-40L可以与一条或多条输入线路33相连。然而,在任意一条输入线路上只可连接一条总线。任意未使用的输入线路可通过编程处于某种固定状态,该状态按要求由ULG51、52等等所提供的特定函数而确定为高电平或低电平。
如图5所示,每个交叉点开关电路111为一个传输门电路113,它由电可擦永久锁存器115进行控制。线路WL为总线,而标记为COL1和COL2的线路为两条输入线路。传输门电路113(此处为n沟道场效应晶体管)的源板和漏极与总线WL在结点117处相连并与输入线路COL1或COL2中的任一个在结点1181或1182处相连。屏蔽编程接线119决定两逻辑单元输入线路COL1和COL2中哪一条与传输门电路113相接。相邻的交叉点开关电路111(图中未示出)的传输门电路经由类似的屏蔽编程接线与其它输入线路相连。传输门电路113由SRAM锁存器115控制,该锁存器的一侧具有永久可编程存储元件121(如浮动栅极型EEPROM)。VREF为该永久存储元件121的传感线路。XSEL1和XSEL2为对应于两逻辑单元输入线路COL1和COL2的两条选择线路,它们通过屏蔽可编程接线125与选择晶体管123相连。当输入线路COL1接于传输门电路113时,选择线路XSEL1便与选择晶体管123相连。在相邻的单元中,COL2与XSEL2相连。选择线路在电源接通后脉动至Vcc,然后便固定在某个参考数值(约为2伏)。存储于永久存储单元121中的值在结点A(即选择晶体管123的源极)读出。传输门电路113的控制栅与SRAM锁存器在结点B相连。
在写模式下,VREF首先被充电至编程电压Vpp,而其它所有线路VC、VB、VS和XSEL均接地,以便对所有永久存储单元121的浮动栅极进行充电。然后,使VREF接地,VC为编程电压Vpp,VB接地及VS浮动,利用将XSEL保持在编程电压Vpp而对浮动栅极进行有选择性的放电。未选择的存储单元121的XSEL接地。在读模式下,VREF和VS接地,VC和VB为正常工作电压Vcc,XSEI在感应状态下为Vcc而在保持锁存器115中感应值的状态下为2伏。
在编程逻辑模式下,每个逻辑单元的输入只使其交叉点锁存器115中的一个被设定。同时将两条总线WL与单个逻辑单元输入COL1或COL2相连将由于通过传输门电路113的直接连接而使这两条总线短路,从而导致不确定信号电平及无效连接。因此,图2和4中所示的交叉点开关矩阵电路37不应被视为逻辑元件,这是由于乘积项不能通过对单个输入线路进行多总线连接而形成。相反,开关矩阵电路37只起着将总线信号引向一个或多个逻辑单元输入。
Claims (3)
1.可编程逻辑装置(PLD)包括:
一组逻辑单元,它们用于通过逻辑单元输入端接收输入信号,该逻辑单元分组排列,从而定义了这些单元的独立逻辑区域;
一组总线,它们用于传输信号;
交叉点开关矩阵电路,用于将总线与该逻辑单元输入端进行编程连接,每条总线可经由该矩阵电路中的一组交及点开关电路与至少一个逻辑区域中的逻辑单元输入端相连,一组该总线为可与多个逻辑区域中的逻辑单元输入端相连的多区域总线,该总线中的一部分为局部总线,其中每一条只能与一个逻辑区域中的逻辑单元输入端相连,而其中各个逻辑单元向该局总线中的一条提供局部反馈信号;以及
一组反馈选择矩阵电路,每个逻辑区域一个,而每个选择矩阵电路具有从其相应逻辑单元的该逻辑区域接收潜在多区域反馈信号的输入端,并具有向该多区域总线提供可编程选择的该潜在多区域反馈信号子集的输出端。
2.根据权利要求1的PLD,其中至少有一条多区域总线为可与每个逻辑区域中的逻辑单元相连的通用总线。
3.根据权利要求1的PLD,其中每个逻辑单元具有接收开关输入端的两个反馈信号的可编程开关装置,它用于选择该反馈信号中的一个作为在第一开关输出端提供给该局部总线之一的局部反馈信号,而选择该反馈信号中的另一个作为在第二开关输出端提供给对应于该逻辑单元的逻辑区域的反馈选择矩阵电路的潜在多区域反馈信号。
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- 1995-05-02 WO PCT/US1995/005436 patent/WO1995030952A1/en active IP Right Grant
- 1995-05-02 CN CN95190388A patent/CN1086815C/zh not_active Expired - Fee Related
- 1995-05-02 KR KR1019960700013A patent/KR100312801B1/ko not_active IP Right Cessation
- 1995-05-02 EP EP95917791A patent/EP0707721B1/en not_active Expired - Lifetime
- 1995-05-02 DE DE69525210T patent/DE69525210T2/de not_active Expired - Lifetime
- 1995-05-02 JP JP52904895A patent/JP3570724B2/ja not_active Expired - Fee Related
- 1995-06-19 US US08/492,390 patent/US5594366A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101009542B (zh) * | 2006-01-27 | 2010-05-12 | 中国科学院空间科学与应用研究中心 | 一种数据网络节点设备端口的扩展装置 |
Also Published As
Publication number | Publication date |
---|---|
EP0707721A1 (en) | 1996-04-24 |
US5594366A (en) | 1997-01-14 |
JPH09500516A (ja) | 1997-01-14 |
WO1995030952A1 (en) | 1995-11-16 |
EP0707721A4 (en) | 1998-06-17 |
EP0707721B1 (en) | 2002-01-30 |
KR100312801B1 (ko) | 2001-12-28 |
CN1086815C (zh) | 2002-06-26 |
DE69525210D1 (de) | 2002-03-14 |
JP3570724B2 (ja) | 2004-09-29 |
KR960704264A (ko) | 1996-08-31 |
DE69525210T2 (de) | 2002-11-28 |
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