CN112803990B - Satellite-borne VDES (vertical double-diffusion evolution) receiving load radio frequency channel - Google Patents
Satellite-borne VDES (vertical double-diffusion evolution) receiving load radio frequency channel Download PDFInfo
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- CN112803990B CN112803990B CN202110269204.5A CN202110269204A CN112803990B CN 112803990 B CN112803990 B CN 112803990B CN 202110269204 A CN202110269204 A CN 202110269204A CN 112803990 B CN112803990 B CN 112803990B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1851—Systems using a satellite or space-based relay
- H04B7/18515—Transmission equipment in satellites or space-based relays
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention provides a satellite-borne VDES receiving load radio frequency channel which is characterized by comprising a receiver structure, a phase-locked loop structure, a wide-band and narrow-band switching structure and an AGC structure. The receiver structure includes VHF antennas and LNA components; the phase-locked loop structure comprises a PLL component; the wide-narrow band switching structure comprises a radio frequency switch, a wide band-pass filter and a narrow band-pass filter; the AGC structure comprises a two-stage AGC circuit comprising a VCA circuit and a VGA circuit. The invention can be applied to a satellite-borne VDES receiving load receiver, works in a VHF frequency band, has the working characteristics of low noise coefficient, high signal-to-noise ratio and large dynamic range, can reasonably switch channels according to the intensity of environmental noise and interference, has strong anti-interference capability, does not influence the concurrent operation of each channel, has the adaptive capability of high-temperature, low-temperature and large-temperature-difference alternation, can work in the high-temperature, low-temperature and large-temperature-difference alternation environment, can reduce the weight of the device, and has the characteristics of miniaturization and low power consumption.
Description
Technical Field
The invention relates to a satellite-borne load receiving radio frequency channel, in particular to a satellite-borne VDES load receiving radio frequency channel.
Background
The VDES (very high frequency Data Exchange System) is an enhancement and upgrade of an existing marine navigation aid System AIS (Automatic Identification System), and in order to solve the problem of high link load caused by the increase of AIS users and the expansion of applications thereof, the VDES adds functions of ASM (Application Specific Messages) and VDE (very high frequency Data Exchange) on the basis of integrating the existing AIS services. The AIS subsystem is used for exchanging ship position and speed information, guaranteeing position tracking, line navigation, ship identity recognition and other information related to ship line safety, and has the highest priority; the ASM is designed to reduce the load of the AIS link and is used for transmitting information such as hydrology and weather forecast; the VDE channel is the core of VDEs, and provides a large capacity data exchange for the system, which is used for transmitting information such as charts.
Since the 90 s of the last century, the automatic ship identification system was not designed in consideration of detection from space, and provides services using satellites. In recent years, a VDES satellite part with newly added ASM and VDE functions is in the process of research and development and international standardization, and has great significance for strengthening traffic safety of sea areas, mastering modern leading technologies and timing and actively researching satellite-borne VDES.
The VDES covers three services and nine types of channels, the modulation and demodulation modes of the channels are different, the bandwidths are different, the mechanisms of accessing the system are not completely the same, the concurrent mechanisms and the transmission priorities of various services are different, and the channel management and channel switching are more complicated. Therefore, the key to the current VDES device development is the coordinated, optimized inter-channel switching method and channel management mode.
Disclosure of Invention
In order to solve the technical problem, the invention provides a satellite-borne VDES payload radio frequency channel which is characterized by comprising a receiver structure, a phase-locked loop structure, a wide-band and narrow-band switching structure and an AGC structure.
Further, the receiver structure filters and amplifies the received signal with low noise, and realizes down-conversion with the local oscillator signal provided by the phase-locked loop structure, so as to provide the intermediate frequency signal with high signal-to-noise ratio and low noise coefficient for the subsequent process; the phase-locked loop structure provides the local oscillation signals with high stability and low phase noise for the receiver structure, local oscillation frequency switching is carried out on each channel in the VDES, and switching and management among different channels are carried out; the wide-narrow band switching structure indicates the wide-band mode and the narrow-band mode of the switching channel according to the intensity of the environmental noise; the AGC structure is used for realizing signal amplitude regulation and control and providing structural support for the performance of a receiver in a large dynamic range.
Further, the receiver architecture includes VHF antenna and LNA components; the phase-locked loop structure comprises a PLL component; the wide-narrow band switching structure comprises a radio frequency switch, a wide band-pass filter and a narrow band-pass filter; the AGC structure comprises a two-stage AGC circuit of VCA circuit and VGA circuit.
Furthermore, the phase-locked loop structure comprises a single chip microcomputer, a phase discriminator, a frequency divider, a low-pass filter circuit and a VCO component.
Further, the baseband processing module sends a frequency switching instruction to the single chip microcomputer through a 3-bit control line, and the selective control phase-locked loop structure switches corresponding local oscillation frequency.
Further, a baseband processor of the baseband processing module sends a switch switching instruction to control the radio frequency control switch to realize switching between the wide band-pass filter and the narrow band-pass filter.
Further, the system comprises 7 receiving channels of AIS1, AIS2, two long-distance AIS channels, ASM1, ASM2 and VDE-SAT, wherein the 7 receiving channels are combined into one channel and enter a baseband processing module for demodulation after passing through the broadband filter and the AGC circuit; or ASM1, ASM2, AIS1, AIS2 are combined into one channel, and in addition, the two channels of long-distance AIS and VDE-SAT are also included, and the two channels pass through the narrow-band filter and the AGC circuit together and enter a baseband processing module for demodulation.
Furthermore, the devices in the phase-locked loop structure adopt ADF4360-8BCP chips of ADI company and a singlechip chip P89LPC915FDH of PHILIPS.
Further, the circuit of the wide-narrow band switching structure adopts a baseband processing module to control a chip HMC849ALP4CE with high isolation to perform SPDT switching, a switch is switched to a narrow-band intermediate frequency filter at high level, the filter selects MP04904 with a bandwidth of 360KHz, the switch is switched to a wide-band filter at low level, the filter selects MA05327 with a bandwidth of 6.7MHz, and the default state of the switch is low level.
Furthermore, the circuit of the AGC structure comprises an integrating circuit and a detection circuit which are formed by an operational amplifier chip MAX4130EUK-T and a resistance-capacitance device and used for providing control voltage for the AGC, and a voltage-controlled gain control circuit: VGA and VCA enable signal amplitude control to be more acute, processed data are effectively sent to a digital baseband to be processed, an automatic gain control chip AD8367 with the gain range of-2.5 dB to +42.5dB is adopted to realize a VGA circuit, a voltage-controlled attenuator RFSA2023 with the gain range of-35 dB to-5 dB is adopted to realize a VCA circuit, and the dynamic range of a VDES receiving load is enabled to reach 75dB.
Compared with the prior art, the satellite-borne VDES receiving load radio frequency channel can be suitable for being applied to a satellite-borne VDES receiving load receiver, works in a VHF frequency band, has the working characteristics of low noise coefficient, high signal-to-noise ratio and large dynamic range, can reasonably switch between channels according to the intensity of environmental noise and interference, has strong anti-interference capability, does not influence the concurrent operation of each channel, has the adaptability of high temperature, low temperature and large temperature difference alternation, can work in the high temperature, low temperature and large temperature difference alternation environment, can reduce the weight of the device, and has the characteristics of miniaturization and low power consumption.
Drawings
FIG. 1 is a functional block diagram of one embodiment of a satellite-borne VDES receive payload radio frequency channel of the present invention;
FIG. 2 is a block diagram of an embodiment of a phase-locked loop architecture for a satellite-borne VDES receiver payload RF channel in accordance with the present invention;
FIG. 3 is a block diagram illustrating the switching structure of the wideband and narrowband switching structure of the RF channel of the satellite-borne VDES receiver payload according to an embodiment of the present invention;
FIG. 4 is a block diagram showing the AGC structure of the RF channel of the satellite VDES receiver load according to one embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to the accompanying drawings.
The satellite-borne VDES load receiving radio frequency channel provided by the invention relates to space-based AIS, ASM, VDE data receiving and VDE data sending functions, is mainly used for acquiring position information, navigation speed, water marks and weather information near a ship and supporting information interaction between an individual user in the ship and a remote ship terminal.
The satellite-borne VDES load receiving radio frequency channel comprises a receiver structure, a phase-locked loop structure, a wide-band and narrow-band switching structure and an AGC (Automatic Gain Control) structure.
FIG. 1 is a schematic block diagram of one embodiment of a satellite-borne VDES receive payload radio frequency channel of the present invention. As shown in fig. 1, in one embodiment, the receiver structure of the satellite-borne VDES receive payload radio frequency channel of the present invention includes a VHF antenna and LNA (Low Noise Amplifier) component; the Phase-Locked Loop structure comprises a PLL (Phase Locked Loop) component; the wide-band and narrow-band switching structure comprises a radio frequency switch, a wide-band pass filter and a narrow-band pass filter; the AGC structure includes a two-stage AGC circuit of a VCA (Voltage Control Attenuator) circuit and a VGA (Variable Gain Amplifier) circuit.
The satellite-borne VDES load receiving radio frequency channel has the main functions of filtering, low-noise amplification, down-conversion, automatic gain control and analog-to-digital conversion of received radio frequency signals, and then transmitting the radio frequency signals to a baseband processing module for digital sampling and signal processing.
The receiver structure carries out filtering and low-noise amplification on the received signals, and realizes down-conversion together with local oscillation signals provided by the phase-locked loop structure, so as to provide intermediate-frequency signals with high signal-to-noise ratio and low noise coefficient for follow-up. After the intermediate frequency signal is subjected to three-stage filtering and AGC, the intermediate frequency signal is divided into two paths of signals by the power divider, one path of signals is received by the baseband processing module, and the other path of signals is output to be AGC control voltage through the detection circuit.
The phase-locked loop structure provides local oscillation signals with high stability and low phase noise for the receiver structure, guarantees are provided for achieving low sensitivity indexes of the receiver structure, and technical guarantees are provided for reasonable switching between channels through switching between different local oscillation frequencies.
Fig. 2 is a block diagram of the phase-locked loop structure of the satellite-borne VDES receive payload rf path according to an embodiment of the present invention. As shown in fig. 2, the phase-locked loop structure of the present invention includes a single chip, a phase detector, a frequency divider, a low-pass filter circuit, and a VCO (Voltage controlled Oscillator) component. Therefore, reasonable channel switching and management are realized for receiving different signal frequencies. In one embodiment, the devices in the phase-locked loop structure adopt an ADF4360-8BCP chip of ADI corporation and a single chip microcomputer chip P89LPC915FDH of PHILIPS, and a VCO (Voltage Controlled Oscillator), a phase detector and a frequency divider are integrated inside the ADF4360-8BCP, so that miniaturization is realized on the basis of outputting a stable local Oscillator, and a clock provides a reference frequency for the phase detector. The baseband processing module sends a frequency switching instruction to the single chip microcomputer through a 3-bit control line, and the selective control phase-locked loop structure switches corresponding local oscillation frequency, so that intermediate frequency signals obtained through down-conversion fall in a pass band of the intermediate frequency filter circuit, channel division is achieved, and hardware resources are saved.
Therefore, the invention utilizes the baseband processing module to carry out 3-bit control line selection control on the phase-locked loop structure, carries out local oscillation frequency switching corresponding to each channel in the VDES, and carries out switching and management among different channels.
The radio frequency channel of satellite-borne VDES receiving load comprises AIS1, AIS2, two long-distance AIS channels, ASM1, ASM2 and VDE-SAT which are 7 receiving channels, wherein the 7 receiving channels can be combined into one channel and enter a baseband processing module for demodulation through a broadband filter and an AGC circuit. In addition, because the satellite environment noise and the interference are relatively complex, in order to improve the single-machine capturing capability, a narrow-band mode is set as a backup, and the backup enters a baseband processing module for demodulation through a narrow-band filter and an AGC circuit. The narrow band channel is divided according to frequency, and ASM1, ASM2, AIS1 and AIS2 can be combined into one channel, and the two channels of long-distance AIS and VDE-SAT are also included. Each independent channel is distinguished by controlling and switching local oscillation frequency through a baseband processing module, and a broadband mode and a narrowband mode are switched through a radio frequency switch by the baseband processing module.
Fig. 3 is a block diagram of the wideband and narrowband switching structure of the satellite-borne VDES payload rf channel according to an embodiment of the present invention. As shown in fig. 3, the baseband processor with the processing module sends a switch switching instruction to control the radio frequency control switch to implement switching between the wide band-pass filter and the narrow band-pass filter, so as to provide structural support for reasonable switching between channels and improve the capturing capability of the receiver for weak signals. In one embodiment, the circuit of the wide-narrow band switching structure uses a Single Pole Double Throw (SPDT) switch chip HMC849ALP4CE with high isolation, the baseband processing module controls the high and low levels of the switch chip pin to realize the switching between the wide band mode and the narrow band mode, the switch switches to a narrow band intermediate frequency filter at the high level, the filter selects MP04904 with a bandwidth of 360KHz, the switch switches to a wide band filter at the low level, the filter selects MA05327 with a bandwidth of 6.7MHz, and the switch default state is the low level.
Therefore, the broadband and narrowband switching structure can indicate the broadband and narrowband modes of the switching channel according to the intensity of the environmental noise, and avoid the phenomena of overhigh noise, deteriorated signal-to-noise ratio and overlarge interference and channel blockage.
FIG. 4 is a block diagram showing the AGC structure of the RF channel of the satellite VDES receiver load according to one embodiment of the present invention. The AGC structure is used for realizing signal amplitude regulation and control and providing structural support for the performance of a receiver in a large dynamic range. As shown in fig. 4, the AGC structure of the satellite-borne VDES receive load radio frequency channel of the present invention includes a VCA circuit and a VGA circuit, and signal amplitude regulation is performed by using a two-stage AGC circuit. In one embodiment, the circuit of the AGC structure of the present invention includes an integrating circuit and a detecting circuit formed by the operational amplifier chip MAX4130EUK-T and the capacitance-resistance device for providing a control voltage for the AGC, and a voltage-controlled gain control circuit: VGA and VCA make the signal amplitude control more acute, and the processed data is effectively sent to a digital baseband for processing. Adjusting the reference voltages Vref1, vref2 of the integrating circuit in fig. 4 can realize gapless connection between two gain control ranges of VGA and VCA.
In a preferred embodiment, the invention adopts an automatic gain control chip AD8367 with a gain range of-2.5 dB to +42.5dB to realize a VGA circuit and a voltage-controlled attenuator RFSA2023 with a gain range of-35 dB to-5 dB to realize a VCA circuit, so that the dynamic range of a VDES receiving load reaches 75dB and far exceeds that of other VDES systems.
Therefore, the AGC structure of the invention can support the uplink signal with the signal intensity between-110 dBm and-35 dBm to carry out AGC adjustment, and simultaneously, the structure supports that the processed data can be effectively sent to a digital baseband for processing.
Claims (6)
1. A satellite-borne VDES receiving load radio frequency channel is characterized by comprising a receiver structure, a phase-locked loop structure, a wide-narrow band switching structure and an AGC structure, wherein the receiver structure comprises AIS1, AIS2, two long-distance AIS channels, ASM1, ASM2 and VDE-SAT 7 receiving channels, the receiver structure comprises a VHF antenna and an LNA component, the receiving signals are filtered and amplified with low noise, down-conversion is realized together with local oscillation signals provided by the phase-locked loop structure, and intermediate frequency signals with high signal-to-noise ratio and low noise coefficient are provided for the follow-up; the phase-locked loop structure comprises a PLL component, the local oscillator signal with high stability and low phase noise is provided for the receiver structure, local oscillator frequency switching is carried out corresponding to each channel in the VDES, and switching and management among different channels are carried out; the wide-band and narrow-band switching structure comprises a radio frequency switch, a wide-band pass filter and a narrow-band pass filter, and the wide-band mode and the narrow-band mode of a switching channel are indicated according to the intensity of the environmental noise; the AGC structure comprises two-stage AGC circuits, namely a VCA circuit and a VGA circuit, and is used for realizing signal amplitude regulation and control and providing structural support for the performance of a large dynamic range of the receiver; the signal enters the baseband processing module through a VHF antenna and LNA component, a VCA circuit, a wide band-pass filter or a narrow band-pass filter and a VGA circuit in sequence,
therefore, after filtering, low-noise amplification, down-conversion, automatic gain control and analog-to-digital conversion are carried out on the received radio frequency signals, the received radio frequency signals are transmitted to a baseband processing module for digital sampling and signal processing, the baseband processing module sends a frequency switching instruction to a single chip microcomputer, a phase-locked loop structure is selectively controlled to switch corresponding local oscillation frequencies, a baseband processor of the baseband processing module sends a switch switching instruction to control a radio frequency control switch to realize the switching between the wide band-pass filter and the narrow band-pass filter,
the 7 receiving channels are combined into one channel, and the channel passes through the broadband filter and the AGC circuit together and enters a baseband processing module for demodulation; or ASM1, ASM2, AIS1, AIS2 are combined into one channel, and in addition, the two channels of long-distance AIS and VDE-SAT are also included, and the two channels pass through the narrow-band filter and the AGC circuit together and enter a baseband processing module for demodulation.
2. The on-board VDES receive payload radio frequency path of claim 1, wherein the phase-locked loop structure comprises a single-chip microcomputer, a phase detector, a frequency divider, a low-pass filter circuit, and a VCO component.
3. The satellite-borne VDES payload radio frequency channel of claim 1, wherein the baseband processing module sends a frequency switch command to the single chip via a 3-bit control line.
4. The satellite-borne VDES receiver load radio frequency channel according to claim 1, wherein the components in the phase-locked loop structure are ADI ADF4360-8BCP chip and PHILIPS single chip P89LPC915FDH.
5. The on-board VDES receiver payload RF path of claim 1, wherein the circuitry of the wide-to-narrow band switching architecture uses the baseband processing module to control the high isolation chip HMC849ALP4CE for SPDT switching, the switch switches to a narrow band IF filter at high level, which is selected from MP04904 and has a bandwidth of 360KHz, and switches to a wide band filter at low level, which is selected from MA05327 and has a bandwidth of 6.7MHz, and the switch default state is low level.
6. The satellite-borne VDES receiver payload radio frequency path of claim 1, wherein the AGC configuration circuit comprises an integrating circuit and a detecting circuit, which are formed by an operational amplifier chip MAX4130EUK-T and a resistance capacitance device, for providing AGC with control voltage, and a voltage-controlled gain control circuit: VGA and VCA enable signal amplitude control to be more acute, processed data are effectively sent to a digital baseband to be processed, an automatic gain control chip AD8367 with the gain range of-2.5 dB to +42.5dB is adopted to realize a VGA circuit, a voltage-controlled attenuator RFSA2023 with the gain range of-35 dB to-5 dB is adopted to realize a VCA circuit, and the dynamic range of a VDES receiving load is enabled to reach 75dB.
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