CN112803922A - Edge modulation transmitter and digital isolator - Google Patents

Edge modulation transmitter and digital isolator Download PDF

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Publication number
CN112803922A
CN112803922A CN202011226532.9A CN202011226532A CN112803922A CN 112803922 A CN112803922 A CN 112803922A CN 202011226532 A CN202011226532 A CN 202011226532A CN 112803922 A CN112803922 A CN 112803922A
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circuit
current detector
input
detection
logic circuit
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Inventor
李立松
方向明
伍荣翔
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Shenzhen Line Easy Microelectronics Co.,Ltd.
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Chongqing Xianyi Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • General Engineering & Computer Science (AREA)
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  • Amplifiers (AREA)

Abstract

The application provides an edge modulation transmitter and a digital isolator, and relates to the technical field of digital circuits. The edge modulation transmitter comprises an encoding control circuit and a common-mode noise detection circuit, the common-mode noise detection circuit comprises at least one multi-stage buffer, at least one current detector and a detection logic circuit, the encoding control circuit comprises an input logic circuit and a pulse extension circuit, the detection logic circuit and a connection circuit of the pulse extension circuit and the at least one multi-stage buffer are connected between the input logic circuit and a drive isolator, each current detector of the at least one current detector is used for sending a current detection signal of the at least one multi-stage buffer to the detection logic circuit, and the pulse extension circuit is connected between the input logic circuit and an output end of the detection logic circuit. When the transmitter detects that large common mode noise occurs in the system, the transmitter carries out adaptive edge modulation through a coding control circuit.

Description

Edge modulation transmitter and digital isolator
Technical Field
The present application relates to the field of digital circuit technology, and more particularly, to an edge modulation transmitter and a digital isolator.
Background
As the digital isolator is mainly used for transmitting digital signals between circuit modules with high voltage difference, the working environment thereof has more noise interference, especially Common Mode noise (CMT), which poses a significant threat to the transmission reliability of the digital isolator signals. The existing pulse-based edge coding and decoding technology is mainly realized by absorbing common-mode current caused by CMT through circuit design in the aspect of CMT interference resistance, but the CMT interference resistance range realized through the method is small, and the signal transmission quality cannot be ensured in some environments.
Disclosure of Invention
In view of the above, an object of the present invention is to provide an edge modulation transmitter and a digital isolator, so as to solve the problem that the CMT interference immunity range in the prior art is small and the signal transmission quality cannot be ensured under some environments.
The embodiment of the application provides an edge modulation transmitter, which comprises an encoding control circuit and a common mode noise detection circuit, wherein the common mode noise detection circuit comprises at least one multi-stage buffer, at least one current detector and a detection logic circuit, the encoding control circuit comprises an input logic circuit and a pulse extension circuit, the connection circuit of the detection logic circuit and the pulse extension circuit and the at least one multi-stage buffer are connected between the input logic circuit and a drive isolator, each current detector of the at least one current detector is used for sending a current detection signal of the at least one multi-stage buffer to the detection logic circuit, and the pulse extension circuit is connected between the input logic circuit and the output end of the detection logic circuit;
when the common mode noise detection circuit detects a common mode noise signal larger than a preset threshold value, the detection logic circuit sends a common mode noise judgment signal to the pulse extension circuit, the pulse extension circuit sends a burst signal to the input logic circuit based on the common mode noise judgment signal and maintains a preset delay, and the input logic circuit sends a pulse signal to the at least one multi-stage buffer when the burst signal starts or ends and continues the preset delay.
In the above implementation manner, the common mode noise detection circuit detects the common mode noise, when the current detector determines that the common mode noise signal received by the multi-stage buffer exceeds a certain range, the CMT detection output synthesized by the detection logic circuit indicates that the receiver circuit may not process the signal normally, and at this time, the transmitter circuit needs to perform adaptive edge modulation, and then, through the pulse extension circuit and the input logic circuit, during the occurrence of the CMT and/or a short period of time after the occurrence of the CMT, the density of the data signal is adaptively increased, and the data pulse is continuously burst for a period of time. Therefore, the absorption capacity of the receiver to common mode current is fully utilized, and in the CMT fading process, once the CMT level is lower than the saturation level of the receiver, normal transmission of signals can be recovered, so that the correctness of signal transmission is maintained, and the influence on signal transmission jitter (jitter) is minimized.
Optionally, the input logic circuit includes a signal input terminal, a signal output terminal and a detection input terminal, the signal input terminal is configured to receive an input signal, the signal output terminal is connected to the input terminal of the at least one multi-stage buffer, the at least one current detector is configured to output the current detection signal of the at least one multi-stage buffer to the detection logic circuit, the output terminal of the detection logic circuit is connected to the input terminal of the pulse extension circuit, the output terminal of the pulse extension circuit is connected to the detection input terminal, and the output terminal of the at least one multi-stage buffer is connected to the receiver through the driving isolator.
In the implementation mode, the current values passing through different multi-stage buffers are detected by different current detectors respectively and transmitted to the detection logic circuit, so that whether the intensity of the common-mode noise influences the system operation or not can be determined under different conduction conditions of the multi-stage buffers.
Optionally, the at least one multi-stage buffer includes a first multi-stage buffer and a second multi-stage buffer, the first multi-stage buffer includes a first MOS transistor and a second MOS transistor, the second multi-stage buffer includes a third MOS transistor and a fourth MOS transistor, the first MOS transistor and the third MOS transistor are N-type, and the second MOS transistor and the fourth MOS transistor are P-type;
the first output end of the input logic circuit is respectively connected with the grids of the first MOS tube and the second MOS tube, the source electrode of the first MOS tube is respectively connected with a VDD power supply and the detection input end, the drain electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube and the first input end of the drive isolator, and the source electrode of the second MOS tube is connected with the detection input end and grounded; the second output end of the input logic circuit is respectively connected with the grid electrodes of the third MOS tube and the fourth MOS tube, the source electrode of the third MOS tube is respectively connected with the VDD power supply and the detection input end, the drain electrode of the third MOS tube is respectively connected with the drain electrode of the fourth MOS tube and the second input end of the drive isolator, and the source electrode of the fourth MOS tube is connected with the detection input end and grounded.
In the implementation mode, each multistage buffer is composed of two MOS transistors, when the voltage on one side of the transmitter rises or falls, the current for driving the isolator is the differential mode current of normal operation when no CMT event occurs, and no matter the voltage of the transmitter rises or falls when the CMT event occurs, one current in the four MOS transistors is always higher than the common mode current value when the four MOS transistors normally operate, so that the common mode noise signal detection under different states is realized.
Optionally, the at least one current detector comprises a first current detector, a second current detector, a third current detector, and a fourth current detector;
the first current detector is connected with a source electrode of the first MOS tube, the second current detector is connected with a source electrode of the second MOS tube, the third current detector is connected with a source electrode of the third MOS tube, the fourth current detector is connected with a source electrode of the fourth MOS tube, and output ends of the first current detector, the second current detector, the third current detector and the fourth current detector are respectively connected with a first input end, a second input end, a third input end and a fourth input end of an input end of the detection logic circuit.
In the implementation mode, four MOS tubes are matched, four current detectors are adopted for current detection, the detection result is output to the detection logic circuit, the currents of the four MOS tubes in different conduction states can be completely monitored, and therefore the common-mode current caused by the common-mode noise is accurately detected.
Optionally, the first current detector includes a first resistor and a first comparator, the first resistor is connected between the source of the first MOS transistor and a VDD power supply, two input ends of the first comparator are respectively connected to two ends of the first resistor, and an output end of the first comparator is connected to the first input end of the detection logic circuit;
the second current detector comprises a second resistor and a second comparator, the source electrode of the second MOS tube is grounded through the second resistor, two input ends of the second comparator are respectively connected with two ends of the second resistor, and the output end of the second comparator is connected with the second input end of the detection logic circuit;
the third current detector comprises a third resistor and a third comparator, the third current detector is connected in the same way as the first current detector, and the output end of the third comparator is connected with the third input end of the detection logic circuit;
the fourth current detector comprises a fourth resistor and a fourth comparator, the connection mode of the fourth current detector is the same as that of the second current detector, and the output end of the fourth comparator is connected with the fourth input end of the detection logic circuit;
the first comparator, the second comparator, the third comparator, and the fourth comparator have a threshold comparison function, and output a first logic when the detected current is greater than or equal to a first threshold, and output a second logic when the detected current is less than a second threshold.
In the implementation mode, each current detector detects the current of the MOS tube through the resistor connected to the source electrode of the MOS tube, and then the comparator determines whether the current is larger than the threshold value influencing the normal operation of the system, so that the pulse modulation can be performed through the coding control circuit when the common-mode noise is large.
Optionally, the first threshold is greater than or equal to the second threshold.
Optionally, the detection logic circuit is a four-input or gate.
In the implementation manner, the detection logic circuit is a four-input or gate, and can detect the currents of the four MOS transistors to determine the common mode current in cooperation with the current detection signals output by the four current detectors.
The embodiment of the present application further provides a digital isolator, where the digital isolator includes the edge modulation transmitter, a driving isolator, and a receiver, the receiver includes a comparator circuit and a latch, an output end of the driving isolator is connected to an input end of the comparator circuit, an output end of the comparator circuit is connected to an input end of the latch, and an output end of the latch is an output end of the digital isolator;
the comparator circuit compares the output signals of the driving isolator, when the output signals of the driving isolator are pulses with a first polarity, the latch is set to be in a first logic latch state, the output end of the latch outputs first logic, when the output signals of the driving isolator are pulses with a second polarity, the latch is set to be in a second logic latch state, and the output end of the latch outputs second logic.
In the implementation mode, the logic latch state switching is carried out through the latch which can be triggered by a single pulse, and the CMT interference resistant stable output of the digital signal is realized.
Optionally, the driving isolator is a differential capacitor pair formed by a pair of capacitors, or a transformer formed by two mutually coupled coils.
In the implementation mode, the input signal is converted and output by driving the isolator, and signal interference and transmission distortion are reduced.
Optionally, the receiver further comprises a resistor-capacitor circuit connected between the drive isolator and the comparator circuit.
In the implementation mode, the waveform of the output signal of the driving isolator is adjusted through the resistor-capacitor circuit, and the output accuracy of the digital signal is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a digital isolator according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of an edge modulation transmitter according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of an operating signal of a conventional transmitter that does not employ the adaptive edge modulation technique according to an embodiment of the present application.
Fig. 4 is a schematic diagram of an operating signal of a conventional edge modulation transmitter using an adaptive edge modulation technique according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of two types of driving isolators according to an embodiment of the present application.
Icon: 10-a digital isolator; 11-edge modulated emitter; 111-a coding control circuit; 1111-input logic circuit; 1112-a pulse extension circuit; 112-common mode noise detection circuitry; 1121-detection logic; 1122-a first multi-level buffer; 1123-a second multi-level buffer; 1124-a first current detector; 1125-a second current detector; 1126 — a third current detector; 1127-a fourth current detector; 12-a drive isolator; 13-a receiver; 131-a comparator circuit; 132-a latch; 133-resistor-capacitor circuit.
Detailed Description
The technical solution in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
First, the digital isolator is introduced from a digital isolator, which is a chip that enables an electronic system to have a high voltage-resistant isolation characteristic when a digital signal and an analog signal are transmitted in the electronic system, so as to achieve isolation between the electronic systems, and the common mode noise has a large influence on the transmission reliability of the digital isolator signal, whereas the digital isolator in the prior art has a small CMT interference resistance range and cannot ensure signal transmission quality in some environments, so the embodiment provides a digital isolator 10 to solve the above problems.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a digital isolator according to an embodiment of the present disclosure.
The digital isolator 10 includes an edge modulation transmitter 11, a drive isolator 12, and a receiver 13, the edge modulation transmitter 11 being electrically connected to the receiver 13 through the drive isolator 12.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an edge modulation transmitter according to an embodiment of the present disclosure.
The edge modulation transmitter 11 includes an encoding control circuit 111 and a common mode noise detection circuit 112, wherein the common mode noise detection circuit 112 includes an input logic circuit 1111 and a pulse extension circuit 1112, and the common mode noise detection circuit 112 includes at least one multi-stage buffer, at least one current detector and detection logic circuit 1121.
A series circuit of the detection logic circuit 1121 and the pulse lengthening circuit 1112, at least one multi-stage buffer connected in parallel between the input logic circuit 1111 and the driving isolator 12, at least one current detector each for sending a current detection signal of the at least one multi-stage buffer to the detection logic circuit 1121, and the pulse lengthening circuit 1112 connected in series between the input logic circuit 1111 and the output terminal of the detection logic circuit 1121.
Specifically, the input logic circuit 1111 includes a signal input terminal, a signal output terminal, and a detection input terminal, the signal input terminal is configured to receive an input signal, the signal output terminal is connected to the input terminal of the at least one multi-stage buffer, the at least one current detector is configured to output a current detection signal of the at least one multi-stage buffer to the detection logic circuit 1121, the output terminal of the detection logic circuit 1121 is connected to the input terminal of the pulse lengthening circuit 1112, the output terminal of the pulse lengthening circuit 1112 is connected to the detection input terminal, and the output terminal of the at least one multi-stage buffer is connected to the receiver 13 through the driving isolator 12.
Alternatively, there may be two at least one multi-stage buffers in this embodiment, each of which is connected to one signal output terminal of the input logic circuit 1111, specifically, the first multi-stage buffer 1122 is connected to a first output terminal of the input logic circuit 1111, and the second multi-stage buffer 1123 is connected to a second output terminal of the input logic circuit 1111.
The first multistage buffer 1122 may be composed of a first MOS transistor M1 and a second MOS transistor M2, and the second multistage buffer 1123 may be composed of a third MOS transistor M3 and a fourth MOS transistor M4. The first MOS transistor M1 and the third MOS transistor M3 are N-type, and the second MOS transistor M2 and the fourth MOS transistor M4 are P-type.
Specifically, a first output end of the input logic circuit 1111 is connected to gates of the first MOS transistor M1 and the second MOS transistor M2, a source of the first MOS transistor M1 is connected to the VDD power supply and the detection input end, a drain of the first MOS transistor M1 is connected to a drain of the second MOS transistor M2 and the first input end of the driving isolator 12, and a source of the second MOS transistor M2 is connected to the detection input end and grounded; the second output end of the input logic circuit 1111 is connected to the gates of the third MOS transistor M3 and the fourth MOS transistor M4, the source of the third MOS transistor M3 is connected to the VDD power supply and the detection input end, the drain of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4 and the second input end of the driving isolator 12, and the source of the fourth MOS transistor M4 is connected to the detection input end and grounded.
The digital isolator 10 will have the following MOS transistor states:
when no CMT event has occurred,
(1) m1 and M4 are turned on, M2 and M3 are turned off, the current of the driving isolator 12 flows back to GND from VDD through the driving isolator 12 and the fourth MOS transistor M4, and the current is the differential mode current Id of normal operation;
(2) m2 and M3 are turned on, M1 and M4 are turned off, the current of the driving isolator 12 flows back to GND from VDD through the third MOS tube M3, the driving isolator 12 and the second MOS tube M2, and the current is the differential mode current Id of normal operation;
when a CMT event occurs in which the common mode current exceeds a threshold,
(3) m1 and M4 are turned on, M2 and M3 are turned off,
3.1) the voltage on one side of the edge modulation transmitter 11 rises, i.e. the common mode current flows from the left side to the right side, so the current of the first MOS transistor M1 increases, the current of the fourth MOS transistor M4 decreases, and the variable is the common mode current Ic;
3.2) the voltage on the side of the edge modulation transmitter 11 is reduced, i.e. the common mode current flows from the right side to the left side, so the current of the first MOS transistor M1 is reduced, the current of the fourth MOS transistor M4 is increased, and the variable is the common mode current Ic;
(4) m2 and M3 are turned on, M1 and M4 are turned off,
4.1) edge modulation emitter 11 side voltage rises, i.e. common mode current flows from left to right, so the current of the third MOS transistor M3 increases, the current of the second MOS transistor M2 decreases, and the variable is common mode current Ic;
4.2) edge modulation emitter 11 side voltage drops, i.e. common mode current flows from right to left, so the current of the third MOS transistor M3 decreases, the current of the second MOS transistor M2 increases, and the variable is the common mode current Ic.
The current conditions for the above several cases can be shown in the following table (all with positive current in the direction from top to bottom in fig. 2):
Figure RE-GDA0003014228660000091
the above table is a schematic illustration, and in the case of a very large CMT current, the body diode of the turned-off MOS transistor may participate in the conduction of the common mode current, but this phenomenon does not affect the operation principle of the present embodiment, and does not limit the content of the present embodiment.
It can be seen from the above table that regardless of the combination of the conducting MOS transistors and the direction of the CMT current, the current of one MOS transistor is higher than that of the normal operation by Ic, i.e. reaches the level of Id + Ic. When the CMT current is small, Ic is small and does not affect the operation of the system within the processing range of the receiver 13. However, when the CMT current is large (the value of dV/dt is large, such as in tens or hundreds of kV/us), the receiver 13 may not be able to process the signal normally, and the adaptive edge modulation by the edge modulation transmitter 11 is required.
In cooperation with the multi-stage buffer composed of the MOS transistors provided in this embodiment, the at least one current detector may include a first current detector 1124, a second current detector 1125, a third current detector 1126, and a fourth current detector 1127.
Specifically, the first current detector 1124 is connected in series to a source of the first MOS transistor M1, the second current detector 1125 is connected in series to a source of the second MOS transistor M2, the third current detector 1126 is connected in series to a source of the third MOS transistor M3, the fourth current detector 1127 is connected in series to a source of the fourth MOS transistor M4, and output terminals of the first current detector 1124, the second current detector 1125, the third current detector 1126, and the fourth current detector 1127 are connected to first, second, third, and fourth input terminals among input terminals of the detection logic circuit 1121, respectively.
It should be understood that the current detector in this embodiment is only required to measure the source passing current of the MOS transistor, and the illustrated position is only an illustration and is not a limitation to the embodiment.
A specific structure of the current detector is explained below, and a specific structure schematic diagram of the current detector is shown in a dashed square frame in fig. 2, and specific structures of the first current detector 1124, the second current detector 1125, the third current detector 1126, and the fourth current detector 1127 in this embodiment may be the same, and are only different input ends of the detection logic circuit 1121 which are input to a final output end, and only the first current detector 1124 is exemplified below, and other current detectors are not described again.
The first current detector 1124 includes a first resistor R1 and a first comparator C1, the first resistor R1 is connected in series between the source of the first MOS transistor M1 and the VDD power supply, two input terminals of the first comparator C1 are respectively connected to two ends of the first resistor R1, and an output terminal of the first comparator C1 is connected to a first input terminal of the detection logic circuit 1121.
The first comparator C1, the second comparator C2, the third comparator C3, and the fourth comparator C4 have a threshold comparison function, and output a first logic when the detection current is greater than or equal to a first threshold value and output a second logic when the detection current is less than a second threshold value.
The first logic and the second logic are level logic 0 or 1 in the digital circuit, and one of the first logic and the second logic is 0 and the other is 1, and the embodiment is explained with the first logic being 1 and the second logic being 2.
Optionally, the first threshold is greater than or equal to the second threshold, when the output value of the current detector is greater than the first threshold, it indicates that the common mode current may affect the normal signal processing of the receiver 13, and adaptive edge modulation is required by the edge modulation transmitter 11, and when the output value of the current detector is less than or equal to the second threshold, it indicates that the common mode current is within the processing range of the receiver 13, and the operation of the system is not affected.
Alternatively, the first threshold may be a value that the value of dV/dt exceeds the normal operating range of the electronic system, and the first threshold may be flexibly adjusted according to the actual situation of the electronic system, such as 10kV/us, 20kV/us, 50kV/us, 100kV/us, 200kV/us, and so on.
Alternatively, in this embodiment, the detection outputs of the first current detector 1124, the second current detector 1125, the third current detector 1126 and the fourth current detector 1127 are processed by the detection logic circuit 1121 to output a common mode noise determination signal, i.e., a first logic (1 in this embodiment) or a second logic (0 in this embodiment), and in this embodiment, the first logic may be used as the common mode noise determination signal to indicate that the CMT current value is too large and needs to be pulse modulated.
Alternatively, the detection logic 1121 may be a 4-input or gate to output a first logic to the pulse lengthening circuit 1112 when a current detection result transmitted from any one of the first current detector 1124, the second current detector 1125, the third current detector 1126 and the fourth current detector 1127 is a first logic. It should be understood that those skilled in the art may vary the output of the current detector and the corresponding logic of the detection logic 1121 to achieve equivalent results.
The common mode noise determination signal enters the pulse extension circuit 1112, and a Burst signal (Burst) output from the pulse extension circuit controls the input logic circuit 1111 to continuously transmit a pulse signal to the first output terminal or the second output terminal of the signal output terminal according to the current input level.
The pulse signal in this embodiment can adopt two modes:
(1) after the common mode noise judgment signal is ended, maintaining the preset time delay, and then ending, wherein the preset time delay is not less than the width of a data pulse signal;
(2) and starting when the common mode noise judgment signal starts, maintaining the preset delay after the common mode noise judgment signal is ended, and then ending, wherein the preset delay is not less than the width of one data pulse signal.
The following compares the situation without the adaptive edge modulation technique with the working situation with the adaptive edge modulation technique provided by the present embodiment with reference to fig. 3 and 4.
Referring to fig. 3, fig. 3 is a schematic diagram of an operating signal of a conventional transmitter without using the adaptive edge modulation technique according to an embodiment of the present invention.
When a CMT event occurs, the first output terminal S1 of the input logic 1111 is transmitting a pulse a1 to the receiver, and since the common mode current caused by the CMT event exceeds the absorption capability of the receiver 13, the pulse a2 that should be present at the receiver 13 cannot be detected by the receiver 13, the corresponding output signal is in error, and the high level A3 at the input terminal is not successfully transmitted to the output terminal. Where S2 denotes a second output terminal of the input logic circuit 1111.
Referring to fig. 4, fig. 4 is a schematic diagram of an operating signal of a conventional edge modulation transmitter using an adaptive edge modulation technique according to an embodiment of the present application.
After the CMT event occurs, the detection logic 1121 outputs the common mode noise decision signal a4 and triggers the corresponding burst signal a5, and the duration of a5 is from the start of the common mode noise decision signal a4 to the end of the common mode noise decision signal a4, and then the preset delay a6 is maintained. During the signal a5, the first output terminal S1 and the second output terminal S2 of the input logic 1111 will continue to transmit pulse signals, as shown by a7 and A8. During the CMT event, the pulse a9 and the pulse a10 are not recognized by the receiver 13 because their common mode current exceeds the absorption capacity of the receiver 13, and the burst signal a5 also maintains the preset delay a6 after the CMT event ends, so that the pulse a11 transmitted during this time is recognized by the receiver 13, and thus a correct output can be made at the output. As can be seen here, the delay of burst signal a5 after common mode noise decision signal a4 should not be less than the width of 1 signal pulse.
Optionally, the drive buffer of drive isolator 12 may also provide a feedback signal to input logic 1111, and different embodiments may depend on the logic design of input logic 1111 and its cooperation with the drive buffer feedback signal of drive isolator 12.
Next, the driving isolator 12 and the receiver 13 of the digital isolator 10 will be described in detail.
Referring to fig. 5, fig. 5 is a schematic structural diagram of two types of driving isolators according to an embodiment of the present disclosure.
The driving isolator 12 is a differential capacitor pair formed by a pair of capacitors as shown in the left diagram of fig. 5, or a transformer formed by two mutually coupled coils as shown in the right diagram of fig. 5.
Receiver 13 includes comparator circuit 131 and latch 132, the output of driver isolator 12 is connected to the input of comparator circuit 131, the output of comparator circuit 131 is connected to the input of latch 132, and the output of latch 132 is the output of digital isolator 10.
Optionally, the receiver 13 may further include a resistor-capacitor (RS) circuit 133 connected in series between the driving isolator 12 and the comparator circuit 131 for adjusting the received waveform, and the specific adjustment method is not essential to the present invention and therefore will not be described in detail.
Specifically, the comparator circuit 131 includes a fifth comparator C5 and a sixth comparator C6, a positive phase input terminal of the fifth comparator C5 is connected to a negative phase input terminal of the sixth comparator C6 and the first output terminal of the resistor-capacitor circuit 133, respectively, and a negative phase input terminal of the fifth comparator C5 is connected to a positive phase input terminal of the sixth comparator C6 and the second output terminal of the resistor-capacitor circuit 133, respectively.
Latch 132 may be an R-S latch, an output terminal of fifth comparator C5 is connected to an S terminal of latch 132, an output terminal of sixth comparator C6 is connected to an R terminal of latch 132, and a Q terminal of latch 132 is a signal output terminal of digital isolator 10.
In summary, the embodiments of the present application provide an edge modulation transmitter and a digital isolator, where the edge modulation transmitter includes an encoding control circuit and a common mode noise detection circuit, the common mode noise detection circuit comprises at least one multi-stage buffer, at least one current detector and detection logic, the encoding control circuit comprises an input logic circuit and a pulse extension circuit, the serial circuit of the detection logic circuit and the pulse extension circuit and the at least one multi-stage buffer are connected in parallel between the input logic circuit and the drive isolator, each current detector of the at least one current detector is for sending a current detection signal of the at least one multi-stage buffer to the detection logic circuit, the pulse extension circuit is connected in series between the input logic circuit and the output end of the detection logic circuit;
when the common mode noise detection circuit detects a common mode noise signal larger than a preset threshold value, the detection logic circuit sends a common mode noise judgment signal to the pulse extension circuit, the pulse extension circuit sends a burst signal to the input logic circuit based on the common mode noise judgment signal and maintains a preset delay, and the input logic circuit sends a pulse signal to the at least one multi-stage buffer when the burst signal starts or ends and continues the preset delay.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The apparatus embodiments described above are merely illustrative, and for example, the block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of devices according to various embodiments of the present application.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims (10)

1. An edge modulation transmitter, comprising an encoding control circuit and a common mode noise detection circuit, wherein the common mode noise detection circuit comprises at least one multi-stage buffer, at least one current detector and a detection logic circuit, wherein the encoding control circuit comprises an input logic circuit and a pulse extension circuit, wherein the connection circuit of the detection logic circuit and the pulse extension circuit, the at least one multi-stage buffer are connected between the input logic circuit and a drive isolator, each current detector of the at least one current detector is used for sending a current detection signal of the at least one multi-stage buffer to the detection logic circuit, and the pulse extension circuit is connected between the input logic circuit and an output end of the detection logic circuit;
when the common mode noise detection circuit detects a common mode noise signal larger than a preset threshold value, the detection logic circuit sends a common mode noise judgment signal to the pulse extension circuit, the pulse extension circuit sends a burst signal to the input logic circuit based on the common mode noise judgment signal and maintains a preset delay, and the input logic circuit sends a pulse signal to the at least one multi-stage buffer when the burst signal starts or ends and continues the preset delay.
2. The edge modulation transmitter of claim 1 wherein the input logic circuit comprises a signal input for receiving an input signal, a signal output connected to an input of the at least one multi-stage buffer, and a detection input, wherein the at least one current detector is configured to output the current detection signal of the at least one multi-stage buffer to the detection logic circuit, wherein an output of the detection logic circuit is connected to an input of the pulse extension circuit, wherein an output of the pulse extension circuit is connected to the detection input, and wherein an output of the at least one multi-stage buffer is connected to a receiver through the drive isolator.
3. The edge modulation transmitter of claim 2, wherein the at least one multi-stage buffer comprises a first multi-stage buffer and a second multi-stage buffer, the first multi-stage buffer comprises a first MOS transistor and a second MOS transistor, the second multi-stage buffer comprises a third MOS transistor and a fourth MOS transistor, the first MOS transistor and the third MOS transistor are N-type, and the second MOS transistor and the fourth MOS transistor are P-type;
the first output end of the input logic circuit is respectively connected with the grids of the first MOS tube and the second MOS tube, the source electrode of the first MOS tube is respectively connected with a VDD power supply and the detection input end, the drain electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube and the first input end of the drive isolator, and the source electrode of the second MOS tube is connected with the detection input end and grounded; the second output end of the input logic circuit is respectively connected with the grid electrodes of the third MOS tube and the fourth MOS tube, the source electrode of the third MOS tube is respectively connected with the VDD power supply and the detection input end, the drain electrode of the third MOS tube is respectively connected with the drain electrode of the fourth MOS tube and the second input end of the drive isolator, and the source electrode of the fourth MOS tube is connected with the detection input end and grounded.
4. The edge modulation emitter of claim 3 wherein the at least one current detector comprises a first current detector, a second current detector, a third current detector, and a fourth current detector;
the first current detector is connected with a source electrode of the first MOS tube, the second current detector is connected with a source electrode of the second MOS tube, the third current detector is connected with a source electrode of the third MOS tube, the fourth current detector is connected with a source electrode of the fourth MOS tube, and output ends of the first current detector, the second current detector, the third current detector and the fourth current detector are respectively connected with a first input end, a second input end, a third input end and a fourth input end of an input end of the detection logic circuit.
5. The edge modulation transmitter of claim 4, wherein the first current detector comprises a first resistor and a first comparator, the first resistor is connected between the source of the first MOS transistor and a VDD power supply, two input terminals of the first comparator are respectively connected with two ends of the first resistor, and an output terminal of the first comparator is connected with a first input terminal of the detection logic circuit;
the second current detector comprises a second resistor and a second comparator, the source electrode of the second MOS tube is grounded through the second resistor, two input ends of the second comparator are respectively connected with two ends of the second resistor, and the output end of the second comparator is connected with the second input end of the detection logic circuit;
the third current detector comprises a third resistor and a third comparator, the third current detector is connected in the same way as the first current detector, and the output end of the third comparator is connected with the third input end of the detection logic circuit;
the fourth current detector comprises a fourth resistor and a fourth comparator, the connection mode of the fourth current detector is the same as that of the second current detector, and the output end of the fourth comparator is connected with the fourth input end of the detection logic circuit;
the first comparator, the second comparator, the third comparator, and the fourth comparator have a threshold comparison function, and output a first logic when the detected current is greater than or equal to a first threshold, and output a second logic when the detected current is less than a second threshold.
6. The edge modulation transmitter of claim 5 wherein the first threshold is greater than or equal to the second threshold.
7. The edge modulated transmitter of claim 5 wherein the detection logic is a four input OR gate.
8. A digital isolator comprising an edge modulated transmitter as claimed in any one of claims 1 to 7, a driven isolator and a receiver, the receiver comprising a comparator circuit and a latch, an output of the driven isolator being connected to an input of the comparator circuit, an output of the comparator circuit being connected to an input of the latch, an output of the latch being an output of the digital isolator;
the comparator circuit compares the output signals of the driving isolator, when the output signals of the driving isolator are pulses with a first polarity, the latch is set to be in a first logic latch state, the output end of the latch outputs first logic, when the output signals of the driving isolator are pulses with a second polarity, the latch is set to be in a second logic latch state, and the output end of the latch outputs second logic.
9. The digital isolator according to claim 8, wherein the driving isolator is a differential capacitor pair formed by a pair of capacitors or a transformer formed by two mutually coupled coils.
10. The digital isolator of claim 8, wherein the receiver further comprises a resistor-capacitor circuit connected between the drive isolator and the comparator circuit.
CN202011226532.9A 2020-11-05 2020-11-05 Edge modulation transmitter and digital isolator Pending CN112803922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011226532.9A CN112803922A (en) 2020-11-05 2020-11-05 Edge modulation transmitter and digital isolator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011226532.9A CN112803922A (en) 2020-11-05 2020-11-05 Edge modulation transmitter and digital isolator

Publications (1)

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CN112803922A true CN112803922A (en) 2021-05-14

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Country Link
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