CN112803912A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN112803912A CN112803912A CN202110299699.6A CN202110299699A CN112803912A CN 112803912 A CN112803912 A CN 112803912A CN 202110299699 A CN202110299699 A CN 202110299699A CN 112803912 A CN112803912 A CN 112803912A
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- 238000000034 method Methods 0.000 title claims abstract description 145
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 81
- 238000005530 etching Methods 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 33
- 239000007772 electrode material Substances 0.000 claims description 31
- 239000007769 metal material Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 238000002360 preparation method Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
- H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
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- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
The invention provides a semiconductor device and a forming method thereof. The metal ring is prepared preferentially, so that the piezoelectric layer covers the metal ring, the metal ring is not exposed out of the surface of the piezoelectric layer, the metal ring is prevented from being damaged when the mass load layer is prepared, the process limitation of the mass load layer can be effectively improved, the flexible adjustment of the sequence of the mass load layer and the upper electrode layer is facilitated, and the manufacturing efficiency of the device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
A crystal oscillator and a filter (for example, a bulk acoustic wave filter) can be further generally configured by applying a resonant structure made of a piezoelectric material having an inverse piezoelectric effect to a semiconductor device. The resonant structure of the semiconductor device generally includes an upper electrode, a lower electrode, and a piezoelectric layer sandwiched between the upper electrode and the lower electrode, and at present, in order to prepare resonant structures with different frequencies, a mass loading layer is usually further provided, and the frequency adjustment of the resonant structure is further realized by adjusting the thickness of the mass loading layer. In addition, in order to raise the Q value of the device, an alternative method is to attach a metal ring around the resonant structure.
In a semiconductor device for practical use, it is common that a mass loading layer is provided in a partial resonance structure and a mass loading layer is not provided in a partial resonance structure, or that the mass loading layers in different resonance structures have different thicknesses. At this time, in the case of manufacturing a semiconductor device having such a structure, there are problems that the manufacturing difficulty is large and the manufacturing process is limited, for example, it is difficult to directly form a mass loading layer in an individual resonance region by using an etching process.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor device, which aims to solve the problems of high preparation difficulty and inflexible process of the existing forming method.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein at least one resonance area is arranged on the substrate; forming a lower electrode layer and a metal ring in each resonance area of the substrate, wherein the metal ring surrounds the edge of the resonance area and is positioned in the area range of the lower electrode layer; forming a piezoelectric layer on the substrate, the piezoelectric layer covering the lower electrode layer and the metal ring; and forming an upper electrode layer and a mass loading layer on the piezoelectric layer, wherein the upper electrode layer is formed in each resonance region, and the mass loading layer is formed in at least one resonance region.
Optionally, the method for forming the lower electrode layer and the metal ring includes: preferentially forming a metal ring at the edge of the resonance area; and then, forming a lower electrode layer, and enabling the lower electrode layer to cover the metal ring.
Optionally, the method for forming the upper electrode layer and the mass loading layer includes: forming a mass loading layer in the at least one resonance region using an etching process or a lift-off process; and forming an upper electrode layer in each resonance region, the upper electrode layer covering the mass loading layer.
Optionally, if the thickness of the mass loading layer is less than or equal to 1000 angstroms, forming the mass loading layer by using an etching process or a stripping process; or, if the thickness of the mass loading layer is more than 1000 angstroms, the mass loading layer is formed by utilizing an etching process.
Optionally, the method for forming the upper electrode layer and the mass loading layer includes: forming a layer of upper electrode material on the piezoelectric layer; forming a mass loading layer in the at least one resonance region using a lift-off process, the mass loading layer being formed on the upper electrode material layer; and performing an etching process on the upper electrode material layer to form the upper electrode layer in each resonance region.
Optionally, the mass loading layer has a thickness of less than 1000 angstroms.
Optionally, when the thickness of the mass loading layer is less than or equal to 1000 angstroms, forming the mass loading layer below the upper electrode layer by using an etching process or a lift-off process, or forming the mass loading layer above the upper electrode layer by using a lift-off process; and when the thickness of the mass loading layer is more than 1000 angstroms, forming the mass loading layer below the upper electrode layer by utilizing an etching process.
Optionally, the substrate has a first resonance region and a second resonance region, the mass loading layer is formed in each of the first resonance region and the second resonance region, and a thickness of the mass loading layer in the first resonance region is greater than a thickness of the mass loading layer in the second resonance region.
Optionally, the method for forming the upper electrode layer and the mass loading layer includes: forming a mass loading layer in the first resonance region by using an etching process; forming a layer of upper electrode material overlying the mass loading layer and the exposed piezoelectric layer in the first resonance region; forming a mass loading layer in the second resonance region using a lift-off process, and a mass loading layer in the second resonance region is formed on the upper electrode material layer; and performing an etching process on the upper electrode material layer to form upper electrode layers in the respective resonance regions.
Optionally, an end portion of the upper electrode layer covers directly above the metal ring.
Optionally, the upper electrode layer, the mass loading layer and the metal ring all comprise the same metal material.
Still another object of the present invention is to provide a semiconductor device comprising: a substrate having at least one resonant region thereon; a lower electrode layer disposed at least in each of the resonance regions; the metal ring surrounds the edge of each resonance area and is positioned in the area range of the lower electrode layer; a piezoelectric layer covering the lower electrode layer and the metal ring; an upper electrode layer disposed in each of the resonance regions; and a mass loading layer disposed in at least one resonance region, and the upper electrode layer and the mass loading layer are stacked and disposed on the piezoelectric layer in the at least one resonance region.
Optionally, the lower electrode layer covers the metal ring.
Optionally, the mass loading layer has a thickness greater than 1000 angstroms and is disposed below the upper electrode layer; alternatively, the mass loading layer has a thickness of 1000 angstroms or less and is disposed below or above the upper electrode layer.
Optionally, the substrate has a first resonance region and a second resonance region, the mass loading layer is formed in each of the first resonance region and the second resonance region, and a thickness of the mass loading layer in the first resonance region is greater than a thickness of the mass loading layer in the second resonance region.
Optionally, the mass loading layer in the first resonance region is disposed below the upper electrode layer, and the mass loading layer in the second resonance region is disposed above the upper electrode layer.
In the method for forming a semiconductor device provided by the present invention, the metal ring is prepared prior to the piezoelectric layer, so that the metal ring is not exposed under the coverage of the piezoelectric layer, and when the upper electrode layer and the mass loading layer are prepared on the piezoelectric layer, the process limitation of the mass loading layer can be effectively improved, including: the preparation process of the mass loading layer is not limited to the stripping process, and the mass loading layer can be formed by adopting an etching process without causing etching damage to the metal ring. Particularly, for a mass loading layer with larger thickness, the etching process is allowed to be applied, so that the preparation difficulty of the mass loading layer is reduced, and the quality of the mass loading layer is improved. In the forming method provided by the invention, the flexible adjustment of the preparation sequence of the mass loading layer and the upper electrode layer can be realized, and the manufacturing efficiency of the device is improved.
Drawings
Fig. 1 and 2 are schematic structural views of a method of forming a semiconductor device during its fabrication.
Fig. 3 is a schematic flow chart of a method for forming a semiconductor device according to the present invention.
Fig. 4 to 8 are schematic structural diagrams of a method for forming a semiconductor device in a first embodiment of the invention during a manufacturing process thereof.
Fig. 9 is a schematic structural view of a semiconductor device in a second embodiment of the present invention.
Wherein the reference numbers are as follows:
10/100-a substrate;
110 a-a cavity;
110-a sacrificial layer;
10A/100A-first resonance region;
10B/100B-second resonance region;
21/210-lower electrode layer;
22/220-a piezoelectric layer;
23' -a layer of electrode material;
23/230 — upper electrode layer;
24/240-metal ring;
25/250/250a/250 b-mass loading layer.
Detailed Description
As described in the background art, for the resonant structure provided with the metal ring and the mass loading layer, the manufacturing process is difficult to be compatible, and the manufacturing method thereof needs to be improved. Referring specifically to fig. 1 and 2, a method of forming a semiconductor device includes the following steps, for example.
First, a lower electrode layer 21 is formed on the resonance region of the substrate 10. Fig. 1 schematically shows a first resonance region 10A and a second resonance region 10B where a resonance structure needs to be formed, and a lower electrode layer 21 is formed on both the first resonance region 10A and the second resonance region 10B.
In a second step, a piezoelectric layer 22 is formed on the substrate 10.
In a third step, a metal ring 24 is formed on the piezoelectric layer 22 of the resonance area. In fig. 1, a metal ring 24 is formed on the piezoelectric layer 22 of each of the first resonance area 10A and the second resonance area 10B.
A fourth step of forming an upper electrode layer 23 and a mass loading layer 25 on the piezoelectric layer 22. Specifically, the upper electrode layer 23 is formed on each resonance region (i.e., the first resonance region 10A and the second resonance region 10B), and the mass loading layer 25 is formed on at least a part of the resonance region (e.g., the first resonance region 10A shown in fig. 2). Based on this, the resonance frequency of the resonance structure on the first resonance region 10A can be made different from the resonance frequency of the resonance structure on the second resonance region 10B.
In the above-described manufacturing method, it is considered that the mass loading layer 25 does not need to be formed in a part of the resonance region (for example, the mass loading layer is not provided in the second resonance region 10B), and therefore, if the mass loading layer 25 is preferentially formed in the first resonance region 10A by the etching process, the metal ring 24 in the second resonance region 10B is inevitably damaged. In view of this, it is common practice to first form an electrode material layer 23 'and cover the metal ring 24, and then form a mass loading layer 25 on the electrode material layer 23', as shown in fig. 1 and 2. Similarly, since the mass loading layer is not required to be formed in the second resonance region 10B, when the material of the mass loading layer in the second resonance region 10B is removed by the etching process, the electrode material layer 23 'therebelow is damaged, and for this reason, the mass loading layer 25 can only be formed by the lift-off process, so as to avoid etching damage to the electrode material layer 23' in the second resonance region 10B. However, there are many process limitations in preparing the mass-supporting layer 25 using a lift-off process, such as difficulty in controlling the lift-off process when preparing a mass-supporting layer having a large thickness.
It can be seen that, in the preparation method as described above, the preparation process and preparation sequence of the mass-carrying layer are greatly limited, and especially for the mass-carrying layer with a large thickness, the problem of poor process compatibility still exists.
Therefore, the invention provides a forming method of a semiconductor device, which aims to improve the process limitation of a mass loading layer, so that the mass loading layer can be formed by adopting a stripping process and an etching process, the quality of the mass loading layer is improved, the problem that the process of the mass loading layer with larger thickness is difficult to be compatible is solved, the flexible adjustment of the preparation sequence of the mass loading layer and an upper electrode layer is facilitated, and the manufacturing efficiency of the device is improved. Referring specifically to fig. 3, the method for forming a semiconductor device according to the present invention may include the following steps.
Step S100, providing a substrate having at least one resonance region thereon.
Step S200, forming a lower electrode layer and a metal ring in each resonance area of the substrate, wherein the metal ring surrounds the edge of the resonance area and is located in the area range of the lower electrode layer.
Step S300, forming a piezoelectric layer on the substrate, wherein the piezoelectric layer covers the lower electrode layer and the metal ring.
Step S400, forming an upper electrode layer and a mass loading layer on the piezoelectric layer, wherein the upper electrode layer is formed in each resonance region and the mass loading layer is formed in at least one resonance region.
The semiconductor device and the method for forming the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It will be understood that relative terms, such as "above," "below," "top," "bottom," "above," and "below," may be used in relation to various elements shown in the figures. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.
< example one >
In this embodiment, a method for forming a semiconductor device will be explained by taking an example in which a mass loading layer is provided in a part of a resonance region and a mass loading layer is not provided in another part of the resonance region.
In step S100, referring to fig. 4 in particular, a substrate 100 is provided, where the substrate 100 has at least one resonance region, and the resonance region is a region for forming a resonance structure. In this embodiment, only two resonance regions are illustrated as an example for explanation, and as shown in fig. 4, the substrate 100 has a first resonance region 100A and a second resonance region 100B.
Wherein the substrate 100 may be adjusted accordingly depending on the particular application of the semiconductor device being formed. For example, the semiconductor device may be a Bulk Acoustic Wave (BAW) filter, in which case the substrate may include multiple layers of bragg reflectors to further form a solid-state fabricated resonator (SMR); alternatively, the substrate may further include a cavity to further constitute a film bulk acoustic resonator Filter (FBAR).
In this embodiment, a film bulk acoustic resonator filter is formed as an example. Based on this, a cavity 110a is formed in each resonant region of the substrate 100, and a sacrificial layer 110 is further filled in the cavity 110a, and the sacrificial layer 110 is removed after the resonant structure is completed in the subsequent preparation, so as to release the cavity.
In step S200, referring to fig. 5 in particular, a lower electrode layer 210 and a metal ring 240 are formed in each resonance region of the substrate 100, and the metal ring 240 surrounds the edge of the resonance region and is located within the area of the lower electrode layer 210.
Wherein, the lower electrode layer 210 and the metal ring 240 may include the same metal material, for example, each including one or a combination of molybdenum, gold, tungsten, platinum, ruthenium, titanium tungsten, aluminum, and titanium. It can be understood that, by forming the metal ring 240 at the edge of the resonance region, after the lower electrode layer 210 on which the metal ring 240 is superimposed is formed, the thickness of the film layer at the edge of the resonance region is increased, which is beneficial to adjusting the frequency of the edge position of the resonance structure to be different from the frequency of the main body portion of the resonance structure, thereby reducing the energy loss at the edge position of the resonance structure and improving the quality factor (Q value) of the device.
Specifically, the lower electrode layer 210 may be preferentially formed, and the metal ring 240 may be formed on the lower electrode layer 210. Alternatively, it is preferable that the metal ring 240 is formed at the edge of the resonance region, and then the lower electrode layer 210 is formed, so that the lower electrode layer 210 covers the metal ring 240. In the above preferred embodiment, the metal ring 240 and the lower electrode layer 210 may be formed by an etching process, and at this time, since the metal ring 240 is covered under the lower electrode layer 210, etching damage to the metal ring 240 can be still avoided when the lower electrode layer 210 is formed by the etching process.
In step S300, referring to fig. 6, a piezoelectric layer 220 is formed on the substrate 100, and the piezoelectric layer 220 covers the lower electrode layer 210 and the metal ring 240. Wherein the material of the piezoelectric layer 220 includes at least one of zinc oxide (ZnO), aluminum nitride (AlN), and lead zirconate titanate (PZT), for example.
In step S400, as shown with particular reference to fig. 7 and 8, an upper electrode layer 230 and a mass loading layer 250 are formed on the piezoelectric layer 220. Wherein the upper electrode layer 220 is formed in each resonance region, and the mass loading layer 250 is formed in at least one resonance region.
In a specific embodiment, the substrate 100 has a plurality of resonance regions, a part of the resonance regions is formed with the mass loading layer 250, and another part of the resonance regions is not formed with the mass loading layer 250. For example, referring to fig. 7, the mass loading layer 250 is formed in the first resonance region 100A, and the mass loading layer 250 is not formed in the second resonance region 100B.
Further, the upper electrode layer 230 and the mass loading layer 250 may both include the same metal material. Further, the upper electrode layer 230, the mass loading layer 250 and the metal ring 240 all comprise the same metal material, for example, the upper electrode layer 230, the mass loading layer 250 and the metal ring 240 may all comprise one or a combination of molybdenum, gold, tungsten, platinum, ruthenium, titanium tungsten, aluminum and titanium.
With continued reference to fig. 8, the end of the upper electrode layer 230 is covered directly above the metal ring 240, i.e., the metal ring 240 is located directly below the end of the upper electrode layer 230. More specifically, in the case where the lower electrode layer 210 covers the metal ring 240, a portion of the lower electrode layer 210 corresponding to the metal ring 240 is formed as a protrusion having a size larger than that of the metal ring 240, and an end portion of the upper electrode layer 230 is covered directly above the protrusion, that is, the protrusion is located directly below an end portion of the upper electrode layer 230.
It should be noted that, in this embodiment, by adjusting the metal ring 240 to be below the piezoelectric layer 220, the limitation of the existence of the metal ring 240 to the mass loading layer 250 is avoided, so that the preparation process of the mass loading layer 250 is not limited, and the sequence of the mass loading layer 250 and the upper electrode layer 230 is not limited, and both of them can be flexibly adjusted according to the requirements.
Specifically, as for the preparation process of the mass loading layer 250, it may be formed by a lift-off process, or may be directly formed by an etching process.
The method for forming the mass loading layer 250 by using the lift-off process may include: firstly, forming a spacing layer (for example, a metal thin film layer) on the piezoelectric layer 220, and forming a patterned photoresist layer on the spacing layer, wherein the patterned photoresist layer exposes a resonance region where a mass loading layer needs to be formed and covers the resonance region where the mass loading layer does not need to be formed; then, a sputtering process may be used to form a metal material layer, which is formed on the resonance region exposed from the patterned photoresist layer and also formed on the top surface of the patterned photoresist layer; then, the patterned photoresist layer is stripped by a stripping solution to remove the metal material on the top surface of the patterned photoresist layer, and the remaining metal material is used to form the mass loading layer 250, wherein the stripping solution is prevented from corroding the piezoelectric layer 220 due to the spacing layer between the patterned photoresist layer and the piezoelectric layer 220. Taking fig. 7 as an example, the patterned photoresist layer (not shown) exposes the first resonance region 100A and covers the second resonance region 100B, and after the patterned photoresist layer is stripped, the mass loading layer 250 is formed in the first resonance region 100A, and the mass loading layer is not formed in the second resonance region 100B.
In general, when the mass loading layer 250 is made to have a small thickness (for example, the thickness of the mass loading layer 250 is 1000 angstroms or less), the mass loading layer 250 may be formed by the lift-off process as described above. For a mass loading layer 250 with a large thickness (e.g., the mass loading layer 250 has a thickness greater than 1000 angstroms), if a lift-off process is still used, there is a risk that: the metal material layer formed by performing the sputtering process under the mask of the patterned photoresist layer, the portion to be removed of the patterned photoresist layer covered by the metal material layer is easily connected with the portion to be reserved formed in the exposed region, so that the subsequent photoresist layer is difficult to strip, and the problem that the edge of the formed mass loading layer has burrs is easily caused.
In this regard, the mass loading layer 250 having a relatively large thickness may be formed using an etching process. Specifically, the method for forming the mass loading layer 250 by using the etching process includes: firstly, forming a metal material layer for constituting a mass loading layer; then, forming a patterned mask layer on the metal material layer, wherein the patterned mask layer covers a resonance area where a mass loading layer is required to be formed and exposes the resonance area where the mass loading layer is not required to be formed; thereafter, an etching process is performed to remove the exposed metal material layer, and the mass loading layer 250 is formed using the remaining metal material layer. It should be appreciated that, during the etching process, since the metal ring 240 is not exposed on the surface of the piezoelectric layer 220, when the resonance region where the mass loading layer is not required to be formed is etched, the metal ring 240 in the resonance region is not damaged. Taking fig. 7 as an example, the patterned mask layer (not shown in the figure) exposes the second resonance region 100B and covers the first resonance region 100A, and the exposed second resonance region 100B is etched in an etching process to remove the metal material layer in the second resonance region 100B, and at this time, the metal ring 240 in the second resonance region 100B is effectively protected below the piezoelectric layer 220.
It should be noted that, when the etching process is directly used to form the mass loading layer 250, the thickness of the mass loading layer 250 to be formed is not limited. That is, the mass loading layer 250 may be formed using an etching process regardless of whether the thickness of the mass loading layer 250 is 1000 angstroms or less, or greater than 1000 angstroms.
Therefore, in this embodiment, the preparation process of the mass loading layer 250 is not limited by the metal ring 240, so that the preparation process can be adjusted more flexibly, including: the metal ring can be directly prepared by adopting an etching process, so that the metal ring 240 is not damaged, the metal ring is generally used for preparing the mass load layers 250 with different thicknesses, and the problem that the process is not easy to control when the mass load layers 250 with larger thicknesses are prepared by adopting a stripping process is effectively avoided.
In addition, since the metal ring 240 is not exposed on the surface of the piezoelectric layer 220, the sequence of the mass loading layer 250 and the upper electrode layer 230 can be adjusted more flexibly.
In one embodiment, the method of preparing the mass loading layer 250 first and then preparing the upper electrode layer 230 on the mass loading layer 250 includes the following steps.
In a first step, a mass loading layer 250 is formed in the at least one resonance region using an etching process or a lift-off process. As shown in fig. 7, for example, a mass loading layer 250 is formed in the first resonance region 100A. As described above, the corresponding preparation process may be selected according to the thickness of the mass loading layer 250 to be prepared, that is: when the thickness of the mass loading layer is less than or equal to 1000 angstroms, forming the mass loading layer 250 by utilizing an etching process or a stripping process; and, when the thickness of the mass loading layer is greater than 1000 angstroms, forming the mass loading layer 250 by using an etching process.
In the second step, the upper electrode layer 230 is formed in each resonance region, and in the resonance region where the mass loading layer is formed, the upper electrode layer 230 covers the mass loading layer 250. For example, as shown in fig. 8, the upper electrode layer 230 is formed in each of the first resonance area 100A and the second resonance area 100B, and the upper electrode layer 230 covers the mass loading layer 250 in the first resonance area 100A.
The upper electrode layer 230 may also be formed by an etching process, which specifically includes: first, an electrode material layer is formed, and then the electrode material layer is etched to complete a patterning process, thereby forming the upper electrode layer 230 in each resonance region. It should be noted that, since the upper electrode layer 230 is formed in each resonance region, and the upper electrode layer 230 also covers the mass loading layer 250 for the resonance region with the mass loading layer, when the etching process of the upper electrode layer 230 is performed, the mass loading layer 250 below the upper electrode layer is not damaged.
In another embodiment, the upper electrode layer 230 is prepared under the mass loading layer 250, and the method includes the following steps.
Step one, a layer of upper electrode material is formed on the piezoelectric layer 220.
And step two, forming a mass loading layer 250 in the at least one resonance region by using a stripping process, wherein the mass loading layer 250 is formed on the upper electrode material layer. In this embodiment, the upper electrode material layer may be used to space the patterned photoresist layer and the piezoelectric layer 220 during the lift-off process, thereby preventing erosion of the piezoelectric layer 220 during lift-off of the patterned photoresist layer.
And step three, performing an etching process on the upper electrode material layer to form upper electrode layers 230 in the respective resonance regions. The method specifically comprises the following steps: forming a patterned mask layer which covers at least electrode regions of the respective resonance regions and exposes at least regions between adjacent resonance regions; thereafter, the upper electrode material layer is etched under the mask of the patterned mask layer to form the upper electrode layer 230.
In another approach as described above, the mass loading layer 250 is formed using a lift-off process rather than an etching process because: damage to the upper electrode material layer in the resonance region where the mass loading layer 250 is not required to be formed in the etching process is avoided.
As can be seen from the above, in the present embodiment, the preparation method of the mass loading layer 250 can be adjusted according to the thickness thereof. Namely: when the thickness of the mass loading layer 250 is less than or equal to 1000 angstroms, forming the mass loading layer 250 under the upper electrode layer 230 by using an etching process or a lift-off process; alternatively, the mass loading layer 250 is formed over the upper electrode layer 230 using a lift-off process. And, when the thickness of the mass loading layer is greater than 1000 angstroms, the mass loading layer 250 is formed under the upper electrode layer 230 directly by using an etching process prior to the upper electrode layer 230.
In addition, after the mass loading layer 250 and the upper electrode layer 230 are prepared, the method further includes: the sacrificial layer in the cavity 110a is removed to release the space of the cavity 110 a.
< example two >
The first embodiment is directed to a case where mass loading layers having different thicknesses are provided for different resonant structures of a semiconductor device in this embodiment.
Referring specifically to fig. 9, a mass loading layer is formed in each of the resonance structure of the first resonance region 100A and the resonance structure of the second resonance region 100B of the semiconductor device. Wherein the thickness of the mass loading layer 250A in the first resonance region 100A is different from the thickness of the mass loading layer 250B in the second resonance region 100B, such that the resonance frequency of the resonant structure in the first resonance region 100A is different from the resonance frequency of the resonant structure in the second resonance region 100B. In this embodiment, the thickness of the mass loading layer 250A in the first resonance region 100A is greater than the thickness of the mass loading layer 250B in the second resonance region 100B.
Further, when mass loading layers with different thicknesses are prepared, in order to avoid the mutual influence of the mass loading layers with different thicknesses, for the mass loading layer 250A with a larger thickness in the first resonance region 100A, the mass loading layer 250A may be prepared below the upper electrode layer 230 by using an etching process or a lift-off process; for the mass loading layer 250B with a small thickness in the second resonance region 100B, in order to avoid affecting the mass loading layer 250A in the first resonance region 100A, a lift-off process may be adopted to form the mass loading layer 250B below the upper electrode layer 230; alternatively, the mass loading layer 250b is formed over the upper electrode layer 230 using a lift-off process.
Referring specifically to fig. 9, an exemplary embodiment of the present invention includes the following steps.
First, a mass loading layer 250A having a large thickness is formed in the first resonance region 100A by an etching process or a lift-off process. Similarly, when the thickness of the mass loading layer 250A in the first resonance region 100A is greater than 1000 angstroms, the mass loading layer 250A may be formed using an etching process.
In a second step, a layer of upper electrode material is formed, covering the mass loading layer 250a and the exposed piezoelectric layer 220.
A third step of forming a mass loading layer 250B in the second resonance region 100B by a lift-off process, and forming the mass loading layer 250B on the upper electrode material layer in the second resonance region 100B in a covering manner. Wherein the thickness of the mass loading layer 250B in the second resonance region 100B may be 1000 angstroms or less.
In the fourth step, an etching process is performed on the upper electrode material layer to form upper electrode layers 230 in the respective resonance regions. The method specifically comprises the following steps: forming a patterned mask layer which covers at least electrode regions of the respective resonance regions and exposes at least regions between adjacent resonance regions; thereafter, the upper electrode material layer is etched under the mask of the patterned mask layer to form the upper electrode layer 230.
In this embodiment, the mass loading layers with different thicknesses are respectively prepared in different steps (i.e., the thicker mass loading layer 250a is prepared before the upper electrode material layer, and the thinner mass loading layer 250b is prepared after the upper electrode material layer), so that the mutual influence of the mass loading layers with different thicknesses is avoided.
Based on the above-mentioned forming method, the structure of the prepared semiconductor device is described below, and specifically, referring to fig. 8 and 9, the semiconductor device includes: a substrate 100 and a resonant structure formed on the substrate 100.
Specifically, the substrate 100 has at least one resonant region thereon. A first resonance region 100A and a second resonance region 100B are illustrated in this embodiment.
And, the resonance structure formed in each resonance region includes the lower electrode layer 210, the metal ring 240, the piezoelectric layer 220, and the upper electrode layer 230. Wherein the metal ring 240 surrounds the edge of each resonance region and is located within the area of the lower electrode layer 210, and is further covered by the piezoelectric layer 220. In this embodiment, the metal ring 240 is further covered by the lower electrode layer 210, that is, the lower electrode layer 210 covers the metal ring 240.
As described with continued reference to fig. 8 and 9, in a plurality of resonance regions of the semiconductor device, it is possible to have a mass loading layer provided in a part of the resonance regions, and the thicknesses of the mass loading layers located in the different resonance regions may also be different from each other, and it is also possible to have another part of the resonance regions not provided with a mass loading layer. In this way, the plurality of resonant structures in the semiconductor device have different resonant frequencies.
Referring to fig. 8 and 9, when the mass loading layer has a large thickness (for example, greater than 1000 angstroms), the mass loading layer 250 may be disposed below the upper electrode layer 230, so as to facilitate the direct fabrication of the mass loading layer by using an etching process. And, when the mass loading layer thickness is small (e.g., 1000 angstroms or less), the mass loading layer 250 may be disposed under the upper electrode layer 230; alternatively, the mass loading layer 250 is disposed above the upper electrode layer 230.
Further, referring to fig. 9, for mass-loading layers having different thicknesses, it is possible to provide a mass-loading layer having a larger thickness below the upper electrode layer and a mass-loading layer having a smaller thickness above the upper electrode layer, respectively. Therefore, the mass loading layers with different thicknesses can be prepared in different process steps respectively, and mutual influence is avoided. That is, in fig. 9, the mass loading layer 250A having a larger thickness in the first resonance region 100A is disposed below the upper electrode layer 230, and the mass loading layer 250B having a smaller thickness in the second resonance region 100B is disposed above the upper electrode layer 230.
In summary, in the method for forming a semiconductor device provided by the present invention, the metal ring is preferentially prepared, and the piezoelectric layer covers the metal ring, so that the metal ring is not exposed from the surface of the piezoelectric layer, and thus, when the mass loading layer is prepared on the piezoelectric layer, the metal ring is not damaged (specifically, the metal ring in the resonance region where the mass loading layer is not formed is not damaged). In addition, as the metal ring is not exposed, the process limitation of the mass load layer can be effectively improved, so that the mass load layer can be formed by adopting a stripping process and an etching process, and the problem that the process of the mass load layer with larger thickness is difficult to be compatible is effectively solved. In addition, the flexible adjustment of the preparation sequence of the mass loading layer and the upper electrode layer is facilitated by adjusting the position of the metal ring, and the manufacturing efficiency of the device is improved.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. Also, while the present invention has been described with reference to the preferred embodiments, the embodiments are not intended to be limiting. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (17)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein at least one resonance area is arranged on the substrate;
forming a lower electrode layer and a metal ring in each resonance area of the substrate, wherein the metal ring surrounds the edge of the resonance area and is positioned in the area range of the lower electrode layer;
forming a piezoelectric layer on the substrate, the piezoelectric layer covering the lower electrode layer and the metal ring; and the number of the first and second groups,
an upper electrode layer and a mass loading layer are formed on the piezoelectric layer, wherein the upper electrode layer is formed in each resonance region, and the mass loading layer is formed in at least one resonance region.
2. The method for forming a semiconductor device according to claim 1, wherein the method for forming the lower electrode layer and the metal ring comprises: preferentially forming a metal ring at the edge of the resonance area; and then, forming a lower electrode layer, and enabling the lower electrode layer to cover the metal ring.
3. The method for forming a semiconductor device according to claim 1, wherein the method for forming the upper electrode layer and the mass loading layer comprises:
forming a mass loading layer in the at least one resonance region using an etching process or a lift-off process; and the number of the first and second groups,
an upper electrode layer is formed in each resonance region, the upper electrode layer covering the mass loading layer.
4. The method for forming a semiconductor device according to claim 3, wherein the mass loading layer is formed by an etching process or a lift-off process if the thickness of the mass loading layer is 1000 angstroms or less; or, if the thickness of the mass loading layer is more than 1000 angstroms, the mass loading layer is formed by utilizing an etching process.
5. The method for forming a semiconductor device according to claim 1, wherein the method for forming the upper electrode layer and the mass loading layer comprises:
forming a layer of upper electrode material on the piezoelectric layer;
forming a mass loading layer in the at least one resonance region using a lift-off process, the mass loading layer being formed on the upper electrode material layer; and the number of the first and second groups,
and performing an etching process on the upper electrode material layer to form the upper electrode layer in each resonance area.
6. The method of forming a semiconductor device of claim 5, wherein the mass loading layer has a thickness of less than 1000 angstroms.
7. The method for forming a semiconductor device according to claim 1, wherein when the thickness of the mass loading layer is 1000 angstroms or less, the mass loading layer is formed below the upper electrode layer by an etching process or a lift-off process, or the mass loading layer is formed above the upper electrode layer by a lift-off process; and the number of the first and second groups,
and when the thickness of the mass loading layer is more than 1000 angstroms, forming the mass loading layer below the upper electrode layer by utilizing an etching process.
8. The method for forming a semiconductor device according to claim 1, wherein the substrate has a first resonance region and a second resonance region, the mass loading layer is formed in each of the first resonance region and the second resonance region, and a thickness of the mass loading layer in the first resonance region is larger than a thickness of the mass loading layer in the second resonance region.
9. The method for forming a semiconductor device according to claim 8, wherein the method for forming the upper electrode layer and the mass loading layer comprises:
forming a mass loading layer in the first resonance region by using an etching process;
forming a layer of upper electrode material overlying the mass loading layer and the exposed piezoelectric layer in the first resonance region;
forming a mass loading layer in the second resonance region using a lift-off process, and a mass loading layer in the second resonance region is formed on the upper electrode material layer; and the number of the first and second groups,
and performing an etching process on the upper electrode material layer to form upper electrode layers in the respective resonance regions.
10. The method for forming a semiconductor device according to claim 1, wherein an end portion of the upper electrode layer is covered directly over the metal ring.
11. The method of forming a semiconductor device according to claim 1, wherein the upper electrode layer, the mass loading layer, and the metal ring each include the same metal material.
12. A semiconductor device, comprising:
a substrate having at least one resonant region thereon;
a lower electrode layer disposed at least in each of the resonance regions;
the metal ring surrounds the edge of each resonance area and is positioned in the area range of the lower electrode layer;
a piezoelectric layer covering the lower electrode layer and the metal ring;
an upper electrode layer disposed in each of the resonance regions; and the number of the first and second groups,
a mass loading layer disposed in at least one resonance region, and the upper electrode layer and the mass loading layer are stacked on the piezoelectric layer in the at least one resonance region.
13. The semiconductor device according to claim 12, wherein the lower electrode layer covers the metal ring.
14. The semiconductor device of claim 12, wherein the mass loading layer is greater than 1000 angstroms thick and is disposed below the upper electrode layer; alternatively, the mass loading layer has a thickness of 1000 angstroms or less and is disposed below or above the upper electrode layer.
15. The semiconductor device according to claim 12, wherein the substrate has a first resonance region and a second resonance region, the mass loading layer is formed in each of the first resonance region and the second resonance region, and a thickness of the mass loading layer in the first resonance region is larger than a thickness of the mass loading layer in the second resonance region.
16. The semiconductor device according to claim 15, wherein the mass loading layer in the first resonance region is provided below the upper electrode layer, and wherein the mass loading layer in the second resonance region is provided above the upper electrode layer.
17. The semiconductor device according to claim 12, wherein the upper electrode layer, the mass loading layer, and the metal ring each include the same metal material.
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| CN103701425A (en) * | 2013-10-25 | 2014-04-02 | 诺思（天津）微系统有限公司 | Wave filter and manufacture method thereof |
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| CN111211757A (en) * | 2020-02-05 | 2020-05-29 | 杭州见闻录科技有限公司 | Top electrode structure of bulk acoustic wave resonator and manufacturing process |
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| CN102075161A (en) * | 2011-01-20 | 2011-05-25 | 张�浩 | Acoustic wave device and manufacturing method thereof |
| CN103701425A (en) * | 2013-10-25 | 2014-04-02 | 诺思（天津）微系统有限公司 | Wave filter and manufacture method thereof |
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