CN112803476A

CN112803476A - Method and system for controlling voltage of variable direct current bus of modular multi-level energy storage converter

Info

Publication number: CN112803476A
Application number: CN202011641452.XA
Authority: CN
Inventors: 高峰; 马展; 张承慧; 李伟; 牛得存; 秦福田
Original assignee: Shandong University
Current assignee: Shandong University
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-05-14
Anticipated expiration: 2040-12-31
Also published as: CN112803476B

Abstract

The utility model provides a DC bus voltage control method and system of modularization multi-level energy storage converter, including: the gate control signal redistribution and the active bypass are carried out according to the change condition of the absolute value of the phase voltage reference wave of the modular multilevel energy storage converter, so that the direct-current bus voltage of the modular multilevel energy storage converter changes along with the change of the absolute value of the phase voltage reference wave; after gate signal redistribution and active bypass, a switching sequence which only generates extra charge throughput is distributed to each sub-module in turn to avoid increasing SOH difference between battery groups; and in each working interval, carrying out SOC (system on chip) equalization on other submodules except the submodule participating in the active bypass, namely rearranging the switch sequences distributed to each submodule according to the average current value generated by each switch sequence.

Description

Method and system for controlling voltage of variable direct current bus of modular multi-level energy storage converter

Technical Field

The disclosure belongs to the technical field of optimization control of a battery energy storage system, and particularly relates to a method and a system for controlling a variable direct current bus voltage of a modular multilevel energy storage converter.

Background

The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.

A large number of battery packs can be directly connected into a medium-high voltage grade power grid by using multilevel converters such as a cascaded H-bridge (CHB) or a Modular Multilevel Converter (MMC), and a power frequency transformer is not needed, so that the engineering floor area is reduced, the efficiency is improved, and the cost is reduced.

Generally, the battery pack may be connected to a following full-bridge or half-bridge circuit directly or through a small capacitor (with a capacitance of several microfarads) to form a Submodule (SM) in a CHB or MMC battery energy storage system (best energy storage system, hereinafter referred to as BESS). This structure can effectively reduce the cost and volume. Meanwhile, a DC-DC converter or a large capacitor with the capacitance value of tens of millifarads can be added between the battery pack and the full-bridge or half-bridge circuit. In addition to cost, size and efficiency, the considerations for selecting different submodule structures are whether the current ripple on the dc side will cause the state-of-health (SOH) of the battery pack to deteriorate in actual operation.

Studies have shown that the current ripple on the dc side with a pass of the multi-level converter type generally does not cause degradation of the SOH of the battery unless this current ripple causes a large temperature rise or contains charge-discharge micro-cycles that can lead to a large amount of extra charge throughput. It is often not too difficult for the BESS to configure a powerful battery thermal management system, so the impact of the extra charge throughput on its lifetime should be of greater concern.

Charge throughput refers to the total amount of charge that can be charged and discharged over the life of the battery (which can be evaluated in units of coulombs or ampere-hours). It depends on the electrochemical characteristics and operating conditions of the cell; it is usually a fixed value for a particular type of battery when other aging effects are ignored. In short, the life of a battery depends on the total charge throughput that its chemically active species can withstand. In general, for an ideal dc current charge/discharge condition, the total charge throughput can be characterized by the charge/discharge average current.

By comparing different sub-module configurations, SM using DC-DC converters can completely eliminate unnecessary ac ripple, but at the expense of increased cost, reduced efficiency, and increased size. Cost and volume considerations are more important in applications where single-phase CHB-or MMC-BESS, which is conveniently and flexibly configured as a primary feature, is more suitable for connecting a battery pack to a semiconductor switching circuit, either directly or through a small capacitor with a capacitance of a few microfarads. Therefore, in consideration of the extra charge throughput which may be caused by the current ripple due to the absence of the DC-DC converter, a new control method needs to be specially designed to solve the problem, so that the problem is solved completely by a software method, the cost is reduced, the efficiency is improved, and the volume is reduced.

Disclosure of Invention

In order to overcome the defects of the prior art, the present disclosure provides a method for controlling a dc-to-dc bus voltage of a modular multilevel energy storage converter, and compared with a conventional carrier phase shift PWM modulation or carrier stacking (PD) PWM, the extra charge throughput is significantly reduced.

In order to achieve the above object, one or more embodiments of the present disclosure provide the following technical solutions:

in a first aspect, a method for controlling a variable direct current bus voltage of a modular multilevel energy storage converter is disclosed, which comprises the following steps:

determining the change condition of the direct-current bus voltage by using the absolute value of the phase voltage reference wave of the modular multilevel energy storage converter;

gate control signal redistribution and active bypass are carried out, so that the direct-current bus voltage of the modular multi-level energy storage converter changes along with the change of the absolute value of a phase voltage reference wave;

after gate signal redistribution and active bypass, a switching sequence which only generates extra charge throughput is distributed to each sub-module in turn to avoid increasing SOH difference between battery groups;

and in each working interval, carrying out SOC (system on chip) equalization on other submodules except the submodule participating in the active bypass, and rearranging the switch sequences according to the average current value generated by each switch sequence.

Specifically, gate control signal (hereinafter referred to as gate control signal) redistribution and active bypass are carried out based on the absolute value of the phase voltage reference wave, so that the direct-current bus voltage of the modular multilevel energy storage converter changes along with the change of the absolute value of the phase voltage reference wave;

in each working interval, the state-of-charge (SOC) equalization is performed on other sub-modules except the sub-module which generates the extra charge throughput, and the switching sequences are rearranged according to the average current value generated by each switching sequence.

According to the further technical scheme, a phase voltage reference wave is generated based on the measured alternating current output of the single-phase modularized multi-level converter type battery energy storage system, and then the phase voltage reference wave is compared with a carrier wave in a modulator to obtain an initial switching sequence of switches on a half-bridge switching circuit.

According to the further technical scheme, gate control signal redistribution and active bypass are carried out according to the change situation of the absolute value of the phase voltage reference wave.

According to the further technical scheme, when the switching sequences are rearranged:

firstly, reading the average current and SOC of a battery pack in each submodule from a battery management system;

then, rearranging the switching sequence, wherein N working intervals are shared in the process;

in the N working intervals, only the switching sequences which can cause extra charge throughput are distributed to the N sub-modules in turn;

the average current is properly distributed by rearranging the remaining (N-1) switching sequences.

The second aspect discloses a single-phase battery energy storage system based on a modular multilevel converter, wherein A, B two phases form an equivalent H bridge for realizing single-phase output, each phase respectively consists of an upper bridge arm, a lower bridge arm and an output filter inductor, each bridge arm consists of N sub-modules and a bridge arm filter inductor, and a battery pack is directly connected with a half-bridge circuit or is connected with a small capacitor in parallel;

the control of the sub-modules is carried out by adopting the method for controlling the voltage of the direct-current bus of the modular multilevel energy storage converter.

In a third aspect, a dc bus voltage control system for a modular multilevel energy storage converter is disclosed, comprising:

the modular multilevel converter controller is used for generating a phase voltage modulation reference wave, and the PD-PWM modulator is used for generating an initial switching sequence of each sub-module;

the gate control signal redistribution and active bypass unit is used for redistributing gate control signals on the basis of the determined number of the sub-modules participating in active bypass so that the direct-current bus voltage of the modular multilevel energy storage converter changes along with the change of the absolute value of the phase voltage reference wave;

a switching sequence rearrangement unit for allocating a switching sequence, which is unique to generate an extra charge throughput, to each sub-module in turn after the gate control signal is reallocated to avoid increasing the SOH difference between the battery groups;

and in each working interval, carrying out SOC (system on chip) equalization on other submodules except the submodule which only generates extra charge throughput, and rearranging the switching sequences according to the average current value generated by each switching sequence.

The above one or more technical solutions have the following beneficial effects:

1. the traditional energy storage battery grid-connected system based on the modular multilevel converter ignores battery SOH (state of health) degradation caused by extra charge throughput due to current fluctuation on a direct current side.

2. The method for rearranging the switching sequences based on the improved PD-PWM method can balance the SOC of the battery pack among the submodules at the same time.

Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to limit the disclosure.

FIG. 1 is a logic diagram of the overall control of the method for controlling the voltage of a variable DC bus of a single-phase battery energy storage system based on a modular multilevel converter according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a single-phase battery energy storage system topology based on a modular multilevel converter according to an embodiment of the invention;

FIG. 3(a) shows the common DC bus voltage (u) under normal conditions in an embodiment of the present invention_dc) And upper and lower arm voltages (u) of phase A_au,u_ad) A schematic diagram of the relationship of (1);

FIG. 3(b) shows the control condition u of the DC-to-DC bus voltage according to the embodiment of the present invention_dcAnd u_au,u_adA schematic diagram of the relationship of (1);

FIG. 3(c) shows one-half (u) of the common DC bus voltage under normal conditions in an embodiment of the present invention_dc/2) and A-phase voltage (u)_{leg_A}) And its absolute value (| u)_{leg_A}|) a relationship diagram;

FIG. 3(d) shows the control condition u of the DC-to-DC bus voltage according to the embodiment of the present invention_dc/2、u_{leg_A}And | u_{leg_A}A schematic diagram of the relationship between | s;

FIG. 3(e) shows the common DC bus voltage (u) under normal conditions in an embodiment of the present invention_dc) And trapezoidal wave (u) of output voltage_{AB_ladder}) And its absolute value (| u)_{AB_ladder}|) a relationship diagram;

FIG. 3(f) shows u under the condition of the control of the DC-converted bus voltage according to the embodiment of the present invention_dc、u_{AB_ladder}And | u_{AB_ladder}A schematic diagram of the relationship between | s;

FIG. 4 is a schematic diagram of the operation of the variable DC bus voltage control;

FIG. 5 is a schematic diagram of the gate signal redistribution and active bypass flow in an embodiment of the present invention;

FIG. 6 is a schematic diagram of a switch sequence rearrangement process according to an embodiment of the present invention;

FIG. 7(a) is a schematic diagram of SOC balancing during discharging during rearrangement of the switching sequences in the embodiment of the present invention;

fig. 7(b) is a schematic diagram of SOC equalization during charging in the rearrangement process of the switch sequence in the embodiment of the present invention.

Detailed Description

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

The embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.

Example one

The embodiment discloses a method for controlling a variable direct current bus voltage of a modular multilevel energy storage converter, which comprises the following steps:

first, a corresponding phase voltage reference wave is generated based on the measured ac output of the single phase MMC-BESS, and then the phase voltage reference waves are compared in the modulator to obtain an initial switching sequence of the switches on the half-bridge switching circuit.

And secondly, performing initial switch gate control signal redistribution and active bypass based on the absolute value of the phase voltage reference wave, and further realizing the voltage control of the variable-direct-current bus.

Finally, the switching sequence is rearranged to achieve SOC equalization.

The invention provides a method for controlling the voltage of a variable direct current bus of a modular multi-level energy storage converter based on an improved PD-PWM modulation method, so that the number of submodules put into each phase at each moment is not always kept to be a constant number any more, but is changed along with the fluctuation of the absolute value of a phase voltage reference wave. This approach can remove the ac current ripple in most sub-modules in each leg and concentrate the PWM switching action that produces extra throughput into 1 sub-module. After applying this method, the extra charge throughput is significantly reduced compared to conventional carrier phase shift PWM modulation or PD-PWM. Even when compared to ideal dc charging/discharging, the proposed method only results in very low additional charge throughput.

In a specific implementation example, a method for controlling a variable direct current bus voltage of a modular multilevel energy storage converter is disclosed, and the method comprises the steps of firstly generating corresponding phase voltage reference waves based on measured alternating current output of MMC-BESS, then performing gate control signal redistribution and active bypass based on absolute values of the phase voltage reference waves, wherein the gate control signals and the active bypass are in a sequentially executed relationship, specifically shown in figure 5, and then rearranging a switching sequence to realize SOC balance.

The method not only can obviously reduce the extra charge throughput caused by the current fluctuation of the direct current side and prolong the whole service life of the energy storage system, but also can balance the SOC of the battery pack among the submodules by the provided method for rearranging the switch sequence.

The overall control logic of the DC bus voltage control method of the modular multilevel energy storage converter is shown in the attached figure 1. The method specifically comprises the following steps:

step (1): generating a corresponding phase voltage reference wave based on the measured AC output of the MMC-BESS;

step (2): gate control signal redistribution and active bypass are carried out based on the absolute value of the phase voltage reference wave, and then the voltage control of the variable direct current bus is realized;

and (3): the switching sequence is rearranged to achieve SOC equalization.

FIG. 2 is a schematic diagram of a topological structure of a single-phase battery energy storage system based on MMC, wherein A, B phases form an equivalent H bridge to realize single-phase output, and each phase comprises an upper bridge arm, a lower bridge arm and an output filter inductor (L)_out) Each bridge arm is composed of N sub-modules and a bridge arm filter inductor (L)_arm) And (4) forming. The battery pack is connected with the half-bridge circuit directly or through a small capacitor connected in parallel.

When the voltage drop on the bridge arm inductance is ignored, the direct current bus voltage of the single-phase MMC-BESS is shown as the formula (1),

u_dc＝u_au+u_ad＝u_bu+u_bd (1)

in the formula u_au,u_ad,u_buAnd u_bdThe bridge arm voltages of the upper bridge arm and the lower bridge arm of the A phase and the B phase are respectively. And phase voltage (u) of single-phase MMC-BESS_{leg_A}And u_{leg_B}) Are defined as shown in formulas (2) and (3).

Then, a step wave u of the output voltage_{AB_ladder}Can be calculated by formula (4) and can be filtered by the bridge arm inductance and the output inductanceTo obtain an output voltage u_AB。

u_{AB_ladder}＝u_{leg_A}-u_{leg_B} (4)

It can be seen from the above formula that if the voltages of the upper and lower bridge arms are reduced by the same voltage value, the dc bus voltage is reduced, and the phase voltage and the output voltage can still be kept unchanged.

When using conventional modulation and control, if the number of submodules of each bridge arm of the MMC-BESS is N, N submodules are always put into operation at the same time for each phase. Therefore, the common dc bus voltage is generally the battery pack voltage u of the N sub-modules that are turned on_{bat_i}To sum, i.e.

After the terminal voltage of the battery pack is equalized according to the general requirements, the voltage of the common direct current bus is N x u_bat. For example, assuming that there are 12 sub-modules in each bridge arm, and the terminal voltage of the battery pack in each sub-module is 60V, the common dc bus voltage u_dcIt is 720V. When the modulation depth is higher, the peak values of the bridge arm voltage and the output voltage are u_dcAs shown in fig. 3(a) and (e), and the peak value of the phase voltage is equal to u_dcThe result of the calculation is shown in FIG. 3 (c).

In fact, the common DC bus voltage u can be dynamically adjusted by actively bypassing the switching signals of the same number of working sub-modules in each leg of the MMC-BESS_dcAs shown in FIGS. 3(b), (d) and (f). As long as u shown in FIG. 3(b) can be secured_dcIf the voltage is larger than the bridge arm voltage, overmodulation cannot occur; and both the phase voltage and the output voltage can therefore be kept constant. Also, bypassing the same number of submodules in each leg does not increase the circulating current.

As can be seen from FIG. 3(b), u_dcWill vary as well as the improved bridge arm voltage envelope; u. of_dcThe/2 will vary along with the envelope of the absolute value of the phase voltage, as shown in fig. 3 (d). As can be seen from fig. 3(b), the bridge arm voltage will change after using the proposed methodTherefore, the number of sub-modules for active bypass will be determined by u _dc2 and the absolute value of the phase voltage reference wave.

First, a corresponding phase voltage reference wave Ref is generated based on the measured ac output of the MMC-BESS, and the expression of the absolute value | Ref | thereof is:

|Ref|＝|msin(wt)| (5)

where m is the modulation depth.

Then, the steps of gate signal redistribution and active bypass are specifically as follows: fig. 4 shows the operation principle of the dc bus voltage control.

Generating an initial switching sequence (hereinafter abbreviated GS) of switches on the half-bridge switching circuit in the FPGA by comparing the reference wave Ref with the carrier generated based on the PD-PWM_o)；

Determining the variation of DC bus voltage by comparing | Ref | with the peak value of each carrier wave in the upper half plane, normalizing the DC bus voltage value u_{dc_norm}The calculation can be made by equation (6):

where ceil is an ceiling function. For example, if | Ref | is at [0,2/N ]]Interval u_{dc_norm}It is equal to 2/N. As shown in FIG. 4, the whole is [0,1 ]]The interval can be according to u_{dc_norm}Dividing the reaction solution into N/2 intervals;

to generate the required varying dc bus voltage, the required varying dc bus voltage can be generated by applying the voltage to the GS according to the process shown in fig. 5_oPerforming redistribution and active bypass to generate a new switching sequence (GS for short hereinafter)_n)。

Specifically, the specific contents of the gate signal reallocation and active bypass are as follows:

a flow chart of the gate signal redistribution and active bypass steps is shown in FIG. 5. first, an initial switching sequence GS is applied_oAre fully assigned to the new switching sequence GS_n。

Taking the kth interval as an example, when the phase voltage reference wave is greater than 0, GS (k) and GS (1) need to exchange their gate control signals first; then, GS_n(k +1) to GS_n(2k-1) the gating signals for this (k-1) switching sequence need to be set to 0. On the other hand, when the phase voltage reference wave is less than 0, GS (N- (k-1)) and GS (N) need to exchange gate control signals first; then, GS_n(N-1) to GS_n(N- (k-1) the (k-1) switching sequences the gating signals at this time all need to be set to 0.

In this way, the switching action of high frequencies is concentrated in the 1 st and nth sub-modules, and (k-1) the gate signal with the unnecessary conduction process is actively bypassed during operation. The final dc bus voltage can be as shown in fig. 3(b), (d), (f).

The specific steps for rearranging the switching sequence are as follows:

allocating a sequence of switches that are unique to produce extra charge throughput to each submodule in turn to avoid increasing SOH differences between battery packs, the time period of the rotation being several seconds;

and in each working interval, carrying out SOC balance on other sub-modules, and distributing the switching sequences according to the average current value generated by each switching sequence. The other sub-modules refer to those sub-modules other than the one uniquely assigned to the switching sequence that will produce the extra charge throughput.

Specifically, the specific contents of rearranging the switching sequence are as follows:

first, an average current (hereinafter, abbreviated as I) of a battery pack in each sub-module is read from a Battery Management System (BMS)_{bat_ave}) And an SOC.

The main principle for rearranging the switching sequence is then as shown in fig. 6, where there are N operating intervals in total. An operation interval is generally set to 1 second or several seconds because the SOC of the battery does not vary greatly in this time scale.

Next, to avoid increasing SOH difference between the battery packs, the N operation stages were operatedIn the interval, only the switching sequence GS which causes extra charge throughput_n(N) are alternately assigned to the N sub-modules.

The average current is then distributed appropriately by rearranging the remaining (N-1) switching sequences. Such a switching sequence rearrangement method works normally because the SOH changes much slower than the SOC. Thus, the remaining (N-1) sub-modules can be SOC equalized, and a specific schematic diagram is shown in FIG. 7. Specifically, the switch sequences are arranged in an ascending order according to the average current caused by the switch sequences in the discharging process, and are arranged in a descending order in the charging process; the sub-modules are arranged in an ascending order according to the SOC value of the battery pack in the charging and discharging process. Subsequently, during the discharging process, the switching sequence with the higher average current value is assigned to the submodule with the higher SOC value, as shown in fig. 7 (a); during charging, a switching sequence with a higher average current value may be assigned to a submodule with a lower SOC value, as shown in fig. 7 (b).

The traditional energy storage battery grid-connected system based on the modular multilevel converter ignores the health state deterioration caused by extra charge throughput due to the current fluctuation of a direct current side.

Example two

The present embodiment is directed to a computing device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor executes the computer program to implement the steps of the method in the above embodiment.

EXAMPLE III

An object of the present embodiment is to provide a computer-readable storage medium.

A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method of the preceding implementation example.

Example four

The purpose of the embodiment is to provide a single-phase battery energy storage system based on a modular multilevel converter, wherein A, B two phases form an equivalent H-bridge for realizing single-phase output, each phase respectively consists of an upper bridge arm, a lower bridge arm and an output filter inductor, each bridge arm consists of N sub-modules and a bridge arm filter inductor, and a battery pack is connected with a half-bridge circuit directly or through a small capacitor connected in parallel;

EXAMPLE five

The object of this embodiment is to provide a dc bus voltage control system of a modular multilevel energy storage converter, including:

a traditional controller of the modular multilevel converter is used for generating a phase voltage modulation reference wave, and a PD-PWM modulator is used for generating an initial switching sequence of each sub-module;

the gate control signal redistribution and active bypass unit is used for carrying out gate control signal redistribution and active bypass so that the direct-current bus voltage of the modular multi-level energy storage converter changes along with the change of the absolute value of the phase voltage reference wave;

and the switching sequence rearrangement unit is used for distributing the unique switching sequence which can generate extra charge throughput to each submodule in turn after the gating signals are redistributed so as to avoid increasing the SOH difference between the battery groups, carrying out SOC balance on other submodules except the submodule participating in the active bypass in each working interval, and rearranging the switching sequences according to the average current value generated by each switching sequence.

The steps involved in the apparatus of the above embodiment correspond to the first embodiment of the method, and the detailed description thereof can be found in the relevant description of the first embodiment. The term "computer-readable storage medium" should be taken to include a single medium or multiple media containing one or more sets of instructions; it should also be understood to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a processor and that cause the processor to perform any of the methods of the present disclosure.

Those skilled in the art will appreciate that the modules or steps of the present disclosure described above can be implemented using general purpose computer means, or alternatively, they can be implemented using program code executable by computing means, whereby the modules or steps may be stored in memory means for execution by the computing means, or separately fabricated into individual integrated circuit modules, or multiple modules or steps thereof may be fabricated into a single integrated circuit module. The present disclosure is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.

Claims

1. The method for controlling the voltage of the variable direct current bus of the modular multilevel energy storage converter is characterized by comprising the following steps:

2. The method of claim 1 wherein the initial switching sequence of the switches in the half-bridge switching circuit is generated by comparing a reference wave to a carrier generated based on PD-PWM.

3. The method as claimed in claim 1, wherein the method for controlling the voltage of the dc bus of the modular multilevel converter battery energy storage system comprises generating corresponding phase voltage reference waves based on the measured ac output of the single-phase modular multilevel converter battery energy storage system, and comparing the phase voltage reference waves in the modulator to obtain an initial switching sequence of the switches in the half-bridge switching circuit.

4. The method of claim 1 wherein, when rearranging the switching sequence:

in the N working intervals, only the switching sequences which cause extra charge throughput are distributed to the N sub-modules in turn;

5. The method as claimed in claim 1, wherein the gate control signal in the initial switching sequence of the switches in the half-bridge switching circuit is redistributed and actively bypassed according to the variation of the absolute value of the phase voltage reference wave.

6. The single-phase battery energy storage system based on the modular multilevel converter is characterized in that an equivalent H bridge is formed by A, B two phases and used for realizing single-phase output, each phase is respectively composed of an upper bridge arm, a lower bridge arm and an output filter inductor, each bridge arm is composed of N sub-modules and a bridge arm filter inductor, and a battery pack is directly connected with a half-bridge circuit or is connected with a small capacitor in parallel;

the control of the sub-modules is carried out by adopting the method for controlling the voltage of the direct current bus of the modular multilevel energy storage converter according to any one of the claims 1 to 5.

7. Many level of energy storage converter's of modularization change direct current bus voltage control system, characterized by includes:

8. A computing device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the steps of the method as claimed in claims 1-5 are performed when the program is executed by the processor.

9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any of the preceding claims 1-5.

10. A modular multilevel energy storage converter characterised in that the dc bus voltage control is performed by the method of any of claims 1 to 5.