CN112802741B - High-voltage gate oxide layer manufacturing method, high-voltage gate oxide layer and terminal equipment - Google Patents
High-voltage gate oxide layer manufacturing method, high-voltage gate oxide layer and terminal equipment Download PDFInfo
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Abstract
Description
技术领域technical field
本发明涉及集成电路制造领域，特别是涉及一种高压栅氧化层制作方法。本发明还涉及一种由所述高压栅氧化层制作方法制作的高压栅氧化层和一种用于执行所述 高压栅氧化层制作方法的终端设备。The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing a high-voltage gate oxide layer. The present invention also relates to a high-voltage gate oxide layer fabricated by the high-voltage gate oxide layer fabrication method and a terminal device for performing the high-voltage gate oxide layer fabrication method.
背景技术Background technique
在集成电路工艺技术中，为了提高器件的集成度和性能，按照等比例缩小原则，MOS(金属-氧化物-半导体)晶体管的工作电压随多晶栅的线宽的缩小而相应减小，栅 氧厚度也相应地不断减薄，例如在0.5um技术节点，CMOS器件的栅氧厚度在150埃左 右，而在65nm技术节点，低压CMOS的栅氧厚度仅为20埃左右。随着工艺节点的不 断推进，集成电路应用也不断丰富，仍有很多领域用到10V以上较高的工作电压，如 液晶显示器驱动芯片，电源控制芯片，汽车电子芯片，工控芯片等。在这些芯片中， 需要集成不同工作电压的MOS晶体管，工作电压在10V至40V范围的高压MOS晶体管， 其栅氧厚度需要对应增加，甚至需要在1000埃以上，这种栅氧就是高压栅氧。In the integrated circuit technology, in order to improve the integration and performance of the device, according to the principle of proportional reduction, the operating voltage of the MOS (metal-oxide-semiconductor) transistor decreases correspondingly with the reduction of the line width of the polycrystalline gate. Oxygen thickness has also been reduced accordingly. For example, at the 0.5um technology node, the gate oxide thickness of CMOS devices is about 150 angstroms, while at the 65nm technology node, the gate oxide thickness of low-voltage CMOS is only about 20 angstroms. With the continuous advancement of process nodes, the application of integrated circuits is also constantly enriched. There are still many fields that use higher operating voltages above 10V, such as LCD driver chips, power control chips, automotive electronic chips, and industrial control chips. In these chips, MOS transistors with different operating voltages need to be integrated. For high-voltage MOS transistors with operating voltages in the range of 10V to 40V, the gate oxide thickness needs to be increased correspondingly, even more than 1000 angstroms. Such gate oxides are high-voltage gate oxides.
55nm高压工艺平台为例，提供工作电压为高压(>30V)、中压(3～6V)、低压(1～1.5V) 的器件，各工作电压对应的栅氧厚度差异较大。高压栅氧厚度大于1000埃，其形成一般采用氮化层作为掩蔽层，遮蔽非高压栅氧区域，再以热氧化的方式形成。由于需 要兼顾中低压器件，不影响中低压器件的浅沟槽隔离结构，当浅沟槽隔离台阶较高， 氮化掩蔽层刻蚀时，容易在浅沟槽隔离台阶处造成氮化层残留。尤其是在工艺前层台 阶差较大的时，氮化层刻蚀残留更加难以控制，严重影响器件性能。Taking the 55nm high-voltage process platform as an example, devices with operating voltages of high voltage (>30V), medium voltage (3-6V) and low voltage (1-1.5V) are provided, and the gate oxide thickness corresponding to each operating voltage is quite different. The thickness of the high-voltage gate oxide is greater than 1000 angstroms, and the formation of the nitride layer is generally used as a masking layer to shield the non-high-voltage gate oxide region, and then formed by thermal oxidation. Due to the need to take into account the medium and low voltage devices without affecting the shallow trench isolation structure of the medium and low voltage devices, when the shallow trench isolation step is high and the nitride masking layer is etched, it is easy to cause a nitride layer residue at the shallow trench isolation step. Especially when the step difference of the front layer of the process is large, the etching residue of the nitride layer is more difficult to control, which seriously affects the performance of the device.
发明内容SUMMARY OF THE INVENTION
在发明内容部分中引入了一系列简化形式的概念,该简化形式的概念均为本领域现有技术简化，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分 并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意 味着试图确定所要求保护的技术方案的保护范围。A series of concepts in simplified form are introduced in the summary of the invention, and the concepts in the simplified form are all simplifications of the prior art in the art, which will be further described in detail in the detailed description. The summary of the present invention is not meant to attempt to limit the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.
本发明要解决的技术问题是提供一种在前层台阶差较大时(如：浅沟槽隔离台阶)能避免形成氮化物刻蚀残留的高压栅氧化层制作方法。The technical problem to be solved by the present invention is to provide a method for manufacturing a high voltage gate oxide layer that can avoid the formation of nitride etching residues when the front layer step difference is large (eg, shallow trench isolation steps).
相应的，本发明还提供了一种由所述高压栅氧化层制作方法制作的高压栅氧化层和一种用于执行所述高压栅氧化层制作方法的终端设备。Correspondingly, the present invention also provides a high-voltage gate oxide layer fabricated by the method for fabricating the high-voltage gate oxide layer and a terminal device for performing the fabrication method for the high-voltage gate oxide layer.
为解决上述技术问题，本发明提供的高压栅氧化层制作方法，包括以下步骤：In order to solve the above technical problems, the method for fabricating a high voltage gate oxide layer provided by the present invention includes the following steps:
S1，提供衬底，在衬底上形成浅沟槽隔离；S1, providing a substrate, and forming shallow trench isolation on the substrate;
S2，淀积第一厚度的氮化层；S2, depositing a nitride layer of a first thickness;
S3，淀积第二厚度的氧化层；S3, depositing an oxide layer of a second thickness;
S4，旋涂光刻胶，将高压栅氧化层区域打开，刻蚀去除高压栅氧化层区域的氧化层，去除光刻胶；S4, spin coating photoresist, open the high-voltage gate oxide layer region, etch and remove the oxide layer in the high-voltage gate oxide layer region, and remove the photoresist;
S5，将氧化层作为掩蔽层，刻蚀去除高压栅氧化层区域的氮化层；S5, using the oxide layer as a masking layer, etching and removing the nitride layer in the high voltage gate oxide layer region;
S6，刻蚀去除剩余氧化层，同时刻蚀去除高压栅氧化层区域的浅沟槽隔离台阶；S6, etching and removing the remaining oxide layer, and simultaneously etching and removing the shallow trench isolation step in the high-voltage gate oxide layer region;
S7，制作高压栅氧化层，刻蚀去除剩余的氮化层。S7, a high voltage gate oxide layer is formed, and the remaining nitride layer is removed by etching.
可选择的，进一步改进所述的高压栅氧化层制作方法，所述第一厚度的范围是200埃～500埃。Optionally, the method for fabricating the high voltage gate oxide layer is further improved, and the first thickness ranges from 200 angstroms to 500 angstroms.
可选择的，进一步改进所述的高压栅氧化层制作方法，所述第二厚度的范围是200埃～500埃。Optionally, to further improve the method for fabricating the high voltage gate oxide layer, the second thickness ranges from 200 angstroms to 500 angstroms.
可选择的，进一步改进所述的高压栅氧化层制作方法，步骤S4中采用湿法刻蚀 去除高压栅氧化层区域的氧化层。Optionally, the method for manufacturing the high voltage gate oxide layer is further improved. In step S4, wet etching is used to remove the oxide layer in the high voltage gate oxide layer region.
可选择的，进一步改进所述的高压栅氧化层制作方法，步骤S5中采用湿法刻蚀 去除压栅氧化层区域的氮化层。Optionally, the method for manufacturing the high voltage gate oxide layer is further improved. In step S5, wet etching is used to remove the nitride layer in the voltage gate oxide layer region.
可选择的，进一步改进所述的高压栅氧化层制作方法，步骤S6中采用湿法刻蚀 去除剩余的氧化层。Optionally, to further improve the method for fabricating the high voltage gate oxide layer, in step S6, wet etching is used to remove the remaining oxide layer.
可选择的，进一步改进所述的高压栅氧化层制作方法，步骤S7中采用湿法刻蚀 去除剩余的氮化层。Optionally, to further improve the method for fabricating the high voltage gate oxide layer, in step S7, wet etching is used to remove the remaining nitride layer.
可选择的，进一步改进所述的高压栅氧化层制作方法，其能用于包括但不限于55nm高压工艺平台器件。Optionally, the method for fabricating the high voltage gate oxide layer is further improved, which can be used for devices including but not limited to 55nm high voltage process platform.
本发明提供一种高压栅氧化层，其由上述任意一项所述的高压栅氧化层制作方法制作。The present invention provides a high-voltage gate oxide layer, which is fabricated by the method for fabricating the high-voltage gate oxide layer described in any one of the above.
本发明提供一种终端设备，其用于执行上述任意一项所述的高压栅氧化层制作方法中的步骤。The present invention provides a terminal device, which is used for performing the steps in any one of the above-mentioned methods for fabricating a high-voltage gate oxide layer.
本发明在第一厚度(200埃～500埃)的氮化层层上淀积第二厚度(200～500A)的氧化层，通过光刻将高压栅氧区域打开，利用湿法腐蚀的各向同性及高选择比特性，腐 蚀高压栅氧区域上层氧化层，光刻胶去除后，继续采用湿法腐蚀工艺去除下层氮化层， 利用湿法腐蚀各向同性的特性，解决氮化层在浅沟槽隔离边缘残留的问题，同时利用 其高选择比特性，保留了前层必要的台阶差异。由于采用纯湿法工艺，避免了干法工 艺对高压栅氧区域的刻蚀损伤。因此，本发明能避免形成氮化物刻蚀残留，提高器件 综合性能。In the present invention, an oxide layer with a second thickness (200-500A) is deposited on a nitride layer with a first thickness (200-500A), the high-voltage gate oxide region is opened by photolithography, and the wet etching is used in all directions. Isotropic and high selectivity characteristics, etch the upper oxide layer of the high voltage gate oxide region, after the photoresist is removed, continue to use the wet etching process to remove the lower nitride layer, and use the isotropic characteristics of wet etching to solve the problem of the shallow nitride layer. The trench isolates the problem of edge residue, while taking advantage of its high selectivity, the necessary step difference of the front layer is preserved. Due to the pure wet process, the etching damage to the high voltage gate oxide region by the dry process is avoided. Therefore, the present invention can avoid the formation of nitride etching residues and improve the overall performance of the device.
附图说明Description of drawings
本发明附图旨在示出根据本发明的特定示例性实施例中所使用的方法、结构和/或材料的一般特性，对说明书中的描述进行补充。然而，本发明附图是未按比例绘制 的示意图，因而可能未能够准确反映任何所给出的实施例的精确结构或性能特点，本 发明附图不应当被解释为限定或限制由根据本发明的示例性实施例所涵盖的数值或 属性的范围。下面结合附图与具体实施方式对本发明作进一步详细的说明：The drawings of the present invention are intended to supplement the description in the specification by illustrating the general characteristics of methods, structures and/or materials used in certain exemplary embodiments according to the present invention. However, the drawings of the present invention are schematic representations not to scale and thus may not accurately reflect the precise structural or performance characteristics of any given embodiment, and the drawings of the present invention should not be construed as limiting or limiting by the present invention. The range of values or properties encompassed by the exemplary embodiments. The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments:
图1是本发明流程示意图。Figure 1 is a schematic flow chart of the present invention.
图2本发明第二实施例中间结构示意图一。FIG. 2 is a schematic diagram 1 of the intermediate structure of the second embodiment of the present invention.
图3本发明第二实施例中间结构示意图二。FIG. 3 is a second schematic diagram of the intermediate structure of the second embodiment of the present invention.
图4本发明第二实施例中间结构示意图三。FIG. 4 is a schematic diagram 3 of the intermediate structure of the second embodiment of the present invention.
图5本发明第二实施例中间结构示意图四。FIG. 5 is a schematic diagram 4 of the intermediate structure of the second embodiment of the present invention.
图6本发明第二实施例中间结构示意图五。FIG. 6 is a schematic diagram V of the intermediate structure of the second embodiment of the present invention.
图7本发明第二实施例中间结构示意图六。FIG. 7 is a schematic diagram 6 of the intermediate structure of the second embodiment of the present invention.
具体实施方式Detailed ways
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所公开的内容充分地了解本发明的其他优点与技术效果。本发明还可以通过不同的 具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点加以应 用，在没有背离发明总的设计思路下进行各种修饰或改变。需说明的是，在不冲突的 情况下，以下实施例及实施例中的特征可以相互组合。本发明下述示例性实施例可以 多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的具体实施例。应当 理解的是，提供这些实施例是为了使得本发明的公开彻底且完整，并且将这些示例性 具体实施例的技术方案充分传达给本领域技术人员。The embodiments of the present invention are described below through specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without departing from the general design idea of the invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other under the condition of no conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
应当理解的是，当元件被称作“连接”或“结合”到另一元件时，该元件可以直 接连接或结合到另一元件，或者可以存在中间元件。不同的是，当元件被称作“直接 连接”或“直接结合”到另一元件时，不存在中间元件。在全部附图中，相同的附图 标记始终表示相同的元件。此外，还应当理解的是，尽管在这里可以使用术语“第一”、 “第二”等来描述不同的元件、参数、组件、区域、层和/或部分，但是这些元件、 参数、组件、区域、层和/或部分不应当受这些术语的限制。这些术语仅是用来将一 个元件、参数、组件、区域、层或部分与另一个元件、参数、组件、区域、层或部分 区分开来。因此，在不脱离根据本发明的示例性实施例的教导的情况下，以下所讨论 的第一元件、参数、组件、区域、层或部分也可以被称作第二元件、参数、组件、区 域、层或部分。It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. The difference is that when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The same reference numbers refer to the same elements throughout the drawings. In addition, it will also be understood that although the terms "first", "second", etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, Regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region without departing from the teachings according to example embodiments of the present invention , layer or section.
第一实施例；first embodiment;
如图1所示，本发明提供一种高压栅氧化层制作方法，包括以下步骤：As shown in FIG. 1 , the present invention provides a method for fabricating a high-voltage gate oxide layer, comprising the following steps:
S1，提供衬底，在衬底上形成浅沟槽隔离；S1, providing a substrate, and forming shallow trench isolation on the substrate;
S2，淀积第一厚度的氮化层；S2, depositing a nitride layer of a first thickness;
S3，淀积第二厚度的氧化层；S3, depositing an oxide layer of a second thickness;
S4，旋涂光刻胶，将高压栅氧化层区域打开，刻蚀去除高压栅氧化层区域的氧化层，去除光刻胶；S4, spin coating photoresist, open the high-voltage gate oxide layer region, etch and remove the oxide layer in the high-voltage gate oxide layer region, and remove the photoresist;
S5，将氧化层作为掩蔽层，刻蚀去除高压栅氧化层区域的氮化层；S5, using the oxide layer as a masking layer, etching and removing the nitride layer in the high voltage gate oxide layer region;
S6，刻蚀去除剩余氧化层，同时刻蚀去除高压栅氧化层区域的浅沟槽隔离台阶；S6, etching and removing the remaining oxide layer, and simultaneously etching and removing the shallow trench isolation step in the high-voltage gate oxide layer region;
S7，制作高压栅氧化层，刻蚀去除剩余的氮化层。S7, a high voltage gate oxide layer is formed, and the remaining nitride layer is removed by etching.
第二实施例；second embodiment;
本发明提供一种高压栅氧化层制作方法，包括以下步骤：The present invention provides a method for fabricating a high voltage gate oxide layer, comprising the following steps:
S1，如图2所示，提供衬底，在衬底上形成浅沟槽隔离；S1, as shown in FIG. 2, a substrate is provided, and shallow trench isolation is formed on the substrate;
S2，淀积200埃～500埃的氮化层；S2, depositing a nitride layer of 200 angstroms to 500 angstroms;
优选氮化层厚度为，200埃、250埃、300埃、350埃、400埃、450埃或500埃；Preferably, the thickness of the nitride layer is 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms or 500 angstroms;
S3，淀积200埃～500埃的氧化层；S3, depositing an oxide layer of 200 angstroms to 500 angstroms;
优选氧化层厚度为，200埃、250埃、300埃、350埃、400埃、450埃或500埃；Preferably, the thickness of the oxide layer is 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms or 500 angstroms;
S4，如图3和图4所示，旋涂光刻胶，将高压栅氧化层区域打开，采用湿法刻蚀 去除高压栅氧化层区域的氧化层，去除光刻胶；S4, as shown in Figure 3 and Figure 4, spin coating photoresist, open the high voltage gate oxide layer region, adopt wet etching to remove the oxide layer in the high voltage gate oxide layer region, remove the photoresist;
S5，如图5所示，将氧化层作为掩蔽层，采用湿法刻蚀去除压高压栅氧化层区域 的氮化层；S5, as shown in Figure 5, the oxide layer is used as a masking layer, and wet etching is used to remove the nitride layer in the high voltage gate oxide layer region;
S6，如图6所示，采用湿法刻蚀去除剩余氧化层，同时刻蚀去除高压栅氧化层区 域的浅沟槽隔离台阶；S6, as shown in Figure 6, the remaining oxide layer is removed by wet etching, and the shallow trench isolation step in the high voltage gate oxide layer region is removed by etching simultaneously;
S7，如图7所示，制作高压栅氧化层，采用湿法刻蚀去除剩余的氮化层。S7 , as shown in FIG. 7 , a high voltage gate oxide layer is formed, and the remaining nitride layer is removed by wet etching.
需要说明的是，无论上述第一实施例或第二实施例均能用于包括但不限于55nm高压工艺平台器件。It should be noted that both the above-mentioned first embodiment or the second embodiment can be used for devices including but not limited to 55nm high-voltage process platform devices.
第二实施例；second embodiment;
本发明提供一种高压栅氧化层，其由上述第一实施例或第二实施例任意一项所述的高压栅氧化层制作方法制作。The present invention provides a high-voltage gate oxide layer, which is fabricated by the method for fabricating a high-voltage gate oxide layer described in any one of the first embodiment or the second embodiment.
第四实施例；fourth embodiment;
本发明提供一种终端设备，其用于执行上述第一实施例或第二实施例任意一项所述的高压栅氧化层制作方法中的步骤。The present invention provides a terminal device, which is used for performing the steps in the method for fabricating a high voltage gate oxide layer described in any one of the first embodiment or the second embodiment.
除非另有定义，否则这里所使用的全部术语(包括技术术语和科学术语)都具有与本发明所属领域的普通技术人员通常理解的意思相同的意思。还将理解的是，除非 这里明确定义，否则诸如在通用字典中定义的术语这类术语应当被解释为具有与它们 在相关领域语境中的意思相一致的意思，而不以理想的或过于正式的含义加以解释。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary should be construed to have meanings consistent with their meanings in the relevant art context, rather than ideally or excessively The formal meaning is explained.
以上通过具体实施方式和实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多 变形和改进，这些也应视为本发明的保护范围。The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the present invention. Without departing from the principles of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.
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| US6159844A (en) * | 1998-05-29 | 2000-12-12 | Philips Electronics North America Corp. | Fabrication of gate and diffusion contacts in self-aligned contact process |
| CN102103992A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing gate oxide |
| CN102243995A (en) * | 2011-06-23 | 2011-11-16 | 上海集成电路研发中心有限公司 | Integration method of gate oxide with different thicknesses in high-voltage process |
| CN105225935A (en) * | 2015-09-22 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | There is trench gate structure and the manufacture method thereof of shield grid |
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| US6159844A (en) * | 1998-05-29 | 2000-12-12 | Philips Electronics North America Corp. | Fabrication of gate and diffusion contacts in self-aligned contact process |
| CN102103992A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing gate oxide |
| CN102243995A (en) * | 2011-06-23 | 2011-11-16 | 上海集成电路研发中心有限公司 | Integration method of gate oxide with different thicknesses in high-voltage process |
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