KR20040107988A - Method of manufacturing dual gate oxide film - Google Patents
Method of manufacturing dual gate oxide film Download PDFInfo
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- KR20040107988A KR20040107988A KR1020030038715A KR20030038715A KR20040107988A KR 20040107988 A KR20040107988 A KR 20040107988A KR 1020030038715 A KR1020030038715 A KR 1020030038715A KR 20030038715 A KR20030038715 A KR 20030038715A KR 20040107988 A KR20040107988 A KR 20040107988A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02249—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by combined oxidation and nitridation performed simultaneously
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
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Abstract
Description
본 발명은 반도체 소자의 듀얼 게이트 산화막 제조방법에 관한 것으로, 특히 고전압 구동소자 영역에서 고전압용 게이트 산화막과 저전압용 게이트 산화막의 계면에 질소 챠지 트랩(Nitrogen Charge Trap)이 발생되는 것을 방지할 수 있는 듀얼 게이트 산화막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dual gate oxide film of a semiconductor device. In particular, a dual charge oxide trap which can prevent a nitrogen charge trap from being generated at an interface between a high voltage gate oxide film and a low voltage gate oxide film in a high voltage driving device region. A method of manufacturing a gate oxide film.
일반적으로, 온-칩(On-Chip)상에서 동시에 서로 다른 트랜스컨덕턴스 (Transconductance)를 갖는 소자를 구현하는 기술이 제안되고 있으며, 이러한 기술은 저전압 구동소자와 고전압 구동소자를 구현하는데 적용되고 있다.In general, a technique for implementing a device having different transconductances on the on-chip at the same time has been proposed, and this technique has been applied to implement a low voltage driving device and a high voltage driving device.
고전압 및 저전압 구동소자를 동시에 구현시킬 때, 통상 두 번의 산화 공정을 실시하여 고전압용 게이트 산화막을 두껍게, 저전압용 게이트 산화막을 얇게 형성시킨다.When the high voltage and the low voltage driving device are simultaneously implemented, two oxidation processes are usually performed to make the high voltage gate oxide film thick and the low voltage gate oxide film thin.
그런데, 저전압 구동소자는 낮은 구동전압에서도 안정된 소자 성능 유지를 위하여 높은 게이트 캐패시턴스를 요구하고 있다. 이를 위해 저전압 구동소자의 게이트 산화막을 NO 어닐공정(Nitrogen-Oxygen Anneal Process)으로 질화시켜 유전상수를 높이는 기술이 연구되고 있다.However, low voltage driving devices require high gate capacitance to maintain stable device performance even at low driving voltages. To this end, a technique of increasing the dielectric constant by nitriding a gate oxide film of a low voltage driving device by a nitrogen-oxygen anneal process has been studied.
이와 같이, NO 어닐 공정이 도입된 고전압 구동소자 및 저전압 구동소자의 듀얼 게이트 산화막은 DRAM 및 SRAM 뿐만 아니라 NAND Flash등 여러 반도체 소자에 적용되고 있다.As such, the dual gate oxide film of the high voltage driving device and the low voltage driving device in which the NO annealing process is introduced is applied to various semiconductor devices such as NAND Flash as well as DRAM and SRAM.
도 1은 종래 듀얼 게이트 산화막 제조방법을 설명하기 위한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining a conventional method of manufacturing a dual gate oxide film.
도 1 참조하면, 고전압 구동소자 영역(HV)과 저전압 구동소자 영역(LV)이 정의된 반도체 기판(11)이 제공된다. 고전압 구동소자 영역(HV)의 반도체 기판(11) 표면에 제 1 게이트 산화막(12)을 두껍게 예를 들어, 약 350Å의 두께로 형성하고, 제 1 게이트 산화막(12)을 포함한 저전압 구동소자 영역(LV)의 반도체 기판(11) 표면에 제 2 게이트 산화막(13)을 얇게 예를 들어, 약 80Å의 두께로 형성한다. 이후, NO 어닐공정을 실시한다.Referring to FIG. 1, a semiconductor substrate 11 in which a high voltage driving device region HV and a low voltage driving device region LV are defined is provided. The first gate oxide film 12 is thickly formed on the surface of the semiconductor substrate 11 in the high voltage driving device region HV, for example, about 350 kV thick, and the low voltage driving device region including the first gate oxide film 12 is formed. The second gate oxide film 13 is thinly formed on the surface of the semiconductor substrate 11 of LV, for example, to a thickness of about 80 kPa. Thereafter, the NO annealing process is performed.
NO 어닐공정에 의해 저전압 구동소자 영역(LV)에는 제 2 게이트 산화막(13)이 질화된 저전압용 NO 게이트 산화막(13N)이 형성되고, 고전압 구동소자 영역(HV)에는 적층된 제 1 및 2 게이트 산화막(12 및 13)이 질화된 고전압용 NO 게이트 산화막(12N)이 형성된다.A low voltage NO gate oxide film 13N in which the second gate oxide film 13 is nitrided is formed in the low voltage driving device region LV by the NO annealing process, and the first and second gates stacked in the high voltage driving device region HV. A high voltage NO gate oxide film 12N in which the oxide films 12 and 13 are nitrided is formed.
그런데, 제 1 게이트 산화막(12)을 고전압 구동소자 영역(HV)에 남기기 위해서 포토레지스트 패턴을 이용한 식각 공정을 실시하게 되고, 이후 포토레지스트 패턴 스트립 공정을 실시하여 포토레지스트 패턴을 제거하는데, 이때 제 1 게이트 산화막(12)의 표면은 손상(Attack)을 당하게 된다. 이 손상부는 후속 제 2 게이트 산화막(13) 형성 공정 및 NO 어닐 공정시에, 도 1에 도시된 바와같이, 질소 챠지 트랩(NCT)으로 작용하여, 결국 고전압용 NO 게이트 산화막(12N)의 특성을 저하시키는 요인이 되어 소자의 전기적 특성 및 신뢰성을 저하시키게 된다.However, in order to leave the first gate oxide layer 12 in the high voltage driving device region HV, an etching process using a photoresist pattern is performed, and then a photoresist pattern strip process is performed to remove the photoresist pattern. The surface of the one-gate oxide film 12 is damaged. This damage portion acts as a nitrogen charge trap (NCT) as shown in FIG. 1 during the subsequent process of forming the second gate oxide film 13 and the NO annealing process, thereby eventually characterizing the characteristics of the high voltage NO gate oxide film 12N. It is a factor of deterioration, thereby lowering the electrical characteristics and reliability of the device.
따라서, 본 발명은 고전압 구동소자 영역에서 고전압용 게이트 산화막과 저전압용 게이트 산화막의 계면에 질소 챠지 트랩이 발생되는 것을 방지하여 소자의 전기적 특성 및 소자의 신뢰성을 향상시킬 수 있는 듀얼 게이트 산화막 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a method of manufacturing a dual gate oxide film which can improve the electrical characteristics and the reliability of the device by preventing nitrogen charge traps from occurring at the interface between the high voltage gate oxide film and the low voltage gate oxide film in the region of the high voltage driving device. The purpose is to provide.
도 1은 종래 듀얼 게이트 산화막 제조방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a conventional method of manufacturing a dual gate oxide film.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 듀얼 게이트 산화막 제조방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of devices for describing a method of manufacturing a dual gate oxide film according to an exemplary embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 21: 반도체 기판 12, 22: 제 1 게이트 산화막11, 21: semiconductor substrate 12, 22: first gate oxide film
13, 23: 제 2 게이트 산화막 12N, 22N: 고전압 NO 게이트 산화막13, 23: second gate oxide film 12N, 22N: high voltage NO gate oxide film
13N, 23N: 저전압 NO 게이트 산화막13N, 23N: low voltage NO gate oxide
30: 포토레지스트 패턴 NCT: 질소 챠지 트랩30: photoresist pattern NCT: nitrogen charge trap
HV: 고전압 구동소자 영역 LV: 저전압 구동소자 영역HV: high voltage drive element area LV: low voltage drive element area
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 듀얼 게이트 산화막 제조방법은 고전압 구동소자 영역 및 저전압 구동소자 영역이 정의된 반도체 기판 상에 제 1 게이트 산화막을 형성하는 단계; 상기 고전압 구동소자 영역을 제외한 부분이 개방되도록 포토레지스트 패턴을 상기 제 1 게이트 산화막 상에 형성하고, 상기 제 1 게이트 산화막의 노출된 부분을 제거하는 단계; 습식 식각 공정으로 상기 포토레지스트 패턴을 제거하는 단계; 상기 노출된 제 1 게이트 산화막의 표면을 O3플라즈마 처리하는 단계; 상기 제 1 게이트 산화막을 포함한 상기 저전압 구동소자 영역의 반도체 기판 상에 제 2 게이트 산화막을 형성하는 단계; 및 NO 어닐공정을 실시하고, 이로 인하여 상기 제 2 게이트 산화막이 질화된 저전압용 NO 게이트 산화막이 형성되고, 제 1 및 2 게이트 산화막이 질화된 고전압용 NO 게이트 산화막이 형성되는 단계를 포함한다.A dual gate oxide film manufacturing method according to an embodiment of the present invention for achieving the above object comprises the steps of forming a first gate oxide film on a semiconductor substrate defined a high voltage driving device region and a low voltage driving device region; Forming a photoresist pattern on the first gate oxide layer so that portions other than the high voltage driving device region are opened, and removing an exposed portion of the first gate oxide layer; Removing the photoresist pattern by a wet etching process; O 3 plasma treatment of the exposed first gate oxide layer; Forming a second gate oxide film on the semiconductor substrate in the low voltage driving device region including the first gate oxide film; And performing a NO annealing process, thereby forming a low voltage NO gate oxide film in which the second gate oxide film is nitrided, and forming a high voltage NO gate oxide film in which the first and second gate oxide films are nitrided.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세하게 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 듀얼 게이트 산화막 제조방법을 설명하기 위한 소자의 단면도이다.2A through 2E are cross-sectional views of devices for describing a method of manufacturing a dual gate oxide film according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 고전압 구동소자 영역(HV) 및 저전압 구동소자 영역(LV)이 정의(Define)된 반도체 기판(21) 상에 제 1 게이트 산화막(22)을 형성한다. 고전압 구동소자 영역(HV)을 제외한 부분이 개방(Open)되도록 포토레지스트 패턴(30)을 제 1 게이트 산화막(22) 상에 형성한다. 포토레지스트 패턴(30)을 식각 마스크로 한 식각 공정으로 제 1 게이트 산화막(22)의 노출된 부분을 제거하고, 이로 인하여 제 1 게이트 산화막(22)은 고전압 구동소자 영역(HV)의 반도체 기판(21) 상에만 존재하게 된다. 제 1 게이트 산화막(22)은 고전압용으로 사용되며, 산화 공정에 의해 300 ~ 500Å의 두께로 형성한다.Referring to FIG. 2A, the first gate oxide layer 22 is formed on the semiconductor substrate 21 on which the high voltage driving device region HV and the low voltage driving device region LV are defined. The photoresist pattern 30 is formed on the first gate oxide film 22 so that portions except the high voltage driving device region HV are open. An exposed portion of the first gate oxide layer 22 is removed by an etching process using the photoresist pattern 30 as an etching mask, and thus, the first gate oxide layer 22 may be formed in the semiconductor substrate of the high voltage driving device region HV. 21) only exist on the phase. The first gate oxide film 22 is used for high voltage and is formed to a thickness of 300 to 500 kV by an oxidation process.
도 2b를 참조하면, 제 1 게이트 산화막(22)의 표면이 손상 당하는 것을 최대한 방지하기 위하여, 습식 식각 방식으로 포토레지스트 패턴(30)을 제거한다. 습식 식각 공정은 H2SO4, H2O2및 DI 혼합 용액을 사용한다.Referring to FIG. 2B, in order to prevent damage to the surface of the first gate oxide layer 22 as much as possible, the photoresist pattern 30 is removed by a wet etching method. The wet etching process uses a mixture of H 2 SO 4 , H 2 O 2 and DI.
도 2c를 참조하면, 습식 식각 공정으로 포토레지스트 패턴(30)을 완전히 제거한 후, 노출된 제 1 게이트 산화막(22)의 표면에 잔존하는 식각 손상을 O3플라즈마 처리를 통하여 제거시켜, 제 1 게이트 산화막(22)의 표면의 깨끗한 상태가 되게한다. O3플라즈마 처리 조건은 50 ~ 500mT의 압력과 O3분위기에서 1GHz의 마이크로파 플라즈마를 사용한다.Referring to FIG. 2C, after the photoresist pattern 30 is completely removed by the wet etching process, the etch damage remaining on the exposed surface of the first gate oxide layer 22 is removed through an O 3 plasma treatment, and the first gate is removed. The surface of the oxide film 22 is brought into a clean state. O 3 plasma treatment conditions using a microwave plasma of 1GHz in a pressure of 50 ~ 500mT and O 3 atmosphere.
도 2d를 참조하면, 제 1 게이트 산화막(22)을 포함한 저전압 구동소자 영역(LV)의 반도체 기판(21) 상에 제 2 게이트 산화막(23)을 형성한다. 제 2 게이트 산화막(23)은 저전압용 및 고전압용으로 사용되며, 산화 공정에 의해 60 내지 100Å의 두께로 형성한다.Referring to FIG. 2D, the second gate oxide layer 23 is formed on the semiconductor substrate 21 of the low voltage driving element region LV including the first gate oxide layer 22. The second gate oxide film 23 is used for low voltage and high voltage, and is formed to a thickness of 60 to 100 kV by an oxidation process.
제 2e를 참조하면, 고전압 구동소자 영역(HV)에는 제 1 및 제 2 게이트 산화막(22 및 23)이 적층되어 있고, 저전압 구동소자 영역(LV)에는 제 2 게이트 산화막(23)만이 있는 상태에서 인-시튜로 NO 어닐공정을 실시한다. NO 어닐공정 동안에 질소가 게이트 산화막들(22 및 23) 내부로 확산되어 저전압 구동소자 영역(LV)에는 제 2 게이트 산화막(23)이 질화된 저전압용 NO 게이트 산화막(23N)이 형성되고, 고전압 구동소자 영역(HV)에는 적층된 제 1 및 2 게이트 산화막(22 및 23)이 질화된 고전압용 NO 게이트 산화막(22N)이 형성된다.Referring to the second 2e, the first and second gate oxide films 22 and 23 are stacked in the high voltage driving device region HV, and only the second gate oxide film 23 is in the low voltage driving device region LV. The NO annealing process is performed in-situ. During the NO annealing process, nitrogen diffuses into the gate oxide films 22 and 23 to form a low voltage NO gate oxide film 23N in which the second gate oxide film 23 is nitrided in the low voltage driving device region LV, and the high voltage driving is performed. In the device region HV, a high voltage NO gate oxide film 22N in which the stacked first and second gate oxide films 22 and 23 are nitrided is formed.
상술한 바와 같이, 본 발명은 포토레지스트 패턴을 습식 식각 방식으로 제거한 후, 노출된 고전압용 게이트 산화막 표면에 잔존하는 손상부를 O3플라즈마 처리를 통하여 제거시키므로, 고전압 구동소자 영역에서 고전압용 게이트 산화막과 저전압용 게이트 산화막의 계면에 질소 챠지 트랩이 발생되지 않아 고전압 구동소자의 게이트 산화막 특성이 향상되고, 따라서 소자의 전기적 특성 및 소자의 신뢰성을 향상시킬 수 있다.As described above, the present invention removes the photoresist pattern by wet etching, and then removes the damage remaining on the exposed high voltage gate oxide film surface by O 3 plasma treatment. Since the nitrogen charge trap is not generated at the interface of the low voltage gate oxide film, the gate oxide film characteristic of the high voltage driving device is improved, and thus, the electrical characteristics of the device and the reliability of the device can be improved.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100906058B1 (en) * | 2007-11-05 | 2009-07-03 | 주식회사 동부하이텍 | Method for fabricating a multiple gate insulated layer in a semiconductor |
| KR100955673B1 (en) * | 2007-06-29 | 2010-05-06 | 주식회사 하이닉스반도체 | Method for fabricating dual gate in semicondutor device |
| US9275993B2 (en) | 2012-09-07 | 2016-03-01 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN105448686A (en) * | 2014-06-23 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Grid oxidation layer manufacturing method and semiconductor device manufacturing method |
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| KR100528445B1 (en) * | 1997-12-10 | 2006-02-13 | 삼성전자주식회사 | A method of forming dual gate oxide |
| KR20010065789A (en) * | 1999-12-30 | 2001-07-11 | 박종섭 | Method For Forming The Dual Gate Oxide Of Semiconductor Device |
| KR20020009213A (en) * | 2000-07-25 | 2002-02-01 | 윤종용 | Method for forming dual-gate oxide layer in semiconductor device |
| KR100327349B1 (en) * | 2001-10-19 | 2002-03-06 | 윤종용 | Method for fabricating of double oxide layer of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100955673B1 (en) * | 2007-06-29 | 2010-05-06 | 주식회사 하이닉스반도체 | Method for fabricating dual gate in semicondutor device |
| KR100906058B1 (en) * | 2007-11-05 | 2009-07-03 | 주식회사 동부하이텍 | Method for fabricating a multiple gate insulated layer in a semiconductor |
| US9275993B2 (en) | 2012-09-07 | 2016-03-01 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN105448686A (en) * | 2014-06-23 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Grid oxidation layer manufacturing method and semiconductor device manufacturing method |
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