CN112802520B - SRAM memory cell and memory - Google Patents

SRAM memory cell and memory Download PDF

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Publication number
CN112802520B
CN112802520B CN202110119716.3A CN202110119716A CN112802520B CN 112802520 B CN112802520 B CN 112802520B CN 202110119716 A CN202110119716 A CN 202110119716A CN 112802520 B CN112802520 B CN 112802520B
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switch circuit
circuit
sram memory
memory cell
control signal
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CN112802520A (en
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宿晓慧
苏泽鑫
李博
罗家俊
韩郑生
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

The invention discloses an SRAM memory cell and an SRAM memory, relates to the technical field of circuit design, and aims to improve data security and reduce the area and power consumption of the SRAM memory. The SRAM memory cell includes: the data latch circuit, the first switch circuit, the second switch circuit, the third switch circuit and the memory circuit. The data latch circuit is provided with a first output end, a second output end and a conversion node. The first switch circuit is connected in series between the second output terminal and the switching node. The second switching circuit is connected in series between the first output terminal and the first terminal of the memory circuit. The third switch circuit is connected in series between the conversion node and the first terminal of the memory circuit. The second terminal of the memory circuit is electrically connected to the ground terminal. The SRAM memory comprises the SRAM memory cell provided by the technical scheme.

Description

SRAM memory cell and memory
Technical Field
The invention relates to the technical field of circuit design, in particular to an SRAM memory cell and a memory.
Background
In order to protect data security, once the security chip detects unauthorized Access, it will cut off the power supply of Static Random-Access Memory (SRAM) to avoid the attacker to steal data. However, the static random access memory has the problem of information residue, and part of information stored in the static random access memory before power failure can be recovered by a method of aging stamping.
The aging imprinting means that when a certain memory cell stores fixed data for a long time, two symmetrical Metal-Oxide-Semiconductor Field-Effect transistors (MOS transistors) will generate different degrees of Bias Temperature Instability (BTI) aging Effect, which generates a permanent threshold voltage mismatch, resulting in that the memory cell has a certain probability (about 10% -20%) to read an initial power-on value opposite to the original stored value after being powered on.
In the prior art, the storage data is continuously exchanged between two nodes through the SRAM storage unit with a master-slave structure, and the aging problem is balanced, so that the threshold mismatch is eliminated. However, the SRAM memory cell of the master-slave structure has a complex structure, and introduces a large number of control signals, which increases the area and power consumption of the SRAM memory.
Disclosure of Invention
The invention aims to provide an SRAM memory cell and a memory, which are used for improving data security, simplifying the SRAM memory cell and reducing the area and power consumption of the SRAM memory.
In a first aspect, the present invention provides an SRAM memory cell, comprising: the data latch circuit, first switching circuit, second switching circuit, third switching circuit and memory circuit. The data latch circuit is provided with a first output end, a second output end and a conversion node. The first switch circuit is connected in series between the second output terminal and the switching node. The second switching circuit is connected in series between the first output terminal and the first terminal of the memory circuit. The third switch circuit is connected in series between the conversion node and the first terminal of the memory circuit. The second terminal of the memory circuit is electrically connected to the ground terminal.
When the first switch circuit, the second switch circuit and the third switch circuit are all controlled by the initial control signal, the first output end has a first potential, the second output end has a second potential, and the data latch circuit charges the storage circuit. When the first switch circuit, the second switch circuit and the third switch circuit are all controlled by the turnover control signal, the storage circuit discharges to the data latch, the first output end has a second potential, and the second output end has a first potential.
Compared with the prior art, the SRAM storage unit provided by the invention comprises a data latch circuit, a first switch circuit, a second switch circuit, a third switch circuit and a storage circuit. The data latch circuit is provided with a first output end, a second output end and a conversion node. The first switch circuit is connected in series between the second output terminal and the switching node. The second switching circuit is connected in series between the first output terminal and the first terminal of the memory circuit. The third switch circuit is connected in series between the conversion node and the first terminal of the memory circuit. The second terminal of the memory circuit is electrically connected to the ground terminal. Under the control of the initial control signal and the inversion control signal, the states of the first switch circuit, the second switch circuit, the third switch circuit and the storage circuit are changed, so that the potential of the first output end and the potential of the second output end of the data latch circuit are inverted.
It should be understood that the data latch circuit includes two cross-coupled inverters, each inverter consisting of one P-type transistor and one N-type transistor. The potential of the first output end and the potential of the second output end of the data latch circuit are inverted, so that the four transistors can alternately carry out BTI aging effect. That is to say, the potential of the first output end and the potential of the second output end of the data latch circuit are inverted, so that the aging of the four transistors can be balanced, the threshold mismatch caused by the aging of the transistors can be relieved or eliminated, and the data safety of the SRAM memory cell can be enhanced.
Meanwhile, compared with the SRAM memory cell with a master-slave structure in the prior art, the SRAM memory cell provided by the invention has the advantages that the SRAM memory cell is simplified, control signals are reduced, and the area and power consumption of an SRAM memory can be reduced.
In a second aspect, the present invention also provides an SRAM memory, including the SRAM memory cell provided in the first aspect.
Compared with the prior art, the beneficial effects of the SRAM memory provided by the invention are the same as those of the SRAM memory cell in the first aspect, and are not repeated herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art transmission gate;
FIG. 2 is a schematic diagram of an inverter according to the prior art;
FIG. 3 is a diagram illustrating a prior art SRAM cell with a master-slave structure;
FIG. 4 is a schematic diagram of a complete structure of an SRAM memory cell according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating data inversion simulation of an SRAM memory cell according to an embodiment of the present invention;
FIG. 6 is a timing diagram of reading and writing of an SRAM memory cell according to an embodiment of the present invention
FIG. 7 is a first diagram illustrating a partial structure of an SRAM memory cell according to an embodiment of the present invention;
FIG. 8 is a second schematic diagram illustrating a partial structure of an SRAM memory cell according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a portion of an SRAM memory cell according to an embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating a fourth partial structure of an SRAM memory cell provided in an embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating a partial structure of an SRAM memory cell according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a partial structure of a SRAM memory cell according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The BTI aging effect mainly refers to Negative-bias Temperature Instability (NBTI) and Positive-bias Temperature Instability (PBTI). Wherein NBTI is an effect for P-type transistors under high temperature and negative bias conditions and PBTI is an effect for N-type transistors under high temperature and positive bias conditions. The BTI effect affects the electrical parameters of the transistor, in particular the absolute value of the threshold voltage of the transistor and the increase of the off-state current of the transistor. At the same time, the leakage current and transconductance of the transistor are reduced. That is, it becomes more difficult for the N-type and P-type transistors to turn on after being subjected to the BTI aging effect.
Fig. 1 illustrates a schematic structure diagram of a transmission gate in the prior art, wherein a in fig. 1 is a circuit structure diagram of the transmission gate, and b in fig. 1 is a schematic diagram of the transmission gate. Referring to fig. 1, the transmission gate includes one P-type transistor and one N-type transistor. The source electrode of the P-type transistor is electrically connected with the source electrode of the N-type transistor, the drain electrode of the P-type transistor is electrically connected with the drain electrode of the N-type transistor, the source electrode is a first signal end B, and the drain electrode is a second signal end C. The gate of the N-type transistor is controlled by a first control signal A, and the gate of the P-type transistor is controlled by a second control signal
Figure BDA0002921990150000041
The second control signal
Figure BDA0002921990150000042
Which is an inverse of the first control signal a. When the first control signal a is at a high level, the first signal terminal B is turned on with the second signal terminal C, the potential of the first signal terminal B and the potential of the second signal terminal C change simultaneously, and when the first control signal a is at a low level, the first signal terminal B is turned off with the second signal terminal C, and the potential of the first signal terminal B does not change with the potential of the second signal terminal C. Similarly, the potential of the second signal terminal C does not change with the potential of the first signal terminal B. I.e. the transmission gate realizes the switching function.
Fig. 2 illustrates a schematic structure of an inverter in the prior art, wherein a in fig. 2 is a circuit structure diagram of the inverter, and b in fig. 2 is a schematic diagram of the inverter. Referring to fig. 2, the inverter includes one P-type transistor and one N-type transistor. The source of the P-type transistor is electrically connected to a power supply terminal, the drain of the P-type transistor is electrically connected to the drain of the N-type transistor and is denoted as an Output terminal Output, and the gate of the P-type transistor is electrically connected to the gate of the N-type transistor and is denoted as an Input terminal Input. When the Input end is at a high level, the Output end is at a low level; when the Input terminal Input is at a low level, the Output terminal Output is at a high level. I.e. an inverter may be used to implement the inverting function.
The SRAM memory cell in the related art includes at least one data storage circuit, and the data storage circuit may include a first inverter and a second inverter which are cross-coupled. That is, the first inverter may include one P-type transistor P1 and one N-type transistor N1, and the second inverter may include one P-type transistor P2 and one N-type transistor N2. The gates of P-type transistor P1 and N-type transistor N1 are commonly electrically connected to the drains of P-type transistor P2 and N-type transistor N2. The drains of P-type transistor P1 and N-type transistor N1 are commonly electrically connected to the gates of P-type transistor P2 and N-type transistor N2. The P-type transistor P1 and the P-type transistor P2 are commonly used for electrical connection to a power supply terminal, and the sources of the N-type transistor N1 and the N-type transistor N2 are commonly used for electrical connection to a ground terminal. The output end of the first phase inverter is a first output end, and the output end of the second phase inverter is a second output end.
In practical application, when the first output terminal is at a low level, the second output terminal is at a high level. At this time, the P-type transistor P2 is in a negatively biased state and the N-type transistor N1 is in a positively biased state. If left in this state for a long period of time, the P-type transistor P2 and N-type transistor N1 will experience BTI aging effects. Thereafter, when the SRAM cell is restarted, since the P-type transistor P2 and the N-type transistor N1 are more difficult to turn on than the P-type transistor P1 and the N-type transistor N2, the power source charges the first output terminal, and the second output terminal discharges to the ground terminal through the N-type transistor N2. When a steady state is formed, the first output terminal has a high probability of being at a high level, and the second output terminal has a low probability of being at a low level. Such volatile SRAM memory cells may also be non-volatile due to BTI aging effects, which may reduce the data security of the SRAM memory cells.
Fig. 3 illustrates a schematic diagram of a SRAM memory cell having a master-slave structure in the prior art. Referring to fig. 3, the SRAM memory cell has a master-slave structure, and includes a master circuit, a first controlled circuit, a second controlled circuit, a reset circuit, and a read-write circuit, where the first controlled circuit, the second controlled circuit, the reset circuit, and the read-write circuit are all electrically connected to the master circuit. The main circuit comprises a data storage circuit, a first transistor, a second transistor and a third transistor.
Referring to fig. 3, a first pole of the first transistor is electrically connected to second poles of the second transistor and the third transistor, a second pole of the first transistor is electrically connected to a ground terminal, and the first transistor is controlled by the MT-CLK control signal. The first pole of the second transistor is electrically connected with the first output end of the data storage circuit, and the grid electrode of the second transistor is electrically connected with the second end of the first controlled circuit. The first electrode of the third transistor is electrically connected with the second output end of the data storage circuit, and the grid electrode of the second transistor is electrically connected with the second end of the second controlled circuit.
Referring to fig. 3, the first terminal of the first controlled circuit is electrically connected to the first output terminal of the data storage circuit, and the first terminal of the second controlled circuit is electrically connected to the second output terminal of the data storage circuit. The reset circuit is electrically connected with the second output end of the data storage circuit and is controlled by the T-RST control signal. The first controlled circuit and the second control circuit are both controlled by the ST-CLK control signal and the ST-CLK reversal control signal.
In the practical application process, the level of the first output end and the level of the second output end of the data storage circuit are continuously turned over through the SRAM storage unit with the master-slave structure. Based on the fact that the level of the first output end and the level of the second output end of the data storage circuit are continuously turned over, aging of the four transistors can be balanced, threshold mismatch caused by transistor aging is relieved or eliminated, and data safety of the SRAM storage unit can be enhanced. However, the structure of the SRAM memory cell having the master-slave structure is complicated, and more control signals are introduced, which increases the area and power consumption of the SRAM memory.
In view of the above technical problems, an embodiment of the present invention provides an SRAM memory cell. Fig. 4 is a schematic diagram illustrating a complete structure of an SRAM memory cell according to an embodiment of the present invention. Referring to fig. 4, the SRAM memory cell includes: the data latch circuit, first switching circuit, second switching circuit, third switching circuit and memory circuit. The data latch circuit has a first output terminal Q, a second output terminal QB and a conversion node. The first switch circuit is connected in series between the second output terminal QB and the conversion node. The second switching circuit is connected in series between the first output terminal Q and the first terminal of the memory circuit. The third switch circuit is connected in series between the conversion node and the first terminal of the memory circuit. The second terminal of the memory circuit is electrically connected to the ground terminal.
Referring to FIG. 4, when the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 are all controlled by the initial control signal, the first output terminal Q has the first potential VQThe second output QB has a second potential VQBThe data latch circuit charges the memory circuit. When the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 are all controlled by the flip-flop control signal, the memory circuit discharges to the data latch, and the first output end Q has the second potential VQBThe second output QB has a first potential VQ。
As can be seen from the above, under the control of the initial control signal and the inversion control signal, the states of the first switch circuit SW1, the second switch circuit SW2, the third switch circuit SW3 and the memory circuit are changed, so that the potential of the first output terminal Q and the potential of the second output terminal QB of the data latch circuit are inverted. The potential of the first output end Q and the potential of the second output end QB of the data latch circuit are inverted, so that the four transistors alternately perform the BTI aging effect. That is to say, the potential of the first output terminal Q and the potential of the second output terminal QB of the data latch circuit are inverted, so that aging of the four transistors can be equalized, threshold mismatch caused by aging of the transistors can be relieved or eliminated, and data security of the SRAM memory cell can be enhanced. Meanwhile, in the SRAM memory cell provided by the present invention, the potential of the first output terminal Q and the potential of the second output terminal QB are controlled only by the initial control signal and the inversion control signal during the inversion process. That is to say, the SRAM memory cell provided by the invention not only can balance the aging of four transistors, but also simplifies the SRAM memory cell and reduces control signals, thereby reducing the area and power consumption of an SRAM memory.
Referring to fig. 4, the SRAM memory cell further includes a read/write circuit electrically connected to the data latch circuit.
In one example, the read/write circuit may include a first N-type transistor and a second N-type transistor. A first pole of the first N-type transistor is electrically connected to the first output terminal Q, and a second pole of the first N-type transistor is electrically connected to the first bit line BL. A first pole of the second N-type transistor is electrically connected to the second output terminal QB, and a second pole of the second N-type transistor is electrically connected to the second bit line BLB. The grid electrode of the first N-type transistor and the grid electrode of the second N-type transistor are commonly electrically connected with a word line WL.
FIG. 5 is a diagram illustrating a data inversion simulation of an SRAM memory cell provided by an embodiment of the present invention. Referring to fig. 5, each falling edge of the word line WL causes the voltage level of the first output terminal Q and the voltage level of the second output terminal QB to be inverted once, which illustrates that the SRAM memory cell has a normal function of inverting data.
FIG. 6 illustrates a timing diagram for reading and writing an SRAM memory cell provided by an embodiment of the present invention. Referring to fig. 6, when the word line WL is at a high level, the first bit line BL is at a high level, and the second bit line BLB is at a low level, the write 1 operation is performed, and the potential of the first output terminal Q rises, and the write 1 operation succeeds. When the word line WL is at a high level, and the first bit line BL and the second bit line BLB are both at a high level, the read operation is performed, the second bit line BLB is discharged through the second output terminal QB, the potential is lowered, and the read 1 is successful. When the word line WL is at a high level, the second bit line BLB is at a high level, and the first bit line BL is at a low level, 0 writing is carried out, the potential of the second output end QB is increased, and 0 writing is successful; when the word line WL is at a high level and both the first bit line BL and the second bit line BLB are at a high level, the first bit line BL is discharged through the first output terminal Q, the potential drops, and the reading of 0 succeeds.
As can be seen from the above, the aging degree of each transistor in the SRAM memory cell tends to be even, and the degradation is also reduced. Therefore, even if the static noise tolerance of the SRAM is degraded, mismatch can not occur, namely, after the SRAM storage unit is electrified again, the probability that the data is 1 or 0 is equal, the aim of anti-aging imprinting is achieved, the threat of data security brought by the aging imprinting is relieved, and the data security is improved.
Referring to fig. 4, the data latch circuit includes a first inverter INV1 and a second inverter INV 2. An output end of the first inverter INV1 and an input end of the second inverter INV2 are electrically connected to the first output Q. An input end of the first inverter INV1 is electrically connected to a first end of the first switch circuit SW1 through a conversion node. A second end of the first switch circuit SW1 and the output end of the second inverter INV2 are electrically connected to the second output end QB.
Referring to fig. 4, the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 have a first state under the control of an initial control signal. The flip control signal may include a first flip control signal and a second flip control signal. The first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 have a second state under the control of the first inversion control signal, and the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 have a third state under the control of the second inversion control signal.
The initial control signals may include a first initial control signal for controlling the first switch circuit SW1 and the second switch circuit SW2, and a second initial control signal for controlling the third switch circuit SW 3. The first inversion control signal may include a third inversion control signal for controlling the first switch circuit SW1 and the second switch circuit SW2, and a fourth inversion control signal for controlling the third switch circuit SW 3. The second inversion control signal may include a fifth inversion control signal for controlling the first switch circuit SW1 and the second switch circuit SW2, and a sixth inversion control signal for controlling the third switch circuit SW 3.
Fig. 7 illustrates a partial structure diagram of a first SRAM memory cell provided in an embodiment of the present invention, and fig. 8 illustrates a partial structure diagram of a second SRAM memory cell provided in an embodiment of the present invention. Referring to fig. 7, the first state is that the first switch circuit SW1 and the second switch circuit SW2 are turned on, and the third switch circuit SW3 is turned off. The second state is that the first switch circuit SW1 and the second switch circuit SW2 are turned off, and the third switch circuit SW3 is turned on. The third state is that the first switch circuit SW1 and the second switch circuit SW2 are turned on, and the third switch circuit SW3 is turned off.
In the first state, the first initial control signal controls the first switch circuit SW1 and the second switch circuit SW2 to be turned on, the second initial control signal controls the third switch circuit SW3 to be turned off, and the first inverter INV1 and the second inverter INV2 are cross-coupled. At this time, the first output terminal Q has the first potential VQThe second output QB has a second potential VQB. Since the memory circuit is electrically connected to the first output terminal Q, the first terminal of the memory circuit also has the first potential VQ。
When the potential of the first output terminal Q and the potential of the second output terminal QB need to be inverted, the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 are in the second state and the third state.
Referring to fig. 8, in the second state, the third inversion control signal controls the first switch circuit SW1 and the second switch circuit SW2 to be turned off, the fourth inversion control signal controls the third switch circuit SW3 to be turned on, and the first inverter INV1 is decoupled from the second inverter INV 2. At this time, the first terminal of the memory circuit is electrically connected to the input terminal of the first inverter INV 1. Since the potential of the input terminal of the first inverter INV1 is the same as the potential of the second output terminal QB in the first state, when the third switch circuit SW3 is turned on, the potential of the input terminal of the first inverter INV1 is inverted to the first potential V of the first output terminal QQ. After passing through the first inverter INV1, the potential of the first output end Q is inverted to a second potential VQBAfter passing through the second inverter INV2, the potential of the second output terminal QB is inverted to the first potential VQ。
In the third state, the fifth inversion control signal controls the first switch circuit SW1 and the second switch circuit SW2 to be turned on, the sixth inversion control signal controls the third switch circuit SW3 to be turned off, and the first inverter INV1 and the second inverter INV2 are cross-coupled again. At this time, the potential of the first output terminal Q is the second potential VQBThe second output QB is at the first potential VQ. So far, the potential of the first output terminal Q and the potential of the second output terminal QB are turned over.
The first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 can be N-type transistors or transmission gates. The transistor may be an N-type transistor.
Fig. 9 illustrates a schematic diagram three of a partial structure of an SRAM memory cell according to an embodiment of the present invention. Referring to fig. 9, in one example, the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 may all be N-type transistors.
In practical applications, when the first initial control signal is at a high level and the second initial control signal is at a low level, the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 are in a first state. When the third inversion control signal is at a low level and the fourth inversion control signal is at a high level, the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 are in a second state. When the fifth inversion control signal is at a high level and the sixth inversion control signal is at a low level, the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 are in a third state.
Fig. 10 illustrates a partial structural diagram of a SRAM memory cell provided in the embodiment of the present invention. Referring to fig. 10, in one example, the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 may all be transmission gates.
In practical applications, when the first initial control signal is at a high level and the second initial control signal is at a low level, the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 are in a first state. When the third inversion control signal is at a low level and the fourth inversion control signal is at a high level, the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 are in a second state. When the fifth inversion control signal is at a high level and the sixth inversion control signal is at a low level, the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 are in a third state.
It should be understood that the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 may include both N-type transistors and transmission gates. The detailed description of the principles is omitted here.
In this way, the fifth inversion control signal and the first initialization control signal may be the same signal. The sixth inversion control signal and the second control signal may be the same signal. The third inversion control signal may be an opposite control signal from the first initial control signal. The fourth inversion control signal may be an opposite control signal from the second initial control signal. The first initial control signal may be an opposite control signal to the second initial control signal. For example: the first initial control signal may be S1_ B, and the second initial control signal may be S1.
The memory circuit may be a MOS capacitor or a parallel plate capacitor CAP 1. In order to ensure that the voltages at the input terminals of the first inverter INV1 are opposite before or after the third switch circuit SW3 is turned on, the capacitance value of the MOS capacitor or the parallel plate capacitor CAP1 is greater than or equal to 100 PF.
Fig. 11 illustrates a partial structural diagram five of an SRAM memory cell provided in the embodiment of the present invention, and fig. 12 is a partial structural diagram six of an SRAM memory cell provided in the embodiment of the present invention. Referring to fig. 9 to 12, in the same SRAM memory cell, the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 may be N-type transistors, and the memory circuit may be a parallel plate capacitor CAP 1. Alternatively, in the same SRAM memory cell, the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 may be N-type transistors, and the memory circuit may be MOS capacitors. Alternatively, in the same SRAM memory cell, the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 may be transmission gates, and the memory circuit may be MOS capacitors. Alternatively, in the same SRAM memory cell, the first switch circuit SW1, the second switch circuit SW2 and the third switch circuit SW3 may be transmission gates, and the memory circuit may be a parallel plate capacitor CAP 1.
The embodiment of the invention also provides an SRAM memory, which comprises the SRAM memory cell.
Compared with the prior art, the beneficial effects of the SRAM memory provided by the embodiment of the present invention are the same as the beneficial effects of the SRAM memory cell described in the first aspect, and are not described herein again.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and shall cover the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. An SRAM memory cell, comprising: the data latch circuit, the first switch circuit, the second switch circuit, the third switch circuit and the storage circuit; the data latch circuit is provided with a first output end, a second output end and a conversion node; the first switch circuit is connected in series between the second output end and the conversion node, the second switch circuit is connected in series between the first output end and the first end of the storage circuit, the third switch circuit is connected in series between the conversion node and the first end of the storage circuit, and the second end of the storage circuit is used for being electrically connected with a ground end;
when the first switch circuit, the second switch circuit and the third switch circuit are all controlled by an initial control signal, the first output end has a first potential, the second output end has a second potential, and the data latch circuit charges the storage circuit;
when the first switch circuit, the second switch circuit and the third switch circuit are all controlled by the turnover control signal, the storage circuit discharges to the data latch, the first output end has the second potential, and the second output end has the first potential.
2. The SRAM memory cell of claim 1, wherein the first, second, and third switch circuits have a first state under control of the initial control signal.
3. The SRAM memory cell of claim 2, wherein the first state is the first switch circuit and the second switch circuit being on, and the third switch circuit being off.
4. The SRAM memory cell of claim 2, wherein the toggle control signal comprises a first toggle control signal and a second toggle control signal;
the first, second, and third switch circuits have a second state under control of the first inversion control signal, and the first, second, and third switch circuits have a third state under control of the second inversion control signal.
5. The SRAM memory cell of claim 4, wherein the second state is the first switch circuit and the second switch circuit being off, and the third switch circuit being on;
the third state is that the first switch circuit and the second switch circuit are on, and the third switch circuit is off.
6. The SRAM memory cell according to any one of claims 1 to 5, wherein the first switch circuit, the second switch circuit and the third switch circuit are N-type transistors or transmission gates.
7. The SRAM memory cell of any one of claims 1 to 5, wherein the memory circuit is a MOS capacitor or a parallel plate capacitor.
8. The SRAM memory cell of claim 7, wherein the MOS capacitance or the parallel plate capacitance has a capacitance value greater than or equal to 100 PF.
9. The SRAM memory cell of claim 4, wherein the data latch circuit comprises a first inverter and a second inverter;
the output end of the first phase inverter and the input end of the second phase inverter are electrically connected to the first output end, the input end of the first phase inverter is electrically connected to the first end of the first switch circuit through the conversion node, and the second end of the first switch circuit and the output end of the second phase inverter are electrically connected to the second output end;
in the first state and the third state, the first inverter and the second inverter are cross-coupled connected.
10. An SRAM memory comprising the SRAM memory cell of any one of claims 1 to 9.
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