CN112802506A - Control method and device of memory device - Google Patents
Control method and device of memory device Download PDFInfo
- Publication number
- CN112802506A CN112802506A CN202110087413.8A CN202110087413A CN112802506A CN 112802506 A CN112802506 A CN 112802506A CN 202110087413 A CN202110087413 A CN 202110087413A CN 112802506 A CN112802506 A CN 112802506A
- Authority
- CN
- China
- Prior art keywords
- stack layer
- voltage
- sub
- preset voltage
- channel structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a control method and a device of a memory device, the memory device comprises a bit line, a source electrode, a stack layer positioned between the bit line and the source electrode, and a memory channel structure penetrating through the stack layer along a direction vertical to the bit line, the stack layer comprises a first sub-stack layer, a first dummy stack layer and a second sub-stack layer which are sequentially stacked, and the control method comprises the following steps: in a pre-charging stage, applying a first preset voltage to the bit line to enable the storage channel structure close to the bit line to generate holes, and applying a second preset voltage to the source electrode, wherein the first preset voltage and the second preset voltage are positive voltages; the storage channel structure corresponding to the first dummy stack layer is opened, and the storage channel structure corresponding to the second sub-stack layer is conducted with the source electrode, so that residual electrons in the channel can be extracted from the bottom of the channel quickly, the number of residual electrons in the channel is reduced as much as possible, and the program disturb phenomenon is improved.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductors, in particular to a control method and a control device of a storage device.
[ background of the invention ]
In recent years, Flash memories (expressed in english as Flash memories) have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In order to further increase the Bit Density of the flash memory (english can be expressed as Bit Density) and reduce the Bit Cost of the memory (english can be expressed as Bit Cost), a three-dimensional (3D, 3Dimensions) memory technology is proposed. Currently, 3D memory technology is rapidly developing.
In 3D memories, each memory cell includes a nonvolatile charge trapping transistor that is programmed or erased by biasing a voltage of appropriate polarity, magnitude, and duration between its control gate and its substrate, a program (also called write) disturb being an unintended and detrimental change in the net charge remaining in the memory cell. During programming or erasing of a selected memory cell, charges are inevitably generated in the channels of unselected memory cells that share the same gate or drain or source voltage as the selected memory cell, and the charges cause program disturb of the unselected memory cells. At present, a larger forward bias voltage can be provided to the source terminal to attract electrons in the channel to move outwards so as to reduce the charge density in the channel and further reduce the program disturb phenomenon.
[ summary of the invention ]
The invention aims to provide a control method and a control device of a memory device, which can better improve channel potential and improve the phenomenon of program disturbance.
In order to solve the above-described problems, the present invention provides a control method of a memory device including a bit line, a source electrode, a stack layer between the bit line and the source electrode, the stack layer including a first sub-stack layer, a first dummy stack layer, and a second sub-stack layer sequentially stacked, and a memory channel structure penetrating the stack layer in a direction perpendicular to the bit line, the control method including:
in a pre-charging stage, applying a first preset voltage to the bit line so that holes are generated in the storage channel structure close to the bit line, and applying a second preset voltage to the source electrode, wherein the first preset voltage and the second preset voltage are positive voltages;
and opening the storage channel structure corresponding to the first dummy stack layer, and conducting the storage channel structure corresponding to the second sub-stack layer with the source.
Wherein the causing the memory channel structure corresponding to the first dummy stack layer to open comprises:
and applying a third preset voltage to the control gate in the first dummy stack layer, wherein the third preset voltage is greater than or equal to the turn-on voltage of the storage channel structure corresponding to the first dummy stack layer.
The second sub-stack layer comprises a lower select gate, and the conducting the storage channel structure corresponding to the second sub-stack layer to the source comprises:
and applying a fourth preset voltage to the lower selection gate, wherein the fourth preset voltage is greater than or equal to the conduction voltage of the storage channel structure corresponding to the lower selection gate.
Wherein the second sub-stack layer further includes a second dummy stack layer, and the connecting the storage channel structure corresponding to the second sub-stack layer to the source further includes:
and applying a fifth preset voltage to the control gate in the second dummy stack layer, wherein the fifth preset voltage is greater than or equal to the turn-on voltage of the storage channel structure corresponding to the second dummy stack layer.
Wherein the first sub-stack layer comprises an upper selection gate, a selected control gate and an unselected control gate which are arranged in a stacked mode, and the control method further comprises the following steps: in the precharge phase, the upper select gates, the selected control gates, and the unselected control gates are grounded.
Wherein the control method further comprises:
entering a programming stage after the pre-charging is finished;
in the programming phase, a programming voltage is applied to the selected control gate, and voltages greater than the turn-on voltage of the respective storage channel structures are applied to the unselected control gates, the control gates in the first dummy stack layer and the control gates in the second sub-stack layer, respectively, while the bit line and the source are grounded.
Wherein, the control method also comprises the following steps:
in the pre-charging stage, a sixth preset voltage is applied to the control gate in the second sub-stack layer, wherein the sixth preset voltage is a positive voltage and is smaller than the second preset voltage.
In the pre-charging stage, the second preset voltage is applied for a time earlier than the fourth preset voltage and the sixth preset voltage, and the release time is later than the fourth preset voltage and the sixth preset voltage.
Wherein the second sub-stack layer comprises a plurality of control gates, and the sixth preset voltage applied to the control gates in the second sub-stack layer is increased in an incremental manner in a direction extending through the stack layers and toward the source.
The present invention also provides a control apparatus of a memory device including a bit line, a source electrode, a stack layer between the bit line and the source electrode, and a storage channel structure penetrating the stack layer in a direction perpendicular to the bit line, the stack layer including a first sub-stack layer, a first dummy stack layer, and a second sub-stack layer sequentially stacked, the control apparatus including:
a first voltage applying module, configured to apply a first preset voltage to the bit line in a precharge stage, so that holes are generated in the memory channel structure close to the bit line, and apply a second preset voltage to the source, where the first preset voltage and the second preset voltage are positive voltages;
and the second voltage application module is used for opening the storage channel structure corresponding to the first dummy stack layer and conducting the storage channel structure corresponding to the second sub-stack layer with the source.
Wherein the second voltage applying module is configured to:
and applying a third preset voltage to the control gate in the first dummy stack layer, wherein the third preset voltage is greater than or equal to the turn-on voltage of the storage channel structure corresponding to the first dummy stack layer.
Wherein the second sub-stack layer comprises a lower select gate, and the second voltage applying module is configured to:
and applying a fourth preset voltage to the lower selection gate, wherein the fourth preset voltage is greater than or equal to the conduction voltage of the storage channel structure corresponding to the lower selection gate.
Wherein the second sub-stack layer further comprises a second dummy stack layer, and the second voltage applying module is further configured to:
and applying a fifth preset voltage to the control gate in the second dummy stack layer, wherein the fifth preset voltage is greater than or equal to the turn-on voltage of the storage channel structure corresponding to the second dummy stack layer.
Wherein the control device further comprises a third voltage applying module for:
in the pre-charging stage, a sixth preset voltage is applied to the control gate in the second sub-stack layer, wherein the sixth preset voltage is a positive voltage and is smaller than the second preset voltage.
The invention has the beneficial effects that: according to the control method of the memory device, the first preset voltage is applied to the bit line in the pre-charging stage, so that holes are generated in the storage channel structure close to the bit line, the second preset voltage is applied to the source electrode, meanwhile, the storage channel structure corresponding to the first dummy stack layer is opened, and the storage channel structure corresponding to the second sub stack layer is conducted with the source electrode, so that residual electrons in the channel can be rapidly extracted from the bottom of the channel, the number of residual electrons in the channel is reduced as much as possible, and the program interference phenomenon is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart illustrating a method for controlling a memory device according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a front view of a memory device in simplified form according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a partial cross-sectional structure of a memory device provided in an embodiment of the present application;
FIG. 4 is a timing diagram illustrating voltages applied to portions of a memory device according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a control device of a memory according to an embodiment of the present application.
[ detailed description ] embodiments
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
It should be readily understood that directional terms used herein, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], etc., are merely directions that refer to the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals. The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
It should be readily understood that references to the meaning of "on … …", "above … …" and "above … …" in the present invention are to be interpreted in the broadest manner such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween.
As used herein, the term "layer" refers to a portion of material having an area of thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above and/or below it, which may include multiple layers.
Referring to fig. 1 to fig. 3, fig. 1 is a schematic flowchart illustrating a control method of a memory device according to an embodiment of the present application, fig. 2 is a schematic front view structure diagram of the memory device according to the embodiment of the present application, which is shown in a simplified form, and fig. 3 is a schematic partial cross-sectional structure diagram of the memory device according to the embodiment of the present application. The memory device 100 includes a Bit Line (BL) 101, a source 102, a stack layer 103 between the bit line 101 and the source 102, and a memory channel structure 104 penetrating the stack layer 103 along a direction perpendicular to the bit line 101, wherein the stack layer 103 includes a first sub-stack layer 1031, a first dummy stack layer 1032, and a second sub-stack layer 1033 sequentially stacked. In fig. 1, the control method includes the steps of:
step S101, in a pre-charge stage, applying a first preset voltage to the bit line 101 to generate holes in the memory channel structure 104 close to the bit line 101, and applying a second preset voltage to the source 102, where the first preset voltage and the second preset voltage are positive voltages; the memory channel structure 104 corresponding to the first dummy stack layer 1032 is opened, and the memory channel structure 104 corresponding to the second sub-stack layer 1033 is conducted to the source 102.
The first sub-stack layer 1031 may include a Top Selection Gate (TSG), a selected control gate sel.w, and a control gate CG (CG), where the selected control gate sel.w is a control gate CG to which a program signal needs to be input. The first dummy stack layer 1032 includes at least one control gate CG, and the second sub-stack layer 1033 includes at least one control gate CG and a Bottom Selection Gate (BSG) stacked and arranged as transistors, and dielectric layers M are disposed between adjacent gates, such as between the upper selection gate TSG and the control gate CG, between the control gate CG and the control gate CG, and between the control gate CG and the lower selection gate TSG, wherein the upper selection gate TSG is connected to a String Selection Line (SSL), the lower selection gate BSG is connected to a Ground Selection Line (GSL), and the control gate CG is connected to a Word Line (WL). The material for forming the upper select gate TSG, the control gate CG, and the lower select gate BSG includes a conductive material, such as a metal material, e.g., tungsten, and the material for forming the dielectric layer M includes an insulating material, such as any one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. The memory device 100 further comprises a substrate (not shown) on which the stack 103 is located. The substrate may be a semiconductor substrate, and may be, for example, Silicon, Germanium, or Silicon-On-Insulator (SOI), Germanium-On-Insulator (GOI), or the like.
In practical operation, referring to fig. 4 and 3, during the pre-charge phase, the first preset voltage Vb applied to the bit line BL may be a high voltage, so that band-to-band tunneling occurs near the upper select gate TSG and the bit line BL, holes are generated in the corresponding storage channel structure 104, and the holes are transported downward through the storage channel structure 104 to recombine with residual electrons in the upper channel 104A, so as to reduce the electron concentration in the upper channel 104A, and at this time, the upper select gate TSG, the selected control gate sel.w and the control gate CG in the first sub-stack 1031 may be grounded at the same time, that is, their applied voltages are 0V. Meanwhile, a second preset voltage Vs is applied to the source 102, and the storage channel structure 104 corresponding to the first dummy stack layer 1032 is opened, so that the upper channel 104A and the lower channel 104B are conducted, and the lower channel 104B is conducted with the source 102, so that under the action of the potential of the source 102, residual electrons in the upper channel 104A and the lower channel 104B can be extracted from the channels, and the purpose of reducing the channel electron concentration is achieved.
It should be explained that when the programming sequence is from top to bottom, the upper channel 104A may include a programmed portion and an unprogrammed portion, and normally, in the pre-charging stage, the transistors corresponding to the programmed portion are in the off state, and the corresponding residual electrons are hard to move under the potential of the source 102, and at this time, by applying a high voltage to the bit line 101, the residual electrons in the upper channel 104A can be eliminated by means of holes.
In some embodiments, the storage channel structure 104 may be formed by a plurality of punching processes, and correspondingly, the stack layer 103 may also be formed by a plurality of stacking processes, and a dummy stack layer is disposed between the control gates CG formed by two adjacent stacking processes. For example, with continued reference to fig. 4 and fig. 2, the stack layer 103 may include an upper select gate TSG, a gate W1-Wm, and a lower select gate BSG, and when the programming order is from top to bottom, a dummy stack layer IDPDMY (i.e. a first dummy stack layer 1032) located closest to and below the selected control gate sel.w may be determined with the selected control gate sel.w as a boundary, and a portion of the stack layer 103 above the dummy stack layer IDPDMY may be regarded as a first sub-stack layer 1031, such as an upper select gate TSG and a control gate W1-Wn, and a portion of the stack layer 103 below the dummy stack layer IDPDMY may be regarded as a second sub-stack layer 1033, such as a lower select gate BSG and a control gate Wn +1-Wm, and dummy stack layers DMY may be disposed between the upper select gate TSG and an adjacent control gate W1, and between the lower select gate BSG and an adjacent control gate Wm.
Specifically, the step of "opening the memory channel structure 104 corresponding to the first dummy stack layer 1032" may include:
a third predetermined voltage Vm is applied to the control gate CG in the first dummy stack layer 1032, where the third predetermined voltage Vm is greater than or equal to the turn-on voltage of the memory channel structure 104 corresponding to the first dummy stack layer 1032.
Wherein the on-voltage may be about-2 v, and the third preset voltage Vm may be a small positive voltage. When the third preset voltage Vm reaches the turn-on voltage, the memory channel structure 104 (hereinafter, referred to as an upper channel 104A) corresponding to the first sub-stack layer 1031 and the memory channel structure 104 (hereinafter, referred to as a lower channel 104B) corresponding to the second sub-stack layer 1033 are turned on, so that the residual electrons in the upper channel 104A can move into the lower channel 104B.
In addition to the need to conduct the upper channel 104A and the lower channel 104B, the need to conduct the lower channel 104B with the source 102 may also include the following steps:
a fourth predetermined voltage Vh is applied to the lower select gate BSG, and the fourth predetermined voltage Vh is greater than or equal to the turn-on voltage of the memory channel structure 104 corresponding to the lower select gate BSG.
The turn-on voltage may be about 2.5v, and the fourth preset voltage Vh may be a voltage not less than 2.5v, such as 5v to 6 v. When the upper and lower channels are conducted with each other and the lower channel 104B is conducted with the source 102, the residual electrons in the storage channel structure 104 can be pumped away under the action of the potential of the source 102, thereby reducing the electron concentration in the storage channel structure 104 and increasing the channel potential.
It is easily understood that, in addition to conducting the dummy stack layer IDPDMY between the first sub-stack layer 1031 and the second sub-stack layer 1033, for the first sub-stack layer 1031 and the second sub-stack layer 1033 formed by the multi-stack process, if the residual electrons are to be moved in the upper channel 104A and the lower channel 104B, all the dummy stack layers corresponding to the upper channel 104A and all the dummy stack layers corresponding to the lower channel 104B are also conducted.
For example, for the lower channel 104B, the second sub-stack layer 1033 may further include a second dummy stack layer (not shown), in which case, the step of "turning on the memory channel structure 104 corresponding to the second sub-stack layer 1033 to the source 102" further includes:
and applying a fifth preset voltage to the control gate in the second dummy stack layer, wherein the fifth preset voltage is greater than or equal to the turn-on voltage of the memory channel structure corresponding to the second dummy stack layer.
Wherein the fifth preset voltage may be equal to the third preset voltage Vm.
Further, to increase the speed at which the residual electrons in the lower channel 104B move to an external circuit, a positive voltage may be applied to the control gate CG in the second sub-stack layer 1033 to enable the electrons around the control gate CG to be rapidly accumulated, that is, the control method of the memory device 100 may further include:
a sixth preset voltage Vj is applied to the control gate CG in the second sub-stack layer 1033, and the sixth preset voltage Vj is a positive voltage and is smaller than the second preset voltage Vs.
The sixth preset voltage Vj may be about 3v, which is generally smaller than the voltage (i.e., Vs) applied to the lower select gate BSG, so that the residual electrons in the lower channel 104B can move toward the lower select gate BSG with a higher potential after being rapidly accumulated near the corresponding control gate CG, and the moving speed of the electrons can be greatly increased compared to the scheme of directly attracting the residual electrons through the potentials of the lower select gate BSG and the source 102. It should be noted that the same voltage value may be applied to all the control gates CG in the second sub-stack layer 1033, for example, a voltage of 3v is applied in fig. 4, and different voltage values may also be applied, for example, the sixth preset voltage Vj applied to the control gates CG in the second sub-stack layer 1033 increases in an increasing manner in a direction (i.e., the direction L in fig. 3) extending through the stack layer 103 and toward the source 102, so as to enable the residual electrons to rapidly gather with a downward moving trend, thereby further increasing the moving speed of the electrons.
It should be noted that, in the pre-charging phase, the application time of the second preset voltage Vs should be earlier than the third preset voltage Vm, the sixth preset voltage Vj, and the fourth preset voltage Vh, and the release time should be later than the third preset voltage Vm, the sixth preset voltage Vj, and the fourth preset voltage Vh, and the application times of the first preset voltage Vb, the third preset voltage Vm, the sixth preset voltage Vj, and the fourth preset voltage Vh may not be limited.
In addition, the control method may further include the steps of:
entering a programming stage after the pre-charging is finished;
in the programming phase, a programming voltage is applied to a selected control gate sel.w, and a voltage greater than a turn-on voltage of the respective memory channel structure is applied to the control gate CG in the first sub-stack layer 1031, the control gate CG in the first dummy stack layer 1032 and the control gate CG in the second sub-stack layer 1033, respectively, while the bit line 101 and the source 102 are grounded.
The programming voltage should be much larger than the turn-on voltage of the corresponding memory channel structure and larger than the voltage applied to the rest of the control gates in the memory cell 103, for example, the programming voltage shown in fig. 4 is 22V, and the voltages applied to the control gate CG in the second sub-stack layer 1033 and the control gate CG in the first sub-stack layer 1031 are 7.2V.
On the basis of the control method of the memory device 100, the embodiment of the present application further provides a control apparatus of the memory device 100, where the memory device 100 includes a bit line 101, a source 102, a stack layer 103 located between the bit line 101 and the source 102, and a storage channel structure 104 penetrating through the stack layer 103 in a direction perpendicular to the bit line 101, and the stack layer 103 includes a first sub-stack layer 1031, a first dummy stack layer 1032, and a second sub-stack layer 1033, which are sequentially stacked.
The first sub-stack layer 1031 may include an upper select gate TSG, a select control gate sel.w, and a control gate CG, which are stacked, where the select control gate sel.w is the control gate CG to which a program signal needs to be input. The first dummy stack layer 1032 includes at least one control gate CG, and the second sub-stack layer 1033 includes at least one control gate CG and a lower select gate BSG stacked together, which may be regarded as a transistor, and a dielectric layer M is disposed between adjacent gates, such as between the upper select gate TSG and the control gate CG, between the control gate CG and the control gate CG, and between the control gate CG and the lower select gate TSG.
Referring to fig. 5, and fig. 1-4, the control device 200 may include a first voltage applying module 201 and a second voltage applying module 202, wherein:
the first voltage applying module 201 is configured to apply a first preset voltage Vb to the bit line 101 during a pre-charging phase to generate holes in the memory channel structure 104 close to the bit line 101, and apply a second preset voltage Vs to the source 102, where the first preset voltage Vb and the second preset voltage Vs are positive voltages.
A second voltage applying module 202, configured to open the memory channel structure 104 corresponding to the first dummy stack layer 1032 and conduct the memory channel structure 104 corresponding to the second sub-stack layer 1033 to the source 102.
Further, the second voltage applying module 202 is configured to:
a third predetermined voltage Vm is applied to the control gate CG in the first dummy stack layer 1032, where the third predetermined voltage Vm is greater than or equal to the turn-on voltage of the memory channel structure 104 corresponding to the first dummy stack layer 1032.
Wherein the on-voltage may be about-2 v, and the third preset voltage Vm may be a small positive voltage. When the third preset voltage Vm reaches the turn-on voltage, the memory channel structure 104 (hereinafter, referred to as an upper channel 104A) corresponding to the first sub-stack layer 1031 and the memory channel structure 104 (hereinafter, referred to as a lower channel 104B) corresponding to the second sub-stack layer 1033 are turned on, so that the residual electrons in the upper channel 104A can move into the lower channel 104B.
Further, the second voltage applying module 202 is configured to:
a fourth predetermined voltage Vh is applied to the lower select gate, where the fourth predetermined voltage Vh is greater than or equal to the turn-on voltage of the memory channel structure 104 corresponding to the lower select gate.
The turn-on voltage may be about 2.5v, and the fourth preset voltage Vh may be a voltage not less than 2.5v, such as 5v to 6 v. When the upper and lower channels are conducted with each other and the lower channel 104B is conducted with the source 102, the residual electrons in the storage channel structure 104 can be pumped away under the action of the potential of the source 102, thereby reducing the electron concentration in the storage channel structure 104 and increasing the channel potential.
For example, for the lower channel 104B, the second sub-stack layer 1033 may further include a second dummy stack layer, and the second voltage applying module 202 is further configured to:
and applying a fifth preset voltage to the second dummy stack layer, wherein the fifth preset voltage is greater than or equal to the turn-on voltage of the memory channel structure corresponding to the second dummy stack layer.
Wherein the fifth preset voltage may be equal to the third preset voltage Vm.
Furthermore, the control device 200 may further include a third voltage applying module 203 for:
a sixth preset voltage Vj is applied to the gate of the second sub-stack layer 1033, and the sixth preset voltage Vj is a positive voltage and is smaller than the second preset voltage Vs.
The sixth preset voltage Vj may be about 3v, which is generally smaller than the voltage (i.e., Vs) applied to the lower select gate BSG, so that the residual electrons in the lower channel 104B can move toward the lower select gate BSG with a higher potential after being rapidly accumulated near the corresponding control gate CG, and the moving speed of the electrons can be greatly increased compared to the scheme of directly attracting the residual electrons through the potentials of the lower select gate BSG and the source 102. It should be noted that the same voltage value may be applied to all the control gates CG in the second sub-stack layer 1033, for example, a voltage of 3v is applied in fig. 4, and different voltage values may also be applied, for example, the sixth preset voltage Vj applied to the control gates CG in the second sub-stack layer 1033 increases in an increasing manner in a direction (i.e., the direction L in fig. 3) extending through the stack layer 103 and toward the source 102, so as to enable the residual electrons to rapidly gather with a downward moving trend, thereby further increasing the moving speed of the electrons.
Furthermore, the control device may further comprise a programming module for:
entering a programming stage after the pre-charging is finished;
in the programming phase, a programming voltage is applied to a selected control gate sel.w, and a voltage greater than a turn-on voltage of the respective memory channel structure is applied to the control gate CG in the first sub-stack layer 1031, the control gate CG in the first dummy stack layer 1032 and the control gate CG in the second sub-stack layer 1033, respectively, while the bit line 101 and the source 102 are grounded.
Different from the prior art, in the control method and the control apparatus 200 of the memory provided in the embodiment of the present application, in the pre-charge stage, the first preset voltage Vb is applied to the bit line 101, so that the storage channel structure 104 close to the bit line 101 generates holes, and the second preset voltage Vs is applied to the source 102, and meanwhile, the storage channel structure 104 corresponding to the first dummy stack layer 1032 is opened, and the storage channel structure 104 corresponding to the second sub-stack layer 1033 is conducted with the source 102, so that the residual electrons in the channel can be extracted from the bottom of the channel faster, the number of residual electrons in the channel is reduced as much as possible, and the program disturb phenomenon is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A control method of a memory device, the memory device including a bit line, a source electrode, a stack layer between the bit line and the source electrode, and a memory channel structure penetrating the stack layer in a direction perpendicular to the bit line, the stack layer including a first sub-stack layer, a first dummy stack layer, and a second sub-stack layer sequentially stacked, the control method comprising:
in a pre-charging stage, applying a first preset voltage to the bit line so that holes are generated in the storage channel structure close to the bit line, and applying a second preset voltage to the source electrode, wherein the first preset voltage and the second preset voltage are positive voltages;
and opening the storage channel structure corresponding to the first dummy stack layer, and conducting the storage channel structure corresponding to the second sub-stack layer with the source.
2. The method of claim 1, wherein said causing the memory channel structure corresponding to the first dummy stack layer to open comprises:
and applying a third preset voltage to the control gate in the first dummy stack layer, wherein the third preset voltage is greater than or equal to the turn-on voltage of the storage channel structure corresponding to the first dummy stack layer.
3. The method of claim 1, wherein the second sub-stack layer comprises a lower select gate, and the conducting the corresponding storage channel structure of the second sub-stack layer to the source comprises:
and applying a fourth preset voltage to the lower selection gate, wherein the fourth preset voltage is greater than or equal to the conduction voltage of the storage channel structure corresponding to the lower selection gate.
4. The method of claim 3, wherein the second sub-stack layer further comprises a second dummy stack layer, and the connecting the corresponding storage channel structure of the second sub-stack layer to the source further comprises:
and applying a fifth preset voltage to the control gate in the second dummy stack layer, wherein the fifth preset voltage is greater than or equal to the turn-on voltage of the storage channel structure corresponding to the second dummy stack layer.
5. The method of controlling a memory device of claim 1, wherein the first sub-stack layer comprises an upper select gate, a selected control gate, and a control gate arranged in a stack, the method further comprising: in the pre-charge phase, grounding the upper select gate, the selected control gate, and the control gate in the first sub-stack layer.
6. The method of controlling a memory device according to claim 5, further comprising:
entering a programming stage after the pre-charging is finished;
in the programming phase, a programming voltage is applied to the selected control gate, and voltages greater than the turn-on voltage of the respective storage channel structures are applied to the control gate in the first sub-stack layer, the control gate in the first dummy stack layer and the control gate in the second sub-stack layer, respectively, while the bit line and the source are grounded.
7. The method of controlling a storage device according to any one of claims 1 to 6, further comprising:
in the pre-charging stage, a sixth preset voltage is applied to the control gate in the second sub-stack layer, wherein the sixth preset voltage is a positive voltage and is smaller than the second preset voltage.
8. The method of claim 7, wherein the second predetermined voltage is applied earlier than the fourth predetermined voltage and the sixth predetermined voltage and is released later than the fourth predetermined voltage and the sixth predetermined voltage during the precharge phase.
9. The method of claim 8, wherein the second sub-stack layer comprises a plurality of control gates, and wherein the sixth predetermined voltage applied to the control gates in the second sub-stack layer increases incrementally in a direction extending through the stack layer and toward the source.
10. A control apparatus of a memory device, the memory device including a bit line, a source electrode, a stack layer between the bit line and the source electrode, and a memory channel structure penetrating the stack layer in a direction perpendicular to the bit line, the stack layer including a first sub-stack layer, a first dummy stack layer, and a second sub-stack layer sequentially stacked, the control apparatus comprising:
a first voltage applying module, configured to apply a first preset voltage to the bit line in a precharge stage, so that holes are generated in the memory channel structure close to the bit line, and apply a second preset voltage to the source, where the first preset voltage and the second preset voltage are positive voltages;
and the second voltage application module is used for opening the storage channel structure corresponding to the first dummy stack layer and conducting the storage channel structure corresponding to the second sub-stack layer with the source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110087413.8A CN112802506B (en) | 2021-01-22 | 2021-01-22 | Control method and device of memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110087413.8A CN112802506B (en) | 2021-01-22 | 2021-01-22 | Control method and device of memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112802506A true CN112802506A (en) | 2021-05-14 |
| CN112802506B CN112802506B (en) | 2022-10-11 |
Family
ID=75811192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110087413.8A Active CN112802506B (en) | 2021-01-22 | 2021-01-22 | Control method and device of memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112802506B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107507646A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of control method and device for reducing programming interference |
| US20200143890A1 (en) * | 2018-11-07 | 2020-05-07 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of programming in the same |
| US10665306B1 (en) * | 2019-04-08 | 2020-05-26 | Sandisk Technologies Llc | Memory device with discharge voltage pulse to reduce injection type of program disturb |
| US20200402584A1 (en) * | 2018-11-07 | 2020-12-24 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of programming in the same |
-
2021
- 2021-01-22 CN CN202110087413.8A patent/CN112802506B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107507646A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of control method and device for reducing programming interference |
| US20200143890A1 (en) * | 2018-11-07 | 2020-05-07 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of programming in the same |
| US20200402584A1 (en) * | 2018-11-07 | 2020-12-24 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of programming in the same |
| US10665306B1 (en) * | 2019-04-08 | 2020-05-26 | Sandisk Technologies Llc | Memory device with discharge voltage pulse to reduce injection type of program disturb |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112802506B (en) | 2022-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3653186B2 (en) | Nonvolatile memory device programming method | |
| US10714184B2 (en) | Memory device with improved program performance and method of operating the same | |
| KR20190018548A (en) | A memory device comprising a plurality of select gates and a different bias condition | |
| US10600488B2 (en) | Non-volatile memory device including decoupling circuit | |
| EP1860687A2 (en) | SONOS memory device | |
| US20150294726A1 (en) | Nand-type flash memory device and method of programming the same | |
| US10803952B2 (en) | Vertical memory device having improved electrical characteristics and method of operating the same | |
| JP5059437B2 (en) | Nonvolatile semiconductor memory device | |
| EP3881322B1 (en) | Non-volatile memory device and control method | |
| US11152074B2 (en) | Memory device with improved program performance and method of operating the same | |
| CN103390427B (en) | Semiconductor storage and the driving method of this semiconductor storage | |
| US8913427B2 (en) | Semiconductor memory device and method of operating the same | |
| JP5640848B2 (en) | Nonvolatile semiconductor memory | |
| KR101739059B1 (en) | Nonvolatile memory device | |
| US10680013B2 (en) | Three-dimensional memory devices having plurality of vertical channel structures | |
| KR100731076B1 (en) | Vertical spilit gate structure of flash memory device, and manufacturing method thereof | |
| CN112771617A (en) | Three-dimensional memory device programming with reduced disturb | |
| US20130080718A1 (en) | Semiconductor memory device and method of operating the same | |
| CN112802506B (en) | Control method and device of memory device | |
| US8755228B2 (en) | Writing method of nonvolatile semiconductor memory device | |
| KR101691094B1 (en) | Nonvolatile memory device and memory system thereof | |
| CN112802505B (en) | Programming operation method and device of memory | |
| JP7297977B1 (en) | flash memory | |
| US20240055055A1 (en) | Memory device including page buffer circuit | |
| EP4365902A1 (en) | Memory device including page buffer circuit and ssd including the memory device, and method of using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |