CN112787727B

CN112787727B - Dynamic error quantizer tuning system and method

Info

Publication number: CN112787727B
Application number: CN202011221781.9A
Authority: CN
Inventors: C·拉泽尔
Original assignee: Maxim Integrated Products Inc
Current assignee: Maxim Integrated Products Inc
Priority date: 2019-11-05
Filing date: 2020-11-05
Publication date: 2023-12-19
Anticipated expiration: 2040-11-05
Also published as: CN112787727A

Abstract

Dynamic error quantizer tuning systems and methods prevent misconvergence to local minima by: a dynamic quantizer circuit is used that controls reference voltages of three or more comparators, which are independently adjusted to modify the transfer function of the dynamic quantizer circuit. The weighted sum of the outputs of the comparators is subtracted from the input to form an error signal in the control loop. The ratio of the reference voltages is selected during control loop convergence to reduce or eliminate the local minimum and is set after control loop convergence is completed to a value that minimizes the mean square error signal with respect to the discrete modulation state of the input.

Description

Dynamic error quantizer tuning system and method

The inventors:

charles Razzell

Cross-reference to related patent applications

The present application relates to U.S. provisional patent application serial No. 62/931,127, filed on 5 th 11 2019, entitled "hals-lazaer and entitled" Dynamic Error Quantizer Tuning Systems and Methods (dynamic error quantizer tuning system and method "), and claims priority according to 35u.s.c. ≡119 (e). Each reference mentioned in this patent document is incorporated herein by reference in its entirety for all purposes.

Background

The present disclosure relates generally to signal processing in high-speed communication circuits. More particularly, the present invention relates to dynamic control of the transfer function of an error quantization function used in a decision directed phase or polarization rotation tracking control loop.

The demand for bandwidth by telecommunication networks has grown over the past few decades. The large available bandwidth, whether transferring data between chips or between Wide Area Network (WAN) fiber links, is a major factor in the increasing popularity of high-speed optical communication systems. For example, there is a high demand in data centers and campus networks for optical transceivers designed for short-range (hundreds of meters) interconnection through optical fibers.

The coherent optical link conveys data through different channels corresponding to different phases and/or polarizations of the input signals of the optical fibers. Although the transmitted data is typically aligned with respect to a common clock, delays may be introduced in the channels due to the inherent characteristics of the transmitter, receiver and optical fibers, such that the polarization and phase of each channel arrive at the receiver with an unknown phase rotation in the phase polarization dimensions, which are inverted to recover the transmitted data. In some designs, misconvergence in the complex LMS control loop may further cause the loop to settle at a location other than the desired global optimum.

It is therefore desirable to provide improved coherent signal processing systems and methods that overcome the shortcomings of the prior methods.

Drawings

Reference will now be made to embodiments of the disclosure, examples of which may be illustrated in the accompanying drawings. The drawings are intended to be illustrative, and not limiting. While the appended disclosure is generally described in the context of these embodiments, it should be understood that it is not intended to limit the scope of the disclosure to these particular embodiments. The items in the figure may not be to scale.

Fig. 1 ("fig. 1") is a block diagram of a conventional dual polarization quadrature amplitude modulation (DP-QAM) receiver architecture based on analog signal processing.

Fig. 2 shows a common PAM4 quantizer transfer function.

Fig. 3 illustrates standard deviation of errors of PAM4 data versus scaling factor applied in accordance with an embodiment of the present disclosure.

Fig. 4 illustrates standard deviation of a modified error quantization function according to an embodiment of the present disclosure, according to an embodiment of the present disclosure.

Fig. 5 illustrates an exemplary polarization and carrier phase correction circuit including an error quantizer according to an embodiment of the present disclosure.

Fig. 6 is an exemplary circuit implementation of a soft quantizer according to various embodiments of the present disclosure.

Fig. 7 is an exemplary circuit implementation of an error estimator according to various embodiments of the present disclosure.

Fig. 8 is an exemplary error estimation transfer function resulting from the use of PAM4 error estimation circuitry in accordance with various embodiments of the present disclosure.

Fig. 9 is a flowchart of an illustrative process for dynamic error quantizer tuning in accordance with an embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, specific details are set forth in order to provide an understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these details. Furthermore, those skilled in the art will recognize that the embodiments of the present disclosure described below may be implemented in a variety of ways, such as in a process, an apparatus, a system/device, or a method, on a tangible computer readable medium.

The components or modules shown in the figures illustrate exemplary embodiments of the present disclosure and are intended to avoid obscuring the disclosure. It should also be understood that throughout this discussion, components may be described as separate functional units that may include sub-units, but those skilled in the art will recognize that various components or portions thereof may be separated into separate components or may be integrated together, including in a single system or component. It should be noted that the functions or operations discussed herein may be implemented as components. The components may be implemented in software, hardware, or a combination thereof.

Furthermore, connections between components or systems within the figures are not intended to be limited to direct connections. Rather, the data between these components may be modified, reformatted, or otherwise changed by intermediate components. Moreover, additional connections or fewer connections may be used. It should also be noted that the terms "coupled", "connected" or "communicatively coupled" (communicatively coupled) should be understood to include direct connection, indirect connection through one or more intermediate devices, and wireless connection.

In this specification, reference to "one embodiment," "a preferred embodiment (preferred embodiment)", "an embodiment (an embodiment)", or "embodiments (embodiments)" means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the disclosure and may be in more than one embodiment. Moreover, appearances of the phrases in various places throughout this specification are not necessarily all referring to the same embodiment or embodiments.

Certain terminology is used in the various places throughout this specification for the purpose of description and should not be taken as limiting. The terms "include", "comprising", "including", and "including" are to be construed as open-ended terms and any list below is exemplary and not intended to be limited to the listed items. All documents cited herein are incorporated by reference in their entirety.

It is noted that while the examples described herein are given in the context of NRZ and PAM4 implementations, those skilled in the art will recognize that the teachings of the present disclosure are not so limited and are equally applicable to M-ary PAM systems and methods (where M.gtoreq.4, i.e., 6-PAM, 8-PAM, etc.) and other contexts.

In this document, the terms quantizer and soft quantizer may be used interchangeably. Soft quantizer refers to a nonlinear transfer function that can be embedded in a circuit and that can map an analog input signal to a value that is closer to the closest modulation symbol than the original input value. In this context, the use of the term "soft" is intended to indicate that the output signal is not necessarily limited to four discrete levels of modulation, i.e. it is closer to, but not necessarily exactly matched to, the ideal case (e.g. PAM4 value). Further, the term "error estimator" refers to a circuit configured to subtract a soft quantized value (e.g., PAM 4) from an original input signal to generate an error estimate between an ideal signal value and an actual received signal value.

Fig. 1 is a block diagram of a conventional DP-QAM receiver architecture based on analog signal processing. Receiver 100 is a homodyne receiver driven by a co-channel laser (not shown) acting as a local oscillator. The arrangement of polarizing beam splitters and 90 ° hybrids 106 is designed to provide balanced orthogonal light outputs for each of the two orthogonal polarizations (labeled X and Y in a conventional manner) incident on eight photodiodes 108 arranged in balanced pairs. This arrangement produces four bipolar photocurrents 110 that are amplified by respective transimpedance amplifiers (TIAs) 112 corresponding to in-phase (I) and quadrature (Q) phases of X-polarization and Y-polarization, respectively. Thus, the four branches (i.e., XI, XQ, YI, YQ) of the receiver 100 can be used for further signal processing in the analog domain.

Existing electronic polarization control loops can be used to separate and phase align dual polarization coherent signals. LMS adaptation is used in coherent optical signal processors to track random phase rotations and other impairments. A continuous version of the classical RLMS update equation is used to perform Least Mean Square (LMS) adaptation on eight coefficients held as charge on a capacitor, for example in an analog integrator.

Eight coefficients represent a 2 x 2 complex matrix for separating and phase correcting the input analog signal:

considering a dual polarization coherent optical receiver (which has four independent branches XI, XQ, YI and YQ representing the I and Q components of two arbitrary orthogonal polarizations X and Y), and ignoring losses and dispersion in the optical channel, the X and Y signals observed in these receiver branches can be represented in complex notation as

Wherein, phi is phi ₁ Theta and phi ₀ Is four real parameters, ψ represents the absolute phase, φ ₀ Representing the relative phase shift between the X-polarized signal and the Y-polarized signal before the plane polarization rotation θ, and φ ₁ Representing the relative phase shift thereafter. By multiplying all these sub-components, a single 2 x 2 complex matrix is obtained which correlates the received signal with the transmitted signal as follows:

the matrix Γ is a unitary matrix due to factors used to create it. The matrix Γ is thus invertible and the estimated value of the original transmitted waveform may be obtained as:

thus, there is a new unmixed matrixIt can be substituted into the above matrix equation to derive:

this represents two linear equations, each having two complex coefficients, i.e.,

X _out ＝C _1X X _in +C _1Y Y _in

and

Y _out ＝C _2X C _in +C _2Y Y _in 。

Although these two equations appear to be independent, they are derived from only four independent real parameters, and therefore, the coefficients of the top and bottom rows of the matrix are not independent of each other. However, for the purpose of iterating toward the solution, these coefficients may be considered independent, as long as they are not correlated in such a way that the top and bottom rows are related to each other by a proportionality constant (i.e., X _out ＝αY _out Where α is a proportionality constant) converges.

Solving one of these equations (and assuming that similar techniques can be applied to the other similar equation) provides X _out ＝C _1X X _in +C _1Y Y _in In which only the signal X is observed _in And Y _in Are known. Although the estimated symbolsIs unknown, but it is known that X should be extracted from the finite letters of the modulation constellation used (e.g. in 16-QAM modulation) _out These samples can be considered as 4-PAM signaling for each of these orthogonal channels. Thus, for C _1X And C _1Y Can estimate the error as the nearest valid constellation point to the output signal X _out Represented by Q (X) _out ) And X is _out The difference between them. Is provided with->The quantizer Q may be defined as two PAM4 modulated quantizers that operate independently in at least approximately the I-dimension and the Q-dimension.

Based on the known complex LMS update equation, the coefficient C may be added by using the following update equation _1X And C _1Y To iterate toward a minimum error condition:

X _out ＝X _in ×C _1X +Y _in C ₁₁

the complex expression described above is extended using the following formula:

output calculations that produce real and imaginary parts of the X-polarized output:

the coefficient update equations for the real and imaginary parts of the upper row of the coefficient matrix are then:

similarly, the Y-polarized output can be written:

Y _out ＝X _in ×C _2X +Y _in C _2Y ，

the expansion is as follows:

and the corresponding update equation is:

the expansion is as follows:

the result is eight real-valued update equations that can be used to solve for the four complex coefficients of the unmixed matrix. In embodiments of the present disclosure, these update equations may be implemented as continuous time integrators in the analog domain.

The above analysis regards the error signal as the difference between the (PAM 4) quantized version of the signal and the signal itself, i.eFig. 2 shows a common PAM4 quantizer transfer function. The choice of quantization function may have a significant impact on performance, particularly in the convergence state, where, ideally, Q (X _out )-X _out =0. This result is unlikely if the choice of Q (-) is not a faithful representation of the ideal PAM4 quantizer. As a result, false error estimates may lead to false tap adjustments and thus to multiplicative noise in the output data stream. Note that the analog signal analyzed is bandwidth limited and occupies only a small fraction of the Unit Interval (UI) at the desired PAM4 level (i.e., at the eye center region). Thus, even if the quantizer is mathematically perfect, the error signal may produce some unwanted fluctuations due to signal transitions.

The parameterized slicing function can be modeled as:

where x is the input voltage, Δ is the (un-scaled) decision threshold of the PAM4 modulated outer symbol, s is the scaling factor such that the outer symbol takes a value of 3/s, and γ is the gradient of the output and input voltages.

When the input signal includes a random PAM4 symbol, the standard deviation of the error may be defined as std (err (x))=std (Q (x) -x).

Fig. 3 illustrates the standard deviation of the error of PAM4 data using delta = 2 versus the scaling factor applied according to an embodiment of the present disclosure. As depicted, while the standard deviation of the error is almost zero at an applied scaling factor of 1, there are two other local error minima 302, 304 at lower scaling factors. This may result in the LMS loop being locked at one of the local minima 302, 304 and similar undesirable locations. Thus, to address this problem, various embodiments contemplate modifying the error profile of the quantizer in which the decision boundary Δ moves closer to zero than the ideal match to the PAM4 constellation, as shown in fig. 4.

Fig. 4 illustrates standard deviation of a modified error quantization function according to an embodiment of the present disclosure, derived using delta = 1.5, according to an embodiment of the present disclosure. Curve 402 shows that the likelihood of convergence point errors can be reduced or eliminated by changing only one parameter. This may come at the cost of increasing the steady state error at the expected signal amplitude 1. Curve 404 shows that increasing the slope reduces steady state error, but at the cost of a more pronounced local minimum at about 0.45.

In an embodiment, the convergence starts with an error quantizer, which may be defined by Q (x, 1.5,3,2), and after the convergence has been achieved, the quantizer, which is defined by Q (x, 2,3, 2), switches to tracking mode. This may be achieved by using a DAC controlling the reference voltage, which in an embodiment defines zero crossings of the two differential amplifiers, to effectively switch the transfer function from the converging mode to the normal operating mode. The method for dynamically changing quantizer behavior during initial convergence is referred to herein as dynamic error quantizer tuning, and may be performed by using a timer or in embodiments based on a value of a lock bit that indicates that convergence has been achieved. As discussed in more detail below with reference to fig. 6 and 7, in an embodiment, dynamic error quantizer tuning may be achieved by adjusting thresholds, which may be represented by DC bias values in the comparator circuit. Adjusting the DC offset value in this manner allows a smooth tradeoff to be achieved between low residual error at the desired operating point and the presence of an undesirable local error minimum.

Fig. 5 illustrates an exemplary polarization and carrier phase correction circuit including an error quantizer according to an embodiment of the present disclosure. The circuit 500 includes an error quantizer (e.g., 510), which may include a comparator circuit, a switch (e.g., 512), an adaptive circuit (e.g., 520), a complex multiplier (e.g., 540), and a supervisory control circuit 550. At the top level, the circuit 500 may be considered as representing four complex multipliers (e.g., 540) of the jones matrix. The multiplier multiplies the time-varying 2 x 2 complex matrix by four input signals (e.g., 502), each of which can be considered as two complex signals, wherein the complex tap weights can be continuously adapted by using the LMS update equation to correct for polarization rotation and phase rotation in the optical channel.

In an embodiment, the adaptation of complex coefficients (e.g., 530) may be implemented by one analog LMS loop (e.g., 522) per coefficient (e.g., 530). In an embodiment, to correct for polarization and phase variations in the fiber, four real error quantizers 510 monitor the error, which may be time varying signals, and compare the error to an ideal constellation. Based on the comparison, the error quantizer 510 drives a complex adaptive circuit (e.g., 520) that determines four complex coefficients (e.g., 530) of the jones matrix. The supervisory control circuit 550 may be implemented by a unitary excitation circuit 550 that, in an embodiment, switches the error quantizer (e.g., 510) to data modulation in the form of a non-return-to-zero (NRZ) transmission such that once the total amplitude of the jones matrix coefficients falls below a predetermined threshold, the data slices generate binary symbol decisions, e.g., 1 and-1 (or 0 and 1 in the case of unipolar notation).

In an embodiment, one quantizer (e.g., 510) may operate as a conventional NRZ quantizer with zero DC bias, and the other two quantizers may be biased to equal and opposite thresholds, e.g., defined by one of two possible constants. In an embodiment, switch 512 may use LMS enable signal 514 to select an operational mode that is active at any given time. In an embodiment, when the two variable slice thresholds are set to zero, the overall transfer function may be restored to a simple NRZ quantizer. NRZ mode can be used to ensure convergence during start-up, while PAM4 mode provides a more accurate error slice for steady state operation.

The polarization and carrier phase correction circuit 500 illustrated in fig. 5 is not limited to the details of the structure shown here or described in the accompanying text. For example, as will be appreciated by those skilled in the art, the switch 512 may be replaced by a suitable ramp generator (not shown) that, in an embodiment, may be used to apply a controlled DC voltage to smooth transitions of the error quantizer (e.g., 510) between NRZ mode and PAM4 mode in a controlled manner to avoid or reduce undesirable transient effects caused by switching events. Such a ramp generator may generate a ramp from an initial voltage to a target voltage (e.g., a voltage that is asymmetric about a zero value).

Fig. 6 is an exemplary circuit implementation of a soft quantizer according to various embodiments of the present disclosure. In an embodiment, quantizer 600 may implement a nonlinear transfer function that maps an analog signal to a value that is closer to the closest modulation symbol than the original input value. Note that the signal generated by quantizer 600 need not exactly match the discrete modulation level of the ideal modulation value (e.g., PAM4 value).

As shown in fig. 6, the quantizer 600 may be implemented as a PAM4 quantizer circuit that utilizes the current-mode summation of three differential pair amplifiers. In an embodiment, a voltage bias (e.g., 609) may be applied to the differential base input terminal (e.g., 609) to offset zero crossings of two of the amplifiers, for example, relative to the nominal zero crossings of the remaining one of the amplifiers. As depicted in fig. 6, two of the amplifiers may be DC biased to equal thresholds with opposite polarities. In an embodiment, the threshold may be dynamically adjusted to tune the quantizer 600 to transition between controllable states, e.g., from NRZ mode to PAM4 mode or from PAM4 mode to NRZ mode.

Fig. 7 is an exemplary circuit implementation of an error estimator according to various embodiments of the present disclosure. In an embodiment, the error estimator 700 is an error detection circuit configured to generate a signal proportional to the difference between the output signal and the PAM4 quantized version of the output signal. The value of the obtained error estimate may be somewhere between the desired signal value and the actual received signal value. In an embodiment, the error estimator 700 may be implemented as a PAM4 error estimator that in operation subtracts a quantized value (e.g., PAM4 soft quantized value obtained from fig. 6) from the original input signal to generate an error estimate that may be used to drive a complex LMS control loop such as that shown in fig. 5.

Fig. 9 is a flowchart of an illustrative process for dynamic error quantizer tuning in accordance with an embodiment of the present disclosure. In an embodiment, process 900 begins at step 902, where an error detection circuit begins driving the control loop in a first mode of operation (e.g., a convergence mode or NRZ mode), such as during an adaptation phase of the control loop. The error detection circuit may calculate the error as the distance between the output signal and the quantized signal, e.g. the closest predetermined symbol. In an embodiment, the error detection circuit drives an adaptive circuit that controls the complex coefficients representing the tap weights.

At step 904, in response to determining that the control loop meets the convergence criterion, the error detection circuit transitions to driving the control loop in a second mode of operation (e.g., tracking mode or PAM4 mode) in order to reduce errors that can cause tap weight noise.

Finally, at step 906, the error detection circuit may transition to the first mode of operation in response to detecting that the total amplitude of the jones matrix coefficients falls below a threshold. It should be noted that certain steps may alternatively be performed; the steps may not be limited to the specific order set forth herein; certain steps may be performed in a different order; and certain steps may be performed simultaneously. It is further noted that the embodiments disclosed herein are applicable to analog and/or digital implementations, as digital tuning systems and methods may equally utilize the teachings of the present disclosure to control quantization and estimation of errors.

Aspects of the disclosure may be encoded on one or more non-transitory computer-readable media with instructions for one or more processors or processing units to cause steps to be performed. It should be noted that the one or more non-transitory computer readable media should include volatile memory and non-volatile memory. It should be noted that alternative embodiments are possible, including hardware embodiments or software/hardware embodiments. The hardware implemented functions may be implemented using Application Specific Integrated Circuits (ASICs), programmable arrays, digital signal processing circuitry, or the like. Accordingly, the terms in any claims are intended to cover both software and hardware implementations. The term "one or more computer-readable media" as used herein includes software and/or hardware or a combination thereof having a program of instructions embodied thereon. In view of these alternatives to the embodiments, it will be appreciated that the figures and accompanying description provide functional information that would be required by one skilled in the art to write program code (i.e., software) and/or fabricate circuits (i.e., hardware) to perform the required processing.

It should be noted that embodiments of the present disclosure may further relate to computer products with a non-transitory tangible computer-readable medium that have computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present disclosure, or they may be of the kind well known or available to those having skill in the relevant arts. Examples of tangible computer readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROM and holographic devices; a magneto-optical medium; and hardware devices that are specially configured for storing or for storing and executing program code, such as ASICs, programmable Logic Devices (PLDs), flash memory devices, and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Embodiments of the present disclosure may be implemented in whole or in part as machine-executable instructions that may be in program modules that are executed by a processing device. Examples of program modules include libraries, programs, routines, objects, components, and data structures. In a distributed computing environment, program modules may be located in a local, remote, or both environment.

Those skilled in the art will recognize that no computing system or programming language is critical to the practice of the present disclosure. Those skilled in the art will also recognize that the various elements described above may be physically and/or functionally divided into sub-modules or combined together.

It will be appreciated by those skilled in the art that the foregoing examples and embodiments are exemplary and not limiting to the scope of the present disclosure. It is intended that all permutations, enhancements, equivalents, combinations and modifications thereof that are apparent to those skilled in the art upon a reading of the present specification and a study of the drawings are included within the true spirit and scope of the present disclosure. It should also be noted that the elements of any claim may be arranged in a different manner, including having a variety of dependencies, configurations, and combinations.

Claims

1. A dynamic quantizer circuit for preventing a decision feedback control loop from failing to converge to a local minimum, the dynamic quantizer circuit comprising:

inputting;

a control circuit that controls one or more reference voltages of a set of reference voltages; and

comparators coupled to the input, each comparator having an output and being associated with at least one of the one or more reference voltages, reference voltages of at least two of the comparators being independently adjustable to adjust a transfer function of the dynamic quantizer circuit,

wherein a weighted sum of the outputs of the comparators is subtracted from the input to form an error signal in the control loop,

during convergence of the control loop, selecting a ratio of at least two voltages of the set of reference voltages to reduce or eliminate a local minimum, an

After the control loop convergence is completed, the ratio of at least two voltages in the set of reference voltages is set to a value that minimizes the mean square error signal relative to the discrete modulation state of the input.

2. The dynamic quantizer circuit of claim 1, wherein the dynamic quantizer circuit drives the control loop in a first mode of operation in response to detecting that the magnitude of the jones matrix coefficients is at or below a threshold value, and drives the control loop in a second mode of operation in response to determining that the control loop meets a convergence criterion.

3. The dynamic quantizer circuit according to claim 2, wherein the first mode of operation is one of a convergence mode or an NRZ mode and the second mode of operation is one of a tracking mode or a PAM4 mode that belongs to a normal mode of operation of the control loop.

4. The dynamic quantizer circuit of claim 2, further comprising: at least one of a timer or a lock bit indicating that the convergence criterion has been met.

5. The dynamic quantizer circuit of claim 1, further comprising: the sum of the current modes of one or more differential pair amplifiers in a set of differential pair amplifiers.

6. The dynamic quantizer circuit of claim 1, further comprising: an adaptive circuit for controlling complex coefficients.

7. The dynamic quantizer circuit of claim 1, further comprising: a ramp generator for generating a ramp from an initial voltage to a target voltage, the ramp being asymmetric about a zero value.

8. A method of dynamic error quantizer tuning for preventing control loop loss from converging to a local minimum, the method comprising:

adjusting the reference voltages of at least two comparators using a control circuit that controls one or more reference voltages of a set of reference voltages to adjust a transfer function of the dynamic quantizer circuit, each comparator coupled to an input, having an output, and being associated with at least one of the one or more reference voltages;

subtracting a weighted sum of the outputs of the comparators from the input to obtain an error signal in the control loop;

during convergence of the control loop, selecting a ratio of at least two voltages of the set of reference voltages to reduce or eliminate a local minimum; and

9. The method of claim 8, further comprising: an error detection circuit that determines an error as a distance between the signal and the quantized signal is caused to drive the control loop in a first mode, and responsive to determining that the control loop meets a convergence criterion, the error detection circuit is caused to transition to driving the control loop in a second mode to reduce the error, the error capable of causing tap weight noise.

10. The method of claim 9, wherein the error detection circuit drives an adaptive circuit that controls the complex coefficients representing tap weights.