CN112786784B - Phase change memory device and manufacturing method thereof - Google Patents
Phase change memory device and manufacturing method thereof Download PDFInfo
- Publication number
- CN112786784B CN112786784B CN202110063237.4A CN202110063237A CN112786784B CN 112786784 B CN112786784 B CN 112786784B CN 202110063237 A CN202110063237 A CN 202110063237A CN 112786784 B CN112786784 B CN 112786784B
- Authority
- CN
- China
- Prior art keywords
- layer
- film layer
- variable resistance
- electrode
- dopant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of the switching material, e.g. post-treatment, doping
- H10N70/043—Modification of the switching material, e.g. post-treatment, doping by implantation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
Abstract
The invention provides a phase change memory device and a manufacturing method thereof. The variable resistance layer included in the phase change memory device is doped with the seed crystal dopant, so that the crystallization speed can be accelerated, and the seed crystal dopant has gradient change in the variable resistance layer, so that the resistance change of the variable resistance layer can be stabilized, and the phenomenon of deviation of resistance of a resistance state representing a stored value is reduced.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a phase change memory device, a method of manufacturing the same, and a semiconductor device having the same.
Background
In the phase change memory device, although the phase change memory cell of a multi-level cell (MLC) or a triple-level cell (TLC) (or a multi-level cell) having a plurality of resistance states has a high storage density, since the resistance value of the resistance state or the state resistance value range representing the stored value in the variable resistance layer in the conventional phase change memory device is prone to be deviated, the accuracy of reading data is reduced, and the stability of the phase change memory cell of the multi-level or triple-level cell (or the multi-level cell) having a plurality of resistance states is further reduced. Therefore, it is desirable to provide a phase change memory device and a method for fabricating the same to solve the problems of the prior art.
Disclosure of Invention
The present invention is directed to a phase change memory device and a method for fabricating the same, which solves the problems of the prior art.
In order to achieve the above object, a first aspect of the present invention provides a method for manufacturing a phase change memory device, including the steps of:
providing a substrate;
stacking a first electrode wire film layer, a storage film layer and a second electrode wire film layer on the substrate from bottom to top along the longitudinal direction; and the number of the first and second groups,
etching the second electrode line film layer, the storage film layer and the first electrode line film layer to form a plurality of independent phase change storage units,
the step of forming the storage film layer at least comprises forming a variable resistance film layer which is composed of a phase change main body and a seed crystal adulterant, wherein the phase change storage unit comprises a first electrode wire, a storage layer and a second electrode wire, the first electrode wire, the storage layer and the second electrode wire are respectively formed by etching the first electrode wire film layer, the storage film layer and the second electrode wire film layer, the storage layer contains the variable resistance layer, and the variable resistance layer comprises the phase change main body and the seed crystal adulterant.
Further, the step of forming the variable resistance film layer includes depositing the phase change host material, and doping the seed dopant into the phase change host material to form the variable resistance film layer, and making the formed variable resistance layer include high-concentration seed dopants located at upper and lower sides of the variable resistance layer, and a low-concentration seed dopant located in the middle of the variable resistance layer.
Further, the step of forming a variable resistance film layer includes depositing the phase change host to form a variable resistance body film layer, and implanting the seed dopant into the variable resistance body film layer to form the variable resistance film layer, and the step of implanting the seed dopant into the variable resistance body film layer includes: the variable resistance layer is formed by doping a high-concentration seed dopant at the lower side of the variable resistance body film layer by using a first energy ion beam, doping a low-concentration seed dopant at the middle of the variable resistance body film layer by using a second energy ion beam, and doping a high-concentration seed dopant at the upper side of the variable resistance body film layer by using a third energy ion beam, so that the variable resistance layer comprises the high-concentration seed dopant doped at the upper side and the lower side of the variable resistance layer and the low-concentration seed dopant doped at the middle of the variable resistance layer, wherein the first energy is greater than the second energy, and the second energy is greater than the third energy.
Further, the high concentration seed dopant has a doping weight percentage concentration ranging from 2% to 5%, and the low concentration seed dopant has a doping weight percentage concentration ranging from 0% to 1%.
Further, the seed dopant includes one of a carbon element, a silicon element, an indium element, a tin element, a nitrogen element, a molybdenum element, and a tungsten nitride compound.
Further, the step of forming a storage film layer further includes:
and stacking the first electrode wire film layer and the variable resistance film layer from bottom to top along the longitudinal direction to form a lower electrode film layer, a selection device film layer and a middle electrode film layer, and forming an upper electrode film layer above the variable resistance film layer.
Further, the step of forming the storage film layer further includes:
forming a first interfacial barrier film layer between the variable resistance film layer and the intermediate electrode film layer; and
forming a second interfacial barrier film layer between the variable resistance film layer and the upper electrode film layer.
Further, the step of etching the second electrode line film layer, the storage film layer, and the first electrode line film layer includes:
etching the second electrode wire film layer, the upper electrode film layer and the variable resistance film layer for the first time to form the second electrode wire, the upper electrode and the variable resistance layer with first widths respectively;
forming an insulating protection layer on the etched longitudinal side surfaces of the second electrode wire, the upper electrode and the variable resistance layer; and
performing second etching on the middle electrode film layer, the selection device film layer, the lower electrode film layer and the first electrode wire film layer to respectively form a middle electrode, a selection device, a lower electrode and a first electrode wire with a second width;
wherein the first width is less than the second width.
Further, the insulation protection layer sequentially comprises a nitride insulation layer and an oxide insulation layer along the longitudinal side surface outwards.
Further, the doping concentration of the seed dopant in the variable resistance layer is changed in a gradient manner along the longitudinal direction.
Further, the step of forming the first electrode line film layer includes:
forming a first metal film layer and a first metal adhesive film layer along the longitudinal direction, the first metal adhesive film layer being located between the first metal film layer and the storage film layer; and
the step of forming the second electrode line film layer comprises the following steps: and forming a second metal film layer and a second metal bonding film layer along the longitudinal direction, wherein the second metal bonding film layer is positioned between the second metal film layer and the storage film layer.
Further, the material of the first metal adhesive film layer and the second metal adhesive film layer comprises tungsten nitride.
Further, the material of the phase change host includes germanium antimony tellurium (Ge)xSbyTez)。
A second aspect of the present invention provides a phase change memory device including a plurality of phase change memory cells, the phase change memory cells including:
a first electrode line;
the memory layer is arranged on the first electrode line along the longitudinal direction and at least comprises a variable resistance layer, and the variable resistance layer comprises a phase change host substance and a seed crystal dopant; and
and second electrode lines disposed on the memory layer in the longitudinal direction.
Further, the seed dopant includes one of carbon, silicon, indium, tin, nitrogen, molybdenum, and tungsten-nitrogen compounds.
Further, the variable resistance layer includes: the variable resistance layer is doped with high-concentration seed crystal dopants at the upper side and the lower side of the variable resistance layer, and the low-concentration seed crystal dopants in the middle of the variable resistance layer.
Further, the high concentration seed dopant has a doping weight percentage concentration ranging from 2% to 5%, and the low concentration seed dopant has a doping weight percentage concentration ranging from 0% to 1%.
Further, the memory layer further includes a lower electrode, a selection device, an intermediate electrode, and an upper electrode above the variable resistance layer, which are sequentially stacked between the first electrode line and the variable resistance layer from bottom to top along the longitudinal direction.
Further, the memory layer further includes a first interface barrier layer disposed between the variable resistance layer and the intermediate electrode, and a second interface barrier layer disposed between the variable resistance layer and the upper electrode.
Further, first electrode line is followed vertically include first metal level and first metal bonding layer, the second electrode line is followed vertically include second metal level and second metal bonding layer, first metal bonding layer is located first metal level with between the storage layer, second metal bonding layer is located the second metal level with between the storage layer.
Further, the doping concentration of the seed dopant in the variable resistance layer is changed in a gradient manner along the longitudinal direction.
Further, the material of the phase change host includes germanium antimony tellurium (Ge)xSbyTez)。
Further, the phase change memory device further includes:
and the insulation protection layer is arranged on the second electrode wire, the upper electrode and the longitudinal side surface of the variable resistance layer, and sequentially comprises a nitride insulation layer and an oxide insulation layer along the longitudinal side surface outwards.
A third aspect of the present invention provides a semiconductor device including the phase-change memory device described in the above-described aspects.
The variable resistance layer is doped with the seed crystal dopant to accelerate crystallization speed, and further when the variable resistance layer has the seed crystal dopant with gradient change, the resistance change of the variable resistance layer can be stabilized, and the phenomenon that the resistance representing a stored value is deviated in a resistance state or a resistance range in a state is reduced; the variable resistance layer doped with the seed dopant (including the gradient seed dopant) can also form crystals with smaller size deviation and slow down the fluctuation amount of the crystals, so that the variable resistance layer is beneficial to forming a plurality of resistance states to store data; the variable resistance layer doped with the seed dopant (including the graded seed dopant) has a higher resistivity, increasing the efficiency of supplying energy to the variable resistance layer during a reset process, reducing the loss of energy used.
Drawings
FIG. 1 is a schematic diagram of a phase change memory cell according to an embodiment of the invention.
Fig. 2 is an exemplary graph of the resistance value of the variable resistance layer according to the embodiment of the present invention as a function of a current applied to an electrode for supplying power to the variable resistance layer.
Fig. 3 is a schematic diagram illustrating a concentration of a seed dopant doped in a variable resistance layer along a longitudinal gradient according to an embodiment of the invention.
FIG. 4 is a flowchart illustrating a method of fabricating a phase change memory device according to an embodiment of the present invention.
Fig. 5A-5B are schematic cross-sectional views of a phase-change memory device manufactured according to the method of manufacturing the phase-change memory device shown in fig. 4.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the particular embodiments described herein are illustrative only, and that the word "embodiment" as used in the description of the invention is intended to serve as an example, instance, or illustration, and is not intended to limit the invention.
Referring to FIG. 1, a phase change memory cell 10 of a phase change memory device according to an embodiment of the invention is shown. The phase change memory device includes a plurality of phase change memory cells 10, each phase change memory cell 10 including first electrode lines 11, a memory layer 12, and second electrode lines 13. The memory layer 12 is longitudinally disposed on the first electrode line 11, and further includes a lower electrode 121, a selection device 122, an intermediate electrode 123, a variable resistance layer 125, and an upper electrode 127, which are sequentially stacked from bottom to top along the longitudinal direction; the second electrode lines 13 are disposed on the memory layer 12 in the longitudinal direction. The memory layer 12 may further include a first interface barrier layer 124 disposed between the middle electrode 123 and the variable resistance layer 125, and a second interface barrier layer 126 disposed between the variable resistance layer 125 and the upper electrode 127, but the present invention is not limited thereto, and the embodiment of the present invention is described below with reference to the memory layer 12 including the first interface barrier layer 124 and the second interface barrier layer 126.
In some embodiments, the first electrode lines 11 are word lines (word lines), and the second electrode lines 13 are bit lines (bit lines); or the first electrode lines 11 are bit lines and the second electrode lines 13 are word lines, which is not specifically limited in the present invention. It should be noted that the first electrode lines 11 extend along a first direction, the second electrode lines 13 extend along a second direction, and the first direction and the second direction may be parallel to the same plane and perpendicular to each other, but this should not be construed as limiting the present invention.
In this embodiment, the first electrode lines 11 sequentially include a first metal layer 111 and a first metal adhesive layer 112 along the longitudinal direction, and the second electrode lines 13 sequentially include a second metal layer 131 and a second metal adhesive layer 132 along the longitudinal direction. The material of the first metal layer 111 and the second metal layer 131 may be tungsten (W), titanium (Ti), tantalum (Ta), or the like. Since the first metal layer 111 has low adhesion to the lower electrode 121 and the second metal layer 131 has low adhesion to the upper electrode 127, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or the like may be used as the materials of the first metal adhesive layer 112 and the second metal adhesive layer 132, so that the first metal adhesive layer 112 adheres the first metal layer 111 to the lower electrode 121 and the second metal adhesive layer 132 adheres the second metal layer 131 to the upper electrode 127. And a thinner (thicker) layer may be formed before depositing the first metal adhesion layer 112 and the second metal adhesion layer 132 to further reduce contact resistanceOn the order of several hundred angstroms) to achieve reduced contact resistance. The first metal adhesive layer 112 and the second metal adhesive layer 132 may be formed by a physical vapor deposition (e.g., sputtering) process, and the like, in which inert gas is introduced into a vacuum chamber, high voltage direct current is applied to a metal target (target) and a substrate, electrons generated by glow discharge collide with each other and excite the inert gas to generate plasma, the plasma with high kinetic energy bombards the surface of the metal target, so that metal particles are sputter-deposited on the surface of the substrate in a vapor phase to form a metal thin film, and nitrogen (N) is introduced after bombarding the metal target for several seconds2) To form a metal adhesion layer of nitride.
In the present embodiment, the lower electrode 121, the middle electrode 123, and the upper electrode 127 may be carbon electrodes (carbon electrodes), or electrodes formed of metal, metal nitride, or metal oxide. The lower electrode 121 and the middle electrode 123 are used to conduct the current input from the first electrode line 11 to the variable resistance layer 125, and then conduct the current from the variable resistance layer 125 to the upper electrode 127 and the second electrode line 13, so as to perform the storage function of the storage layer 12.
In the present embodiment, the selection device 122 is referred to as a switching device or an access device, and is a current control layer for controlling current conduction. The selection device 122 may be an Ovonic Threshold Switch (OTS), and when a voltage lower than a threshold voltage is applied to the selection device 122, the selection device 122 may be in a high resistance state in which almost no current flows, and when a voltage higher than the threshold voltage is applied to the selection device 122, the selection device 122 may be in a low resistance state in which current may flow. The selection device 122 may also be a diode (diode) or a Magnetic Tunnel Junction (MTJ) device with a function of controlling current conduction.
Further, the material of the ovonic threshold switch (i.e., the select device 122) may be a chalcogenide including one or more of the elements of group VI or any one or more of the elements of group III, group IV, and group V of the periodic table of elements. The material of the select device 122 may include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), indium (In), or combinations thereof, for example, including about 14% silicon (Si), about 39% tellurium (Te), about 37% arsenic (As), about 9% germanium (Ge), about 1% indium (In); the material of the select device 122 may include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), or combinations thereof, for example, including about 5% silicon (Si), about 34% tellurium (Te), about 28% arsenic (As), about 11% germanium (Ge), about 21% selenium (Se), about 1% selenium (Se); the material of the select device 122 may include tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), antimony (Sb), or a combination thereof, for example, including about 21% tellurium (Te), about 10% arsenic (As), about 15% germanium (Ge), about 2% sulfur (S), about 50% selenium (Se), about 2% antimony (Sb).
In this embodiment, if the selection device 122 is in a high resistance state, the lower electrode 121 and the middle electrode 123 cannot conduct the current input from the first electrode line 11 to the variable resistance layer 125; if the selection device 122 is in a low-resistance state, the lower electrode 121 and the middle electrode 123 may conduct the current input by the first electrode line 11 to the variable resistance layer 125.
In this embodiment, the memory layer 12 is configured to perform a memory function according to a resistance change of the variable resistance layer 125. Specifically, the resistance of the variable resistance layer 125 can be changed by applying a current to the electrodes to provide the electrodes with energy (e.g., thermal energy) related to time, that is, the crystalline phase of the variable resistance layer 125 can be reversibly switched between a stable crystalline phase and a metastable amorphous phase according to the energy and the acting time applied thereto. Semi-metallic characteristics when the crystal phase of the variable resistance layer 125 is a crystalline phase, which is a low resistance state; when the crystalline phase of the variable resistance layer 125 is an amorphous phase, it exhibits semiconductor characteristics, which is a high resistance state. In the present embodiment, the electrode may be the upper electrode 127, but is not limited thereto.
Further, the transition from the metastable amorphous phase to the stable crystalline phase requires the use of an energy temperature above the crystallization temperature and below the melting temperature with sufficient time to allow the crystalline phase of the variable resistance layer 125 to be sufficiently crystallized to form the crystalline phase, which is called a SET (SET) process; the transition from the stable crystalline phase to the metastable amorphous phase requires the use of an energy temperature above the melting temperature with a short activation time to rapidly heat-melt and rapidly cool the crystalline phase of the variable resistance layer 125, i.e., undergo a rapid annealing and rapid solidification process to obtain an amorphous state, which is called a RESET (RESET) process.
Further, different data is written according to the variation of the resistance value of the variable resistance layer 125. Specifically, when the phase change memory cell 10 is a single-level cell (SLC) phase change memory cell, it may write one bit of data "0" when most of the crystal phase of the variable resistance layer 125 is a crystal phase in a low resistance state (as indicated by a point a in fig. 2), and write one bit of data "1" when most of the crystal phase of the variable resistance layer 125 is an amorphous phase in a high resistance state (as indicated by a point D in fig. 2); when the phase change memory cell 10 is a multi-level cell (MLC) phase change memory cell, it may write two bits of data "00" when most of the crystal phases of the variable resistance layer 125 are the crystal phase (fourth resistance state) of the low resistance state (as indicated by point a in fig. 2), write two bits of data "11" when most of the crystal phases of the variable resistance layer 125 are the amorphous phase (first resistance state) of the high resistance state (as indicated by point D in fig. 2), write two bits of data "01" when most of the crystal phases of the variable resistance layer 125 have more crystal phases (third resistance state) (as indicated by point B in fig. 2), and write two bits of data "10" when most of the crystal phases of the variable resistance layer 125 have more amorphous phase (second resistance state) (as indicated by point C in fig. 2). It should be noted that a triple-level cell (TLC) phase change memory cell or other more multilevel cell phase change memory cells may also be applied to the present invention.
In this embodiment, the materials of the first interface barrier layer 124 and the second interface barrier layer 126 are conductive materials, which are used to prevent chemical interaction between the material of the variable resistance layer 125 and other components, thereby affecting the memory function. In one embodiment, the first interface barrier 124 and the second interface barrier 126 may be the electrodes for providing the variable resistance layer 125 with time-dependent energy, which may provide the advantage of providing energy to both sides of the variable resistance layer 125 at the same time, thereby providing a faster phase transition speed compared to a phase change memory cell using only one electrode for providing energy.
In this embodiment, the phase change memory cell 10 further includes an insulating protection layer 14, where the insulating protection layer 14 is disposed on the second electrode line, the upper electrode, and a longitudinal side of the variable resistance layer. The insulating protection layer 14 includes a nitride insulating layer 141 and an oxide insulating layer 142 in sequence along the longitudinal side surface.
In this embodiment, the variable resistance layer 125 may include one or more of group VI elements of the periodic table of elements as a phase change host, or include one or more of group III, group IV, and group V elements, for example, the phase change host material of the variable resistance layer 125 is germanium antimony tellurium alloy (Ge)xSbyTez) Which comprises Ge2Sb2Te5、Ge2Sb2Te7、Ge1Sb2Te4、Ge1Sb4Te7And the like.
When the phase change memory cell 10 is a multi-level or three-level (or more) phase change memory cell, the variable resistance layer 125 has a plurality of different resistance states. The resistance state when most of the crystal phases in the variable resistance layer 125 are the crystalline phase has the lowest resistance (e.g., point a in fig. 2), the resistance state when most of the crystal phases in the variable resistance layer 125 are the amorphous phase has the highest resistance (e.g., point D in fig. 2), and the resistance state when the crystal phases in the variable resistance layer 125 are the mixed crystal phase of the crystal phases and the amorphous phase has a resistance between the lowest resistance and the highest resistance (e.g., points B and C in fig. 2).
The inventor found that when the variable resistance layer 125 is provided with the corresponding energy and the acting time to form the corresponding resistance state, the actually formed resistance state may deviate from the resistance of the corresponding preset resistance state, and particularly, the resistance state formed through the setting process may generate a more significant resistance deviation due to the longer acting time of the energy, thereby reducing the stability of the phase change memory cell of the multi-level or three-level cell (or more levels of cells) having a plurality of resistance states.
In order to solve the above technical problem, the present invention mixes a seed crystal dopant capable of accelerating the crystallization speed of the variable resistance layer into the phase change host material of the variable resistance layer 125, so that the variable resistance layer 125 doped with the seed crystal dopant has an effect of forming a small seed crystal (crystalline seed) in the variable resistance layer 125, and thus the nucleation reaction can be accelerated, the crystallization speed can be increased, and the time for energy action can be reduced. Further, when the variable resistance layer 125 is doped with the seed dopant with a gradient change along the longitudinal direction (as shown in fig. 3), for example, the variable resistance layer 125 doped with the seed dopant includes a high-concentration seed dopant (with a doping weight percentage concentration range of preferably 2% to 5%) doped on both sides of the variable resistance layer 125 (i.e., a side of the variable resistance layer 125 close to the second interface barrier layer 126 and a side of the variable resistance layer 125 close to the first interface barrier layer 124), and a low-concentration seed dopant (with a doping weight percentage concentration range of preferably 0% to 1%) doped in the middle of the variable resistance layer 125, and the variable resistance layer 125 doped with the seed dopant with a gradient change has a boundary resistance (boundary resistance) function, which may be used to assist in stabilizing the resistance change of the variable resistance layer 125, so as to reduce the resistance deviation phenomenon of the formed resistance state, thereby implementing a stable multi-value storage function. In this way, in addition to increasing the stability of the phase change memory cell of the multi-level or three-level cell (or more) having a plurality of resistance states, the data reading range is increased and the storage speed of the phase change memory cell 10 is accelerated. In addition, the variable resistance layer 125 doped with the seed dopant (including the gradient seed dopant) can also form crystals (grains) with smaller size deviation and reduced crystal fluctuation amount, that is, the formed crystals are uniform in size, which makes the variable resistance layer 125 beneficial for forming more finely divided multiple resistance state thresholds to store data to increase reading accuracy and storage capacity. Meanwhile, the variable resistance layer 125 doped with the seed dopant (including the graded seed dopant) has a higher resistivity, increasing the efficiency of supplying energy (heating) to the variable resistance layer 125 during a reset process, reducing the loss of energy used.
In this embodiment, the seed dopant may be one of carbon, silicon, indium, tin, nitrogen, molybdenum, and tungsten nitride, as long as the seed can provide the crystallization effect.
Referring to fig. 4 and fig. 5A-5B, fig. 4 is a flowchart illustrating a method for fabricating a phase-change memory device 10 according to an embodiment of the invention, and fig. 5A-5B are schematic cross-sectional views illustrating a method for fabricating the phase-change memory device 10 according to the embodiment of the invention illustrated in fig. 4. The method comprises the following steps:
step S10: a substrate 1 is provided.
In step S10, the base plate 1 is a bonding base plate, which includes a substrate 101 and a substrate insulating layer 102 disposed on the substrate 101. The material of the substrate insulating layer 102 may be an oxide, wherein a plurality of bonding units 103 are disposed, and the plurality of bonding units 103 are used as components for connecting with other devices (including other phase change memory cells).
Step S20: the first electrode line film layer 110, the storage film layer 120, and the second electrode line film layer 130 are sequentially stacked from bottom to top along the longitudinal direction on the substrate 1, where the storage film layer 120 at least includes a variable resistance film layer 1250.
In step S20, the step of forming the storage film layer 120 includes:
a lower electrode film layer 1210, a selection device film layer 1220, an intermediate electrode film layer 1230, the resistance variable layer 1250, and an upper electrode film layer 1270 are sequentially stacked from bottom to top along the longitudinal direction on the first electrode line film layer 110.
The storage film layer 120 may further include a first interfacial barrier film layer 1240 formed between the intermediate electrode film layer 1230 and the variable resistance film layer 1250, and a second interfacial barrier film layer 1260 formed between the variable resistance film layer 1250 and the upper electrode film layer 1270, but this is not a limitation of the present invention, and embodiments of the present invention are described below with reference to the storage film layer 120 including the first interfacial barrier film layer 1240 and the second interfacial barrier film layer 1260.
The step of forming the memory film layer 120 includes at least forming a layer of the variable resistance layer 1250 made of a phase change host and a seed dopant. In this embodiment, the method for forming the variable resistance film 1250 may be to deposit a germanium antimony tellurium alloy (GexSbyTez) including the phase-change host materials such as Ge2Sb2Te5, ge2Sb2Te7, ge1Sb2Te4, and Ge1Sb4Te7 to form the variable resistance body film (corresponding to the position of the variable resistance film 1250), and then dope, for example, ion implantation (ion implantation) the entire surface of the seed dopant (blanket) to the variable resistance body film, preferably, to form the variable resistance film 1250. The seed dopant may be one of carbon, silicon, indium, tin, nitrogen, molybdenum, and tungsten-nitrogen compounds, and for convenience of description, the seed dopant is used as carbon.
Further, in the process of doping the carbon element, the doping depth of the carbon element may be controlled by controlling the energy of the ion beam, for example, in fig. 3, a first energy ion beam is used to dope a high concentration of the carbon element into a deep layer of the variable resistance body film (i.e., the side of the variable resistance layer 1250 close to the first interfacial barrier film layer 1240), a second energy ion beam is used to dope a low concentration of the carbon element into the middle of the variable resistance body film, a third energy ion beam is used to dope a high concentration of the carbon element into the surface of the variable resistance body film (i.e., the side of the variable resistance layer 1250 close to the second interfacial barrier film 1260), and after performing ion implantation of the carbon element, rapid thermal annealing is performed to uniformly diffuse the carbon element into the formed variable resistance layer 1250, wherein the first energy is greater than the second energy, the second energy is greater than the third energy (this causes the variable resistance layer 125 in each phase change memory cell 10 to include the high concentration dopant doped above and below the variable resistance layer 125, and the middle concentration of the seed crystal seed dopant).
In a modification of this embodiment, the variable resistance film layer 1250 may be formed by depositing the phase change host material and the seed dopant at the same time, for example, by evaporation, and doping the seed dopant into the phase change host material to form the variable resistance film layer 1250, that is, by introducing a seed dopant gas during the process of evaporating the phase change host material to form the variable resistance film layer 1250, the seed dopant is doped. The variable resistance layer 1250 includes high-concentration seed dopants doped at upper and lower sides of the variable resistance layer 1250, and a low-concentration seed dopant doped in the middle of the variable resistance layer 1250 (that is, the variable resistance layer 125 in each phase change memory cell 10 includes the high-concentration seed dopants doped at upper and lower sides of the variable resistance layer 125, and the low-concentration seed dopant doped in the middle of the variable resistance layer 125).
Further, the high concentration seed dopant preferably has a doping weight percentage concentration ranging from 2% to 5%, and the low concentration seed dopant preferably has a doping weight percentage concentration ranging from 0% to 1%.
In step S20, the materials and characteristics of the layers can refer to the above descriptions corresponding to the first electrode lines 11, the lower electrodes 121, the selection devices 122, the middle electrodes 123, the first interface barrier layers 124, the variable resistance layers 125, the second interface barrier layers 126, the upper electrodes 127, and the second electrode lines 13, which are not repeated herein.
Step S30: etching the first electrode line film 110, the storage film 120, and the second electrode line film 130 to form the plurality of independent phase change memory cells 10, wherein each phase change memory cell 10 includes the first electrode line film 110, the storage film 120, and the second electrode line film 130, the first electrode line 11, the storage layer 12, and the second electrode line 13 formed by etching, and the storage layer 12 includes the variable resistance layer 125, and the variable resistance layer 125 includes the phase change host substance and the seed dopant.
Step S30 includes the steps of:
performing a first etching on the second electrode line film layer 130, the upper electrode film layer 1270, the second interfacial barrier film layer 1260, the variable resistance layer 1250, and the first interfacial barrier film layer 1240 to form the second electrode line 13, the upper electrode 127, the second interfacial barrier layer 126, the variable resistance layer 125, and the first interfacial barrier layer 124, respectively, having a first width W1;
forming an insulating protection layer 14 on longitudinal sides of the second electrode lines 13, the upper electrode 127, the second interface barrier 126, the variable resistance layer 125, and the first interface barrier 124; and
performing a second etching on the middle electrode film 1230, the selection device film 1220, the lower electrode film 1210, and the first electrode line film 110 to form the middle electrode 123, the selection device 122, the lower electrode 121, and the first electrode line 11 with a second width W2, respectively.
In step S30, the insulating protection layer 14 sequentially forms a nitride insulating layer 141 and an oxide insulating layer 142 along the longitudinal side surface.
In step S30, after the insulating protection layer 14 is formed, in order to make the insulating protection layer 14 have a denser film quality, a plasma may be formed using, for example, helium gas to process the insulating protection layer 14, so as to, for example, fill up defect voids in the insulating protection layer 14, thereby forming the insulating protection layer 14 having a high film quality.
In step S30, the second etching also includes forming a groove 15 between each memory cell 10 in the substrate insulating layer 102, where the groove 15 is used to isolate two adjacent phase change memory cells 10, so as to avoid mutual influence.
To further form the phase-change memory device, the step S30 further includes:
a cell insulating protective layer 16 is formed on the side of each of the phase change memory cells 10 including the insulating protective layer 14. The material of the cell insulating protective layer 16 may be nitride.
In order to make the unit insulating protective layer 16 have a denser film quality, plasma may be formed using, for example, helium gas to perform plasma treatment on the unit insulating protective layer 16, so as to, for example, fill up defect voids in the unit insulating protective layer 16, form the unit insulating protective layer 16 having a high film quality, and after performing the plasma treatment, may further form an oxide film (not shown) on a side surface of each of the phase change memory cells 10 including the unit insulating protective layer 16.
After step S30, a cover layer 17 is formed to cover the above structure.
In this embodiment, the method for forming the first electrode line film layer 110 further includes: a first metal film 1110 and a first metal adhesive film 1120 are sequentially formed along the longitudinal direction, the first metal adhesive film 1120 is used to adhere the first metal film 1110 and the storage film 120, and after step S30, the first metal layer 111 and the first metal adhesive layer 112 are formed.
The method for forming the second electrode line film layer 130 further includes: a second metal film 1310 and a second metal adhesive film 1320 are sequentially formed along the longitudinal direction, the second metal adhesive film 1320 is used to adhere the second metal film 1310 and the storage film 120, and after step S30, the second metal layer 131 and the first metal adhesive layer 132 are formed.
Further, the material of the first metal adhesive film 1120 and the second metal adhesive film 1320 includes tungsten nitride.
The variable resistance layer 125 is doped with the seed crystal dopant to accelerate the crystallization speed, and further, when the variable resistance layer 125 has the seed crystal dopant with gradient change, the resistance value change of the variable resistance layer 125 can be stabilized, and the resistance value deviation of the formed resistance value state is reduced; the variable resistance layer 125 doped with the seed dopant (including the gradient seed dopant) can also form crystals with small size deviation and slow down the fluctuation amount of the crystals, so that the variable resistance layer 125 facilitates the formation of a plurality of resistance states to store data; the variable resistance layer 125 doped with the seed dopant (including the graded seed dopant) has a higher resistivity, increasing the efficiency of supplying energy to the variable resistance layer 125 during a reset process, reducing the loss of energy used.
Embodiments also provide a semiconductor device that may be applied to, for example, a neuron, and the semiconductor device includes the above-described phase-change memory device.
Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above-described preferred embodiments, and those skilled in the art can make various changes and modifications without departing from the scope of the present invention.
Claims (23)
1. A method of fabricating a phase change memory device, comprising the steps of:
providing a substrate;
stacking a first electrode wire film layer, a storage film layer and a second electrode wire film layer on the substrate from bottom to top along the longitudinal direction; and the number of the first and second groups,
etching the second electrode wire film layer, the storage film layer and the first electrode wire film layer to form a plurality of independent phase change storage units;
the step of forming the storage film layer at least comprises forming a variable resistance film layer which is composed of a phase change main body and a seed crystal adulterant, wherein the phase change storage unit comprises a first electrode wire, a storage layer and a second electrode wire which are respectively formed by etching the first electrode wire film layer, the storage film layer and the second electrode wire film layer, the storage layer contains a variable resistance layer, and the variable resistance layer comprises high-concentration seed crystal adulterants which are positioned at the upper side and the lower side of the variable resistance layer and a low-concentration seed crystal adulterant which is positioned in the middle of the variable resistance layer.
2. The method of claim 1, wherein: the step of forming the variable resistance film layer includes depositing the phase-change host material and doping the seed dopant into the phase-change host material to form the variable resistance film layer.
3. The method of claim 1, wherein: the step of forming the variable resistance film layer includes: depositing the phase-change host species to form a variable resistance body film layer, and implanting the seed dopant into the variable resistance body film layer to form the variable resistance film layer, and the implanting the seed dopant into the variable resistance body film layer includes: the variable resistance layer is formed by doping a high-concentration seed dopant at the lower side of the variable resistance body film layer by using a first energy ion beam, doping a low-concentration seed dopant at the middle of the variable resistance body film layer by using a second energy ion beam, and doping a high-concentration seed dopant at the upper side of the variable resistance body film layer by using a third energy ion beam, so that the variable resistance layer comprises the high-concentration seed dopant doped at the upper side and the lower side of the variable resistance layer and the low-concentration seed dopant doped at the middle of the variable resistance layer, wherein the first energy is greater than the second energy, and the second energy is greater than the third energy.
4. A method according to claim 1 or 3, characterized in that: the high-concentration seed crystal dopant is doped in a weight percentage concentration range of 2% to 5%, and the low-concentration seed crystal dopant is doped in a weight percentage concentration range of 0% to 1%.
5. The method of claim 1, wherein: the seed dopant includes one of a carbon element, a silicon element, an indium element, a tin element, a nitrogen element, a molybdenum element, and a tungsten-nitrogen compound.
6. The method of claim 1, wherein the step of forming a storage film layer further comprises:
and stacking the first electrode wire film layer and the variable resistance film layer from bottom to top along the longitudinal direction to form a lower electrode film layer, a selection device film layer and a middle electrode film layer, and forming an upper electrode film layer above the variable resistance film layer.
7. The method of claim 6, wherein the step of forming the storage film layer further comprises:
forming a first interfacial barrier film layer between the variable resistance film layer and the intermediate electrode film layer; and
forming a second interfacial barrier film layer between the variable resistance film layer and the upper electrode film layer.
8. The method of claim 6, wherein the step of etching the second electrode line film layer, the storage film layer, and the first electrode line film layer comprises:
etching the second electrode wire film layer, the upper electrode film layer and the variable resistance film layer for the first time to form the second electrode wire, the upper electrode and the variable resistance layer with first widths respectively;
forming an insulating protection layer on the second electrode line, the upper electrode, and a longitudinal side of the variable resistance layer; and
performing second etching on the middle electrode film layer, the selection device film layer, the lower electrode film layer and the first electrode wire film layer to respectively form a middle electrode, a selection device, a lower electrode and a first electrode wire with a second width;
wherein the first width is less than the second width.
9. The method of claim 8, wherein: the insulating protective layer sequentially comprises a nitride insulating layer and an oxide insulating layer along the longitudinal side surface outwards.
10. The method of claim 1, wherein: the doping concentration of the seed dopant in the variable resistance layer is changed in a gradient manner along the longitudinal direction.
11. The method of claim 1, wherein:
the step of forming the first electrode line film layer comprises the following steps: forming a first metal film layer and a first metal adhesive film layer along the longitudinal direction, the first metal adhesive film layer being located between the first metal film layer and the storage film layer; and
the step of forming the second electrode line film layer comprises the following steps: and forming a second metal film layer and a second metal bonding film layer along the longitudinal direction, wherein the second metal bonding film layer is positioned between the second metal film layer and the storage film layer.
12. The method of claim 11, wherein: the material of the first metal adhesive film layer and the second metal adhesive film layer comprises tungsten nitride.
13. The method of claim 1, wherein: the material of the phase change main body comprises germanium antimony tellurium alloy (Ge)xSbyTez）。
14. A phase change memory device comprising a plurality of phase change memory cells, the phase change memory cells comprising:
a first electrode line;
the memory layer is arranged on the first electrode line along the longitudinal direction and at least comprises a variable resistance layer, and the variable resistance layer comprises a phase change host substance and a seed crystal dopant; and
second electrode lines disposed on the memory layer in the longitudinal direction;
wherein the variable resistance layer includes: the variable resistance layer is doped with high-concentration seed crystal dopants at the upper side and the lower side of the variable resistance layer, and the low-concentration seed crystal dopants in the middle of the variable resistance layer.
15. The phase-change memory device according to claim 14, wherein: the seed dopant includes one of a carbon element, a silicon element, an indium element, a tin element, a nitrogen element, a molybdenum element, and a tungsten-nitrogen compound.
16. The phase-change memory device according to claim 14, wherein: the high-concentration seed crystal dopant is doped in a weight percentage concentration range of 2% to 5%, and the low-concentration seed crystal dopant is doped in a weight percentage concentration range of 0% to 1%.
17. The phase-change memory device according to claim 14, wherein: the storage layer further comprises a lower electrode, a selection device, a middle electrode and an upper electrode, wherein the lower electrode, the selection device and the middle electrode are sequentially stacked between the first electrode wire and the variable resistance layer from bottom to top along the longitudinal direction, and the upper electrode is arranged above the variable resistance layer.
18. The phase-change memory device according to claim 17, wherein: the memory layer further includes a first interface barrier layer disposed between the variable resistance layer and the intermediate electrode, and a second interface barrier layer disposed between the variable resistance layer and the upper electrode.
19. The phase-change memory device according to claim 14, wherein: the first electrode line is followed vertically include first metal level and first metal adhesion layer, the second electrode line is followed vertically include second metal level and second metal adhesion layer, first metal adhesion layer is located the first metal level with between the storage layer, the second metal adhesion layer is located the second metal level with between the storage layer.
20. The phase-change memory device according to claim 14, wherein: the doping concentration of the seed dopant in the variable resistance layer is changed in a gradient manner along the longitudinal direction.
21. The phase-change memory device according to claim 14, wherein: the material of the phase change main body comprises germanium antimony tellurium alloy (Ge)xSbyTez）。
22. The phase change memory device of claim 17, further comprising:
and the insulation protection layer is arranged on the second electrode wire, the upper electrode and the longitudinal side surface of the variable resistance layer, and sequentially comprises a nitride insulation layer and an oxide insulation layer along the longitudinal side surface outwards.
23. A semiconductor device characterized by comprising the phase-change memory device according to any one of claims 14 to 22.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110063237.4A CN112786784B (en) | 2021-01-18 | 2021-01-18 | Phase change memory device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110063237.4A CN112786784B (en) | 2021-01-18 | 2021-01-18 | Phase change memory device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112786784A CN112786784A (en) | 2021-05-11 |
| CN112786784B true CN112786784B (en) | 2022-11-01 |
Family
ID=75757172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110063237.4A Active CN112786784B (en) | 2021-01-18 | 2021-01-18 | Phase change memory device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112786784B (en) |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7893419B2 (en) * | 2003-08-04 | 2011-02-22 | Intel Corporation | Processing phase change material to improve programming speed |
| US20050062087A1 (en) * | 2003-09-19 | 2005-03-24 | Yi-Chou Chen | Chalcogenide phase-change non-volatile memory, memory device and method for fabricating the same |
| TWI277207B (en) * | 2004-10-08 | 2007-03-21 | Ind Tech Res Inst | Multilevel phase-change memory, operating method and manufacture method thereof |
| US20060289847A1 (en) * | 2005-06-28 | 2006-12-28 | Richard Dodge | Reducing the time to program a phase change memory to the set state |
| TWI312998B (en) * | 2005-12-23 | 2009-08-01 | Ind Tech Res Inst | Phase-change recording layer and method of manufacturing the same and phase-change recording cell using such recording layer |
| US7723712B2 (en) * | 2006-03-17 | 2010-05-25 | Micron Technology, Inc. | Reduced power consumption phase change memory and methods for forming the same |
| US7501648B2 (en) * | 2006-08-16 | 2009-03-10 | International Business Machines Corporation | Phase change materials and associated memory devices |
| US7550313B2 (en) * | 2007-07-21 | 2009-06-23 | International Business Machines Corporation | Method for delineation of phase change memory (PCM) cells separated by PCM and upper electrode regions modified to have high film resistivity |
| US8617972B2 (en) * | 2009-05-22 | 2013-12-31 | Advanced Technology Materials, Inc. | Low temperature GST process |
| KR20120104031A (en) * | 2011-03-11 | 2012-09-20 | 삼성전자주식회사 | Phase change material layer, method of forming a phase change layer, phase change memory device and method of manufacturing a phase change memory device |
| US20160181515A1 (en) * | 2014-12-18 | 2016-06-23 | Stmicroelectronics S.R.I. | Embedded phase change memory devices and related methods |
| KR20170099214A (en) * | 2016-02-23 | 2017-08-31 | 삼성전자주식회사 | Variable resistance memory devices and methods of manufacturing the same |
| CN105742490B (en) * | 2016-03-11 | 2018-09-07 | 中国科学院上海微系统与信息技术研究所 | A kind of phase-change material layers structure improving phase transition storage data retention |
| CN110098322A (en) * | 2018-01-30 | 2019-08-06 | 中国科学院上海微系统与信息技术研究所 | C adulterates Sc-Sb-Te phase-change storage material, phase-changing memory unit and preparation method thereof |
| US10454025B1 (en) * | 2018-06-13 | 2019-10-22 | International Business Machines Corporation | Phase change memory with gradual resistance change |
| CN110335941B (en) * | 2019-07-03 | 2023-08-18 | 芯盟科技有限公司 | Phase change memory structure and forming method thereof |
| CN111816766B (en) * | 2020-08-27 | 2020-11-27 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
| CN112164748B (en) * | 2020-09-17 | 2021-12-28 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
-
2021
- 2021-01-18 CN CN202110063237.4A patent/CN112786784B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112786784A (en) | 2021-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6708722B2 (en) | Resistive switching device having switching layer and intermediate electrode layer and method of forming the same | |
| KR101929458B1 (en) | Ge-RICH GST-212 PHASE CHANGE MEMORY MATERIALS | |
| US8481359B2 (en) | Methods of forming a phase change material | |
| US7879645B2 (en) | Fill-in etching free pore device | |
| US7569844B2 (en) | Memory cell sidewall contacting side electrode | |
| US8003970B2 (en) | Phase-change random access memory and method of manufacturing the same | |
| TWI357154B (en) | Phase change memory cell with filled sidewall memo | |
| US7919766B2 (en) | Method for making self aligning pillar memory cell device | |
| JP2006165553A (en) | Phase-change memory device comprising phase-change substance layer including phase-change nano particle and method for manufacturing the same | |
| US8916414B2 (en) | Method for making memory cell by melting phase change material in confined space | |
| US11211427B2 (en) | Switching element, variable resistance memory device, and method of manufacturing the switching element | |
| CN102832340B (en) | Phase transition storage unit and manufacture method thereof | |
| US6825135B2 (en) | Elimination of dendrite formation during metal/chalcogenide glass deposition | |
| US10833265B2 (en) | Storage device | |
| CN112786784B (en) | Phase change memory device and manufacturing method thereof | |
| EP1848047A2 (en) | Transitioning the state of phase change material by annealing | |
| CN112840460A (en) | Phase change memory cell and method of manufacturing the same | |
| US20230047263A1 (en) | Elementary cell comprising a resistive memory and a device intended to form a selector, cell matrix, associated manufacturing and initialization methods | |
| KR20090015716A (en) | Phase-change memory device having upper plate electrode with increasing resistance and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |