CN112786539B - Two-stage excitation self-destruction chip based on array pore canal and preparation method thereof - Google Patents
Two-stage excitation self-destruction chip based on array pore canal and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a secondary excitation self-destruction chip based on an array pore canal and a preparation method thereof, wherein the secondary excitation self-destruction chip comprises a basal layer and a self-destruction structure; the basal layer is a target chip; the self-destruction structure is arranged on the back of the target chip and comprises a heating circuit, a plurality of pore canals and an energy-containing material layer, the pore canals are arranged in an array manner in a damage-like area on the target chip, the energy-containing material layer covers a heating area of the heating circuit and the pore canal array area, and the heating circuit is connected in series in a circuit loop formed by an external control unit and a power supply unit. The self-destruction chip can be prepared by a conventional chip preparation process. The self-destruction chip adopts a secondary excitation structure of weak current excitation-chemical explosion, and three-dimensional structures such as an array pore canal, a deep hole and the like are arranged on a semiconductor substrate to reduce the strength of the substrate, so that the smashing damage of the target chip is realized, the thorough destruction of the target chip under the working condition of low power consumption is realized by two technical means, and the information safety of the chip is ensured.
Description
Technical Field
The invention belongs to information safety and semiconductor devices, relates to a structural design which can be integrated with a core chip or a micro-electromechanical device (MEMS) and has a self-destruction function and a preparation method thereof, and in particular relates to a secondary excitation self-destruction chip based on an array pore canal and a preparation method thereof.
Background
With the rapid development of modern information technology, various semiconductor devices based on semiconductor materials such as silicon, gallium nitride and the like are widely applied to links such as information acquisition, analysis, storage, transmission and the like in the field of army and civilian, and a large amount of core data is inevitably stored in some information terminal equipment. If the information terminal equipment is lost or stolen, the important information stored in the memory chip can be stolen and compromised, so that the self-destruction function of the memory chip and other important chips is required to be added during product planning and design, and the core chip can be destroyed under emergency conditions to protect the information from being leaked. In addition, the precise MEMS device embodies the exquisite design thought of a designer, and a corresponding self-destruction structure needs to be integrated to prevent the imitation by tearing.
At present, a strong pulse current impact method is mostly adopted in chip self-destruction design, and a chip circuit is broken down by utilizing the strong pulse current which is instantaneously conducted so as to lose the function of the chip circuit, but the chip is broken down only in a small area, so that the chip is not completely destroyed, the whole structure is still reserved, and the possibility of partially recovering stored information is still realized. Only if the physical structure or the functional layer of the chip is completely destroyed by adopting a physical or chemical method, the chip can be completely destroyed, and the information cannot be recovered. The 200480013540.8 patent discloses a device structure for etching a storage medium with a reactant chemical, but the structure is complex in design and is not reliable enough.
In summary, the development of the self-destruction chip with high safety and reliability and complete self-destruction of the chip with important information to ensure the information safety has important significance for the information safety assurance of the chip in the field.
Disclosure of Invention
The invention aims to solve the problems and provide a secondary excitation self-destruction chip based on an array type pore canal and a preparation method thereof, wherein the self-destruction chip adopts a secondary excitation structure of weak current excitation-chemical explosion, three-dimensional structures such as an array type pore canal, a deep hole and the like are prepared on the back surface of a basal layer (target chip) to reduce the strength of a basal body, and an energetic material is coated, so that the smashing damage to the target chip is realized, the thorough destruction to the target chip is realized under the low-power consumption working condition by the technical means, and the information safety of the target chip is ensured.
In order to achieve the purpose, the two-stage excitation self-destruction chip based on the array pore canal provided by the invention comprises a basal layer and a self-destruction structure;
the basal layer is a target chip;
the self-destruction structure is arranged on the back of the target chip and comprises a heating circuit, a plurality of pore canals and an energy-containing material layer, the pore canals are arranged in an array mode in a to-be-destroyed area on the target chip, the energy-containing material layer covers a heating area of the heating circuit and at least part of the pore canal array area, and the heating circuit is connected in series in a circuit loop formed by an external control unit and a power supply unit.
The two-stage excitation self-destruction chip based on the array pore canal comprises a silicon substrate and a target circuit arranged on the silicon substrate. The target circuit is designed to realize a certain function, such as storage, logic operation, logic control, etc. The present invention does not improve the target circuit, and any existing chip carrying any functional target circuit in the field can be used as the target chip of the present invention. Similarly, the preparation of the target chip may be carried out in a conventional manner, and is not particularly limited.
The two-stage excitation self-destruction chip based on the array pore canal, wherein the external control unit comprises a photosensitive switch or/and a force-sensitive switch, and two ends of the photosensitive switch or/and the force-sensitive switch are respectively connected with a heating circuit and a power supply unit. When the external control unit comprises a photosensitive switch and a force-sensitive switch at the same time, the photosensitive switch and the force-sensitive switch are connected in parallel and then connected into the heating circuit, and are connected with the power supply unit. The photosensitive switch and the force-sensitive switch are used as preset triggering conditions, when the package tube shell of the chip is subjected to unauthorized uncovering, the force-sensitive switch can sense the change of fastening force when the package body is uncovered to conduct the heating circuit, and meanwhile, the photosensitive switch can sense the brightness change inside the package body to conduct the heating circuit on the back of the core chip as a parallel triggering mechanism. After the heating circuit is loaded with current, a hot area is formed locally and a blasting reaction is excited, and huge impact force is formed in the airtight packaging shell instantaneously, so that a target chip is quickly and accurately destroyed, and core information is prevented from being stolen. It should be noted that the preset triggering condition may be only a photosensitive switch or a force-sensitive switch, and the triggering condition is not limited to the photosensitive switch and the force-sensitive switch. Moreover, the preset triggering conditions can be set in other conventional manners in the art, such as setting corresponding self-destruction programs and circuits in the chip, so that the chip automatically turns on the heating circuit after receiving the command; or a self-destruction procedure using a laser trigger chip, etc. The invention adopts a two-stage parallel triggering mechanism formed by the photosensitive switch and the force-sensitive switch, and is simple and easy to implement.
The two-stage excitation self-destruction chip based on the array pore canal is mainly used for heating the energy-containing material layer, and on the basis that the energy-containing material layer can be heated to be burnt and exploded, a person skilled in the art can correspondingly design the heating circuit according to actual conditions. In the invention, the heating circuit comprises an electrode pad, two metal wires and a heating wire, wherein the electrode pad comprises an anode pad and a cathode pad, the anode pad and the cathode pad are respectively connected with one metal wire, the two end parts of the heating wire are respectively connected with the two metal wires, the anode pad and the cathode pad are respectively connected with an external control unit and a power supply unit, and the heating wire is a heating zone of the heating circuit.
The two-stage excitation self-destruction chip based on the array pore canal is mainly used for providing excitation energy for energetic materials, and the specific size of the heating wire is designed based on the fact that the corresponding excitation energy can be provided, and can refer to the conventional heating wire parameters in the field. The heating wire preferably has a width of 2-50 μm, a wire length of 500-50000 μm (curved arrangement), an aspect ratio of 200-5000, a wire thickness of 200-1000nm, and further preferably has a width of 2-10 μm, an aspect ratio of 500-1000, and a wire thickness of 200-1000nm.
The heating circuit can be made of conventional materials such as aluminum, copper and the like, and can also be made of alloy materials with high melting point, such as NiCr alloy or W alloy. The chip is typically a silicon substrate. In order to improve the bonding strength of metal electrodes such as aluminum, copper and the like and a silicon substrate, a good interface bonding force is formed, and an annealing process is usually carried out, which also causes the mutual diffusion of the metal electrode and Si to reduce the electrical performance of the electrode. In order to prevent the interdiffusion phenomenon, a blocking layer is preferably arranged between the silicon substrate and the heating circuit (metal electrode), the blocking layer is a silicon nitride or silicon dioxide film, the interdiffusion between the silicon substrate and the metal electrode is blocked, the heating chip can bear higher heating temperature, and the temperature and the reliability of a hot zone of the heating circuit are improved.
The two-stage excitation self-destruction chip based on the array pore canal is designed for reducing the matrix strength, so that the smashing damage of the target chip is realized, meanwhile, the dosage and the chip area of the blasting agent can be reduced by introducing the porous array structure, the directional fixed-point damage is realized, and the damage effect is improved. In order to ensure good self-destruction effect, the conventional method is to increase the filling amount of the energy-containing material, and the coating thickness of the energy-containing material is too high to reduce the binding force and easily fall off, so that the chip area is necessarily increased by limiting the coating thickness. The porous silicon array structure design is adopted, the energetic material filled into the pore canal has better self-destruction effect, and in addition, the binding force between the coating of the energetic material and the chip is better due to the filling of the pore canal. The shape of the layer of energetic material is not particularly limited and may take the form of, but is not limited to, a circular, square, or other irregular shape. The layer of energetic material may cover a portion of the cell array region or the entire cell array region. Preferably, the pore spacing of the pore channel array is 20-200 microns; the aperture width of the pore canal is 10-100 micrometers, and the depth of the pore canal is 20-200 micrometers. The shape of the tunnel is not particularly limited, and may take the form of, but not limited to, a circle, a rectangle, or a regular polygon.
The two-stage excitation self-destruction chip based on the array pore canal covers the pore canal array and the heating area of the heating circuit, when heated, the energy-containing material generates a severe explosion reaction, and strong impact is instantaneously generated on the target chip in the sealed packaging shell, so that the target chip is thoroughly damaged in penetration or crushing. I.e., energetic materials, whose primary function is chemical explosion, may be employed as are conventional in the art. In the present invention, the energetic material is preferably lead stevenate.
According to the secondary excitation self-destruction chip based on the array pore canal, based on the design thought of physical damage, the secondary excitation structure design of weak current excitation-chemical blasting is adopted, when the preset triggering condition is met, the self-destruction program of the chip is activated, the excitation circuit is conducted to release heat, the energetic material pre-buried in the pore canal on the back of the target chip is heated to generate severe blasting reaction, and strong impact is instantaneously generated on the target chip in the sealed packaging shell, so that the target chip is thoroughly damaged through or in a crushing manner. The physical damage of penetration or crushing property has irrecoverability and more thorough damage effect. The self-destruction structure on the self-destruction chip provided by the invention is mainly used in the field of information security, and especially can be used for irrecoverable and thorough physical destruction of semiconductor-based devices such as a core memory chip, a key MEMS device and the like.
The invention also provides a preparation method of the array pore canal-based two-stage excitation self-destruction chip, which mainly comprises the following steps:
s1, preparing an insulating layer on the back of a substrate, and depositing a metal conducting layer on the surface of the insulating layer;
s2, etching the metal conductive layer into a heating circuit by adopting a photoetching process;
s3, etching a pore array on the substrate by adopting a photoetching process according to the to-be-damaged area, wherein the range of the pore array covers the to-be-damaged area of the target chip;
s4, coating an energy-containing material layer on the back surface of the target chip by adopting a coating process, wherein the energy-containing material layer covers a heating area of the heating circuit and at least part of the pore channel array area;
and S5, connecting the heating circuit with an external control unit and a power supply unit.
In the preparation method of the two-stage excitation self-destruction chip based on the array pore canal, in the step S1, the preparation of the insulating layer and the metal conducting layer is carried out by adopting the conventional preparation mode and parameters in the field, and no special requirements are required. In the present invention, the insulating layer is preferably prepared on the substrate by a thermal oxidation or chemical vapor deposition process, and the metal conductive layer is deposited on the surface of the insulating layer by a magnetron sputtering or evaporation process. In general, the base material of the base can be a silicon single crystal substrate which is conventional in the art, the insulating layer is a silicon dioxide or silicon nitride insulating layer, the thickness is 10-200nm, and a thermal oxidation process is further preferred to prepare a silicon dioxide oxide film; the metal conductive layer is preferably an aluminum conductive layer or a copper conductive layer, and the thickness of the metal conductive layer is 200-1000nm. Further, the processes involved in the steps, such as photolithography process and plasma dry etching process, may be all conventional parameters in the art, and are not particularly limited.
In the present invention, the step S1 specifically includes the following steps:
s11, cleaning preparation: cleaning a substrate containing a silicon matrix, and drying for later use;
s12, preparing an oxide film: after the treatment of the step S11, the substrate is placed in a thermal oxidation furnace, the oxidation furnace chamber is sealed and vacuumized to be lower than 10 -1 Pa, introducing oxygen, heating the furnace body to 1050-1150 ℃ according to a heating rate of 15-25 ℃/min, preserving heat for 10-20 minutes, cooling to below 400 ℃ according to a cooling rate of 15-25 ℃/min, and naturally cooling to room temperature to form a silicon dioxide oxide film;
s13, coating: after the treatment of the step S12, the substrate is placed on a sample table of a coating machine, and is vacuumized to 10 -3 Pa or below, at 15-25cm 3 Argon is filled into the flow of/min to 0.2-0.8Pa, sputtering coating is carried out on the metal target material to form a metal film, the coating time is 5-20min, and then the metal film is naturally cooled to room temperature.
In the step S11, the substrate is cleaned and dried in a conventional manner in the art, preferably by sequentially ultrasonic cleaning with acetone, ethanol and deionized water for 10-20 minutes, taking out, dehydrating in nitrogen atmosphere at 250-350 ℃, and baking and drying. The metal target is aluminum or copper.
In the present invention, the step S2 specifically includes the following steps:
s21, gluing, whirl coating and soft baking: placing the coated substrate on a gumming machine, dripping the coating, then throwing the coating, heating to 100-120 ℃ in vacuum, and preserving the temperature for 30-60s for soft baking;
s22, exposing and post-baking: after the treatment in the step S21, placing the substrate on a sample stage of an exposure machine, copying a heating circuit diagram on photoresist, and then placing the substrate in an environment of 110-130 ℃ for heat preservation for 1-3min for post-baking treatment;
s23, developing and hard baking: after the treatment in the step S22, the developing solution is sprayed on the surface of the substrate for developing, and then the substrate is placed in an environment of 110-130 ℃ for heat preservation for 1-3min for hard drying treatment, so that the heating circuit pattern is exposed;
s24, etching: after the treatment in the step S23, placing the substrate in an etching machine, introducing chlorine as working gas to ionize and dry etch the metal film, and removing the exposed redundant metal film;
s25, photoresist removal: after the treatment in step S24, the excess photoresist is removed sequentially with acetone and isopropyl alcohol, and then the substrate is washed with deionized water and dried.
In the step S2, in the step S21, the substrate can rotate at a low speed during the glue dripping, and then rotate at an accelerated speed to 2800-3200rpm for spin coating after the glue dripping is completed. After the photoresist is removed in step S25, the quality of the heating circuit can be checked by a microscope, so as to ensure that the heating area is not broken.
The step S3 specifically comprises the following steps:
s31, gluing, whirl coating and soft baking: after the treatment in the step S25, placing the substrate on a glue spreader, dripping glue, then throwing the glue, heating to 100-120 ℃ in vacuum, and preserving heat for 30-60S for soft baking treatment;
s32, exposing and post-baking: after the treatment in the step S31, placing the substrate on a sample stage of an exposure machine, copying the pore channel pattern on photoresist, and then placing the substrate in an environment of 110-130 ℃ for heat preservation for 1-3min for post-baking treatment;
s33, developing and hard baking: after the treatment in the step S32, spraying a developing solution on the surface of the substrate for developing, and then placing the substrate in an environment of 110-130 ℃ for heat preservation for 1-3min for hard drying treatment to expose the pore channel patterns;
s34, etching: after the treatment of the step S33, the substrate is placed in an etching machine and C is introduced 2 F 6 Ionization of silicon dioxide oxide film and silicon substrate as working gasEtching by a method to form a pore channel with a set depth;
s35, photoresist removal: after the treatment in step S34, the excess photoresist is removed sequentially with acetone and isopropyl alcohol, and then the substrate is washed with deionized water and dried.
In the step S3, in the step S31, the substrate can rotate at a low speed during the glue dripping, and then the substrate is accelerated to rotate to 2800-3200rpm for spin coating after the glue dripping is completed. After the photoresist removal in step S35 is completed, the etching quality of the pore canal is checked by a microscope, so that the pore canal is ensured to reach the corresponding design size and coverage area.
In the preparation method of the array-type pore canal-based two-stage excitation self-destruction chip, the coating process involved in the step S4 can be, but is not limited to, screen printing or dripping. After the coating of the energetic material, it can be dried at a low temperature of 30-50 ℃.
In the preparation method of the two-stage excitation self-destruction chip based on the array pore canal, when the photosensitive switch or/and the force-sensitive switch is adopted to form an external control unit as a preset triggering condition, in the step S5, the photosensitive switch or/and the force-sensitive switch is connected between the power supply unit and the heating circuit, and then the packaging is carried out. When the external control unit comprises a photosensitive switch and a force-sensitive switch at the same time, the photosensitive switch and the force-sensitive switch are required to be connected in parallel firstly and then connected between the power supply unit and the heating circuit.
The invention provides a secondary excitation self-destruction chip based on an array pore canal and a preparation method thereof, which have the innovation points and the protection points of a self-destruction structure and a preparation method of the self-destruction structure, and the preparation of a target chip is carried out by adopting a conventional preparation method, so that the circuit structure of the target chip is not limited, such as an MEMS structure and the like. The self-destruction structure provided by the invention can be prepared first, and then the preparation of the target chip is carried out. Or the circuit structure of the target chip can be prepared first, and then the self-destruction structure can be prepared. In the invention, the preparation of the target chip circuit structure is preferably carried out after the self-destruction structure is prepared.
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
(1) The secondary excitation self-destruction chip based on the array pore canal adopts the secondary excitation structure design of weak current excitation-chemical explosion, when the preset triggering condition is met, the self-destruction program of the chip is activated, an excitation circuit is conducted to release heat, the energetic material pre-buried in the pore canal of the back of the target chip is heated to generate severe explosion reaction, and strong impact is instantaneously generated on the target chip in the sealed packaging shell, so that the target chip is thoroughly damaged in penetration or crushing, the physical damage in penetration or crushing is irrecoverable, the damage effect is more thorough, and the information safety of the target chip is ensured.
(2) According to the two-stage excitation self-destruction chip based on the array pore canal, the three-dimensional structures such as the pore canal, the deep hole and the like are designed on the semiconductor substrate to reduce the strength of the substrate, meanwhile, the dosage and the chip area of the blasting agent can be reduced, the directional fixed-point damage is realized, and the damage effect on the smashing performance of the target chip is achieved under the low-power consumption working condition.
(3) The two-stage excitation self-destruction chip based on the array pore canal provided by the invention adopts a trigger mechanism formed by the photosensitive switch and the force-sensitive switch, can realize the rapid self-destruction of the core chip during unauthorized dissection, and can effectively ensure the safety of important sensitive information and key chip technology.
(4) The two-stage excitation self-destruction chip based on the array pore canal provided by the invention has the advantages that the self-destruction structure is manufactured on the substrate by photoetching and film plating methods, and meanwhile, the adopted photosensitive switch and the adopted force-sensitive switch are integrated with the target chip, so that the single-tube shell integration of the whole self-destruction chip is realized, the original chip is slightly changed, and the controllability is high.
(5) The two-stage excitation self-destruction chip based on the array pore canal and the preparation method thereof provided by the invention have the characteristics of high secrecy, microminiaturization, low power consumption, high controllability and the like, and have the advantages of safety, reliability, high technical maturity, small change of original chip processing and wide application range, and the preparation process is mature and easy to operate, is easy to industrialize and is worthy of popularization.
Drawings
FIG. 1 is a schematic diagram of the self-destructing structure in embodiment 1;
fig. 2 is a schematic structural diagram of a self-destruction chip (photosensitive switch and force-sensitive switch are not shown) in embodiment 1;
FIG. 3 is a schematic diagram of a self-destructing chip package structure in embodiment 1;
fig. 4 is a self-destruction effect diagram of the self-destruction chip provided in embodiment 1; wherein, (a) is a packaged picture before self-destruction, and (b) is a chip destroyed picture after self-destruction.
Reference numerals illustrate: 1. an electrode pad; 2. a metal wire; 3. a heating wire; 4. a duct; 5. a target chip; 6. an energy-containing material layer; 7. a photosensitive switch; 8. a force sensitive switch; 9. and a power supply.
Detailed Description
In order to clearly and fully describe the technical solutions of the various embodiments of the invention, reference should be made to the accompanying drawings, it is apparent that the described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on the embodiments of the present invention, are within the scope of the present invention.
Example 1
In this embodiment, the two-stage excitation self-destruction chip based on the array pore canal is shown in fig. 1-3. The secondary excitation self-destruction chip based on the array pore canal comprises a basal layer and a self-destruction structure.
The base layer is the target chip 5.
The self-destruction structure is arranged on the back of the target chip 5 and comprises a heating circuit, a plurality of pore canals 4, an energy-containing material layer 6, a photosensitive switch 7, a force-sensitive switch 8 and a power supply 9. The pore channels 4 are arranged in an array manner in a to-be-damaged area on the target chip 5, and the energy-containing material layer 6 covers a heating area of the heating circuit and a part of the pore channel array area.
The heating circuit comprises an electrode pad 1, two metal wires 2 and a heating wire 3, wherein the electrode pad 1 comprises an anode pad and a cathode pad, the anode pad and the cathode pad are respectively connected with one metal wire 2, the two end parts of the heating wire 3 are respectively connected with the two metal wires 2, the anode pad and the cathode pad are respectively connected with an external control unit and a power supply unit (namely, a power supply), and the heating wire 3 is a heating zone of the heating circuit. The heating wire 3 has a width of 4 μm, a length of 2000 μm, an aspect ratio of 500 and a thickness of 500nm.
The hole spacing of the hole array is 50 mu m; the cross section of the cell channels 4 was 10X 10 μm square, and the depth of the cell channels 4 was 50. Mu.m. The overall size of the array is 5×5 mm.
The energy-containing material layer 6 is a lead stevenate coating; the section of the material is round with the diameter of 4 mm and the thickness of 0.3mm.
The external control unit comprises a photosensitive switch 7 and a force sensitive switch 8. The photosensitive switch 7 and the force-sensitive switch 8 are connected in parallel, the positive electrode of the power supply 9 is connected into the positive electrode bonding pad through a gold wire after passing through the parallel photosensitive switch 7 and the force-sensitive switch 8, and the negative electrode of the power supply is connected with the negative electrode bonding pad through the gold wire.
Example 2
The following describes a preparation method of the array pore canal-based two-stage excitation self-destruction chip provided in embodiment 1, in this embodiment, the base material of the base is a silicon single crystal substrate, and the specific steps are as follows:
s1, providing a silicon single crystal substrate, preparing an insulating layer on the back surface of the silicon single crystal substrate, and depositing a metal conducting layer on the surface of the insulating layer:
s11, cleaning preparation: cleaning a silicon single crystal substrate, sequentially and respectively ultrasonically cleaning the silicon single crystal substrate by using acetone, ethanol and deionized water for 10min, taking out, dehydrating, baking and drying at 300 ℃ in nitrogen atmosphere for later use;
s12, preparing an oxide film: after the treatment of the step S11, vertically placing the silicon single crystal substrate on a sample holder, pushing the silicon single crystal substrate into a thermal oxidation furnace, sealing an oxidation furnace chamber, and vacuumizing to be lower than 10 -1 Pa, introducing oxygen, heating the heating furnace body to 1100 ℃ according to a heating rate of 15 ℃/min, preserving heat for 10min, cooling to 400 ℃ according to a cooling rate of 15 ℃/min, and naturally cooling to room temperature;
s13, coating: after the treatment of the step S12, the silicon single crystal substrate is placed on a sample table of a coating machine and vacuumized to 10 - 3 Pa or less, at 20cm 3 Argon is filled into the reactor at the flow rate of/min to 0.5Pa, and the reactor is openedAnd starting a direct current sputtering power supply to perform sputtering coating on the aluminum target to form an aluminum film, wherein the coating time is 10min, and then naturally cooling to room temperature.
S2, etching the metal conductive layer into a heating circuit by adopting a photoetching process:
s21, gluing, whirl coating and soft baking: after the treatment in the step S13, placing the silicon single crystal substrate subjected to film coating on a glue spreader, rotating at a low speed, dripping glue, accelerating to rotate to 3000rpm for spin coating, heating to 110 ℃ in vacuum, and preserving heat for 45S for soft baking treatment;
s22, exposing and post-baking: after the treatment in the step S21, the silicon single crystal substrate is placed on a sample stage of an exposure machine, pre-alignment is carried out through laser positioning, a preset exposure program is started to copy a heating circuit pattern on a photomask on photoresist, and then the silicon single crystal substrate is placed in an environment of 120 ℃ for heat preservation for 1min for post-baking treatment;
s23, developing and hard baking: after the treatment in the step S22, spraying a developing solution on the surface of a silicon single crystal substrate rotating at a low speed of 300rmp through a plurality of nozzles for developing, and then placing the substrate in an environment of 120 ℃ for heat preservation for 1.5min for hard drying treatment to expose a heating circuit pattern;
s24, etching: after the treatment in the step S23, the silicon single crystal substrate is placed in an etching machine, and the introduced chlorine is ionized to carry out dry etching on the aluminum film, so as to remove the exposed redundant metal aluminum;
s25, photoresist removal: after the treatment in the step S24, removing redundant photoresist by acetone and isopropanol in sequence, and then cleaning and drying the silicon single crystal substrate by deionized water;
s26, checking: after the treatment in step S25, the quality of the heating circuit is checked by a microscope, so as to ensure that the heating area is not broken.
S3, etching a pore array window in a blank area beside the heating circuit by adopting a photoetching process according to the target chip to-be-damaged area, covering the target chip to-be-damaged area by the range of the pore array window, and etching the pore array window into a pore array by adopting a plasma dry etching process;
s31, gluing, whirl coating and soft baking: after the treatment in the step S26, placing the silicon single crystal substrate on a glue spreader, rotating at a low speed, dripping glue, accelerating to rotate to 3000rpm for spin coating, heating to 110 ℃ in vacuum, and preserving heat for 45S for soft baking treatment;
s32, exposing and post-baking: after the treatment in the step S31, placing the silicon single crystal substrate on a sample stage of an exposure machine, pre-aligning the silicon single crystal substrate through laser positioning, starting a preset exposure program to copy the pore path pattern on a photomask on a photoresist, and then placing the substrate in a 120 ℃ environment for heat preservation for 1min for post-baking treatment, wherein the pore path pattern is a square pore path array with the thickness of 10 multiplied by 10 mu m, the pore spacing is 50 mu m, and the array forms a window with the thickness of 5 multiplied by 5 mm;
s33, developing and hard baking: after the treatment in the step S32, spraying a developing solution on the surface of a silicon single crystal substrate rotating at a low speed of 300rmp through a multi-nozzle to develop, and then placing the substrate in an environment of 120 ℃ for heat preservation for 1.5min to carry out hard baking treatment to expose the pore channel patterns;
s34, etching: after the treatment of the step S33, the sample is placed in an ion etching machine, and the introduced C is introduced 2 F 6 Carrying out dry etching on the silicon dioxide protective layer and the silicon substrate by ionization of working gas to form a pore canal with the depth of 50 mu m;
s35, photoresist removal: after the treatment in the step S34, removing redundant photoresist by acetone and isopropanol in sequence, and then cleaning and drying the silicon single crystal substrate by deionized water;
s36, checking: after the treatment in the step S35, the etching quality of the pore canal is checked by a microscope, so that the pore canal meets the preset design;
s4, coating the back surface of the silicon single crystal substrate by adopting a dripping process to form an energy-containing material layer with the diameter of 4 mm and the thickness of 0.3mm, wherein the energy-containing material layer covers a heating area of the heating circuit and a part of pore channel array area;
and S5, connecting the photosensitive switch and the force-sensitive switch in parallel, connecting one end of the photosensitive switch and one end of the force-sensitive switch into an anode pad of the heating circuit through a gold wire, connecting the other end of the photosensitive switch and the anode of the power supply through the gold wire, connecting the cathode of the power supply with the cathode pad through the gold wire, and then packaging.
The embodiment mainly takes a silicon single crystal substrate as an example, and the self-destruction structure preparation method provided by the invention is explained in detail. When the circuit structure of the target chip needs to be prepared, the process may be performed after step S36, taking the MEMS structure of the target chip as an example: and preparing the MEMS structure of the target chip on the other side (namely the front side) of the silicon single crystal substrate by a conventional means, cutting the silicon single crystal substrate into single chips by adopting a laser scribing process, and then taking gold wires led out from the positive electrode bonding pad and the negative electrode bonding pad as the positive electrode and the negative electrode of the circuit of the target chip to jump to the relevant pins of the target chip.
The following describes the self-destruction principle and process of the two-stage excitation self-destruction chip based on the array pore canal provided in this embodiment as follows: when the package tube shell of the chip is subjected to unauthorized uncovering, the force-sensitive switch can sense the change of fastening force when the package body is uncovered to conduct the heating circuit, and meanwhile, the force-sensitive switch can sense the change of brightness inside the package body as a parallel triggering mechanism to conduct the heating circuit on the back of the target chip. After the heating circuit on the back of the target chip is loaded with current, a hot zone is formed locally and energetic materials are excited to cause explosion reaction, huge impact force is formed in the airtight packaging shell instantaneously, and irreparable crushing self-destruction damage is realized on the core electronic chip, so that the target chip is quickly and accurately destroyed, and core information is prevented from being stolen.
The self-destruction test was performed on the self-destruction chip provided in example 1, and the silicon single crystal substrate prepared with the self-destruction structure was connected to an existing printed circuit board and sealed and fixed by a steel sheet and a sealing ring to simulate the sealed state of the chip. The pressure switch and the photosensitive switch were turned on, and the results before and after the experiment are shown in fig. 4. As can be seen from the figure, after the current is applied, the chip is blasted and a shattering damage effect is formed.
In summary, the self-destruction structure provided by the invention is a structure which can be integrated with a core chip or a micro-electromechanical device (MEMS) and has a self-destruction function, is based on the design thought of physical destruction, adopts a secondary excitation structure design of weak current excitation-chemical explosion, and has the advantages that when a chip level is integrated with a trigger device and an explosion material and a preset trigger condition is met, the self-destruction program of the chip is activated, a heating circuit is conducted to release heat, the explosion reaction is caused by exciting an energetic material, the self-destruction damage which cannot be repaired is realized on a target chip, and the physical destruction through or in a smashing manner has irrecoverability, so that the damage effect is more thorough. The technology has the characteristics of high secrecy, microminiaturization, low power consumption, high controllability and the like, can realize the rapid self-destruction of the core chip during unauthorized dissection, and can effectively ensure the safety of important sensitive information and key chip technology. The explosion type self-destruction technology based on the energetic material has the advantages of safety, reliability, high technical maturity, small change to the original chip processing and wide application range, and is a self-destruction mode with high feasibility in the prior art.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (10)
1. A two-stage excitation self-destruction chip based on an array pore canal is characterized in that: comprises a basal layer and a self-destruction structure;
the basal layer is a target chip (5) to be destroyed;
the self-destruction structure is arranged on the back of the target chip (5) and comprises a heating circuit, a plurality of pore canals (4) and an energy-containing material layer (6), the pore canals are arranged in an array manner in a quasi-destruction area on the target chip (5), the energy-containing material layer (6) covers a heating area of the heating circuit and the pore canal array area, and the heating circuit is connected with an external control system or a power supply system;
the hole spacing of the hole array is 20-200 micrometers, the aperture width of the hole (4) is 10-100 micrometers, and the depth of the hole (4) is 20-200 micrometers.
2. The array-channel-based two-stage excitation self-destruction chip of claim 1, wherein: the self-destruction chip further comprises a photosensitive switch (7) and a force-sensitive switch (8), wherein the photosensitive switch (7) and the force-sensitive switch (8) are connected in parallel to a heating circuit and are connected with an external control system or a power supply system.
3. The array-channel-based two-stage excitation self-destruction chip of claim 1, wherein: the heating circuit comprises an electrode pad (1), two metal wires (2) and a heating wire (3), wherein the electrode pad (1) comprises an anode pad and a cathode pad, the anode pad and the cathode pad are respectively connected with one metal wire (2), the two end parts of the heating wire (3) are respectively connected with the two metal wires (2), the anode pad and the cathode pad are connected with an external control system or a power supply system, and the heating wire (3) is a heating zone of the heating circuit.
4. The array-channel-based two-stage excitation self-destruction chip of claim 3, wherein: the width of the heating wire (3) is 2-50 micrometers, the wire length is 500-50000 micrometers, the length-width ratio is 200-5000, and the wire thickness is 200-1000 nanometers.
5. The array-based two-stage excitation self-destruction chip according to any one of claims 1-4, wherein: the cross section of the pore canal (4) is round, rectangular or regular polygon.
6. A method for preparing the array pore canal-based two-stage excitation self-destruction chip as claimed in any one of claims 1 to 5, which is characterized in that: the method comprises the following steps:
s1, preparing an insulating layer on one surface of a substrate, and depositing a metal conducting layer on the surface of the insulating layer;
s2, etching the metal conductive layer into a heating circuit by adopting a photoetching process;
s3, etching a pore array beside the heating circuit on the substrate by adopting a photoetching process according to the to-be-damaged area, wherein the range of the pore array covers the to-be-damaged area of the target chip;
s4, coating an energy-containing material layer on the back surface of the substrate by adopting a pattern coating process, wherein the energy-containing material layer covers a heating area of the heating circuit and a pore channel array area;
and S5, connecting the heating circuit with an external control system or a power supply system.
7. The method for preparing the array pore canal-based two-stage excitation self-destruction chip as claimed in claim 6, wherein the method is characterized by comprising the following steps: in the step S5, a photosensitive switch and a force-sensitive switch connected in parallel are connected between an external control system or a power supply system and a heating circuit.
8. The method for preparing the array pore canal-based two-stage excitation self-destruction chip as claimed in claim 6, wherein the method is characterized by comprising the following steps: the step S1 specifically comprises the following steps:
s11, cleaning preparation: cleaning a substrate, and drying for later use;
s12, preparing an oxide film: after the treatment of the step S11, the substrate is placed in a thermal oxidation furnace, the oxidation furnace chamber is sealed and vacuumized to be lower than 10 -1 Pa, introducing oxygen, heating the furnace body to 1050-1150 ℃ according to a heating rate of 15-25 ℃/min, preserving heat for 10-20 minutes, cooling to below 400 ℃ according to a cooling rate of 15-25 ℃/min, and naturally cooling to room temperature to form a silicon dioxide oxide film, namely an insulating layer;
s13, coating: after the treatment of the step S12, the substrate is placed on a sample table of a coating machine, and is vacuumized to 10 -3 Pa or below, at 15-25cm 3 Argon is filled into the metal target material at the flow rate of/min to 0.2-0.8Pa, sputtering coating is carried out on the metal target material to form a metal film, namely a metal conductive layer, the coating time is 5-20min, and then the metal target material is naturally cooled to room temperature.
9. The method for preparing the array pore canal-based two-stage excitation self-destruction chip as claimed in claim 8, wherein the method is characterized by comprising the following steps: the step S2 specifically includes the following steps:
s21, gluing, whirl coating and soft baking: placing the coated substrate on a gumming machine, dripping the coating, then throwing the coating, heating to 100-120 ℃ in vacuum, and preserving the temperature for 30-60s for soft baking;
s22, exposing and post-baking: after the treatment in the step S21, placing the substrate on a sample stage of an exposure machine, copying a heating circuit diagram on photoresist, and then placing the substrate in an environment of 110-130 ℃ for heat preservation for 1-3min for post-baking treatment;
s23, developing and hard baking: after the treatment in the step S22, spraying the developing solution on the surface of the substrate for developing, then placing the substrate in an environment of 110-130 ℃ for heat preservation for 1-3min for hard drying treatment, and exposing the heating circuit pattern;
s24, etching: after the treatment in the step S23, placing the substrate in an etching machine, introducing chlorine as working gas to ionize and dry etch the aluminum film, and removing the redundant metal film;
s25, photoresist removal: after the treatment in step S24, the excess photoresist is removed sequentially with acetone and isopropyl alcohol, and then the substrate is rinsed with deionized water and baked.
10. The method for preparing the array pore canal-based two-stage excitation self-destruction chip as claimed in claim 9, wherein the method is characterized by comprising the following steps: the step S3 specifically comprises the following steps:
s31, gluing, whirl coating and soft baking: after the treatment in the step S25, placing the substrate on a glue spreader, dripping glue, then throwing the glue, heating to 100-120 ℃ in vacuum, and preserving heat for 30-60S for soft baking treatment;
s32, exposing and post-baking: after the treatment in the step S31, placing the substrate on a sample stage of an exposure machine, copying the pore channel pattern on photoresist, and then placing the substrate in an environment of 110-130 ℃ for heat preservation for 1-3min for post-baking treatment;
s33, developing and hard baking: after the treatment in the step S32, spraying the developing solution on the surface of the substrate for developing, and then placing the substrate in an environment of 110-130 ℃ for heat preservation for 1-3min for hard drying treatment to expose the pore channel patterns;
s34, etching: after the treatment of the step S33, the substrate is placed in an etching machine and C is introduced 2 F 6 As working gas ionization, carrying out dry etching on the silicon dioxide oxide film and the silicon substrate to form a pore canal with a set depth;
s35, photoresist removal: after the treatment in step S34, the excess photoresist is removed sequentially with acetone and isopropyl alcohol, and then the substrate is rinsed with deionized water and baked.
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| US8425704B2 (en) * | 2009-08-04 | 2013-04-23 | The United States Of America As Represented By The Secretary Of The Army | Silicon-based explosive devices and methods of manufacture |
| US9842812B2 (en) * | 2014-03-24 | 2017-12-12 | Honeywell International Inc. | Self-destructing chip |
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