CN1127846C - Device capable of uniformly magnifying and contracting image size - Google Patents
Device capable of uniformly magnifying and contracting image size Download PDFInfo
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- CN1127846C CN1127846C CN 00106548 CN00106548A CN1127846C CN 1127846 C CN1127846 C CN 1127846C CN 00106548 CN00106548 CN 00106548 CN 00106548 A CN00106548 A CN 00106548A CN 1127846 C CN1127846 C CN 1127846C
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Abstract
The present invention relates to a device for uniformly stretching and contracting the size of a digital image. An original digital image has N continuous original image data, and a target digital image has M continuous target digital image data. M is larger than N, and a residual interpolation image datum is generated in the linear interpolation of the n-th original image datum and the (n+1)-th original image datum. A quotient S of (M-N)/(N-1) is obtained, and when n is the minimum value of n+1*S>=s*N, the interpolation image datum is inserted between the n-th original image datum and the (n+1)-th original image datum. When M is smaller than N, an address generator can control a memory unit to output a selective original image datum. A subsequent original image datum output by the memory unit offsets a numerical value V or V+1 at a previous original image datum output by the memory unit, and V is the quotient of N/M.
Description
Patent application of the present invention is for dividing an application, and original applying number is 96106993.7, and original application day is on July 31st, 1996, and the name of former application for a patent for invention is called " the evenly device of flexible digital image size ".
Technical field
The present invention relates to a kind of image processing apparatus, particularly relate to the device of the evenly flexible Digital Image Processing size of the instant two dimension of a kind of energy.
Background technology
In the application of multimedia computer, it is very important having the ability of integrating digital picture, before a digital picture (DIGITAL IMAGE) and the integration of another digital picture, essential this digital picture is handled earlier, and the method for handling is normally waited to another zone by a chosen part that increases this digital image size (hereinafter referred to as stretching (SCALING UP)), reduces this digital image size (hereinafter referred to as compression (SCALING DOWN)), a chosen part of cutting out this digital picture, this digital picture of translation and finishes.
The stretching, extension of above-mentioned digital picture and compression are to be finished by specially designed computer, this digital picture comprises most scan lines, each scan line also includes a plurality of pixel datas (PIXEL DATA), and the stretching, extension of this digital picture is by carry out linear interpolation (LINEAR INTERPOLATION) between per two scan lines, and obtain at least one interpolation scan line between two scan lines, and by between per two scanning elements, carrying out linear interpolation, and obtain at least one the inter polated pixel data between two scanning elements.The compression of digital picture then is to be reached by the part of scanning line of deletion digital picture and the partial pixel data of deleting each scan line that is retained.
For the stretching, extension of digital picture, the linear interpolation that relies on computer to handle raw image data is quite slow, therefore, develops the hardware unit of the special use of all kinds of stretching digital picture.
These special-purpose hardware unit great majority can only stretch the limited area of digital picture to.When stretching, extension one has the digital picture of N bar scan line, the sum of the scan line that is inserted into must be the integral multiple of N-1, has similar number with the interpolation scan line between per two scan lines that allow to be inserted in this original scan line, make the image after stretching still can keep evenly, in the same manner, also be the same ground when stretching, extension one has the individual pixel data of N '.
The flexible special pattern processor that can rely on the variable expansion of a carries out image and dwindle of the two dimension of general digital picture uses, or relies on use one hardware unit that can reach the special use of equifinality to reach.Earlier this original image is stored in the frame memory, this original image is stretched in one first dimension (first dimension) then, and the flexible image of final one dimension system is stored in this frame memory.In one second dimension, stretched then by flexible image, and the flexible image of final two dimension as a computer monitor or printer, was stored in this frame memory before being provided to an output device.General telescopic method does not meet economic benefit because the sizable memory of their demands, when especially using big magnification.In addition, general telescopic method uses a large amount of treatment steps, therefore has the efficient of being on duty mutually, because the flexible image of this one dimension can must be stored in this frame memory before flexible in this second dimension, and because the flexible image of this two dimension must be stored in this frame memory before can being provided to this output device, therefore, general telescopic method is not adapted at using in the live video application.
Summary of the invention
The present invention's first purpose is to provide the device of the evenly flexible digital picture of the instant two dimension of a kind of energy.
The present invention's second purpose is to provide a kind of and is adapted at using in the live video application, cost is low and high efficiency retractor device.
The invention provides a kind of device, can handle an original digital image, to obtain an evenly flexible purpose digital picture, this device comprises one in order to store this original digital image frame memory within it, this original digital image has the continuous original scan line of some (N) bar and the individual continuous raw pixel data of every original scan line some (N '), this device also comprise one in order in flexible this original digital image of vertical direction obtaining the vertical telescopic unit of the continuous purpose scan line of majority (M) bar, and one in order in the horizontal direction flexible from this vertical telescopic unit purpose scan line to obtain the horizontal telescopic unit of the individual continuous purpose pixel data of every scan line some (M ').
When this numerical value (M) is bigger than this numerical value (N), in order to make this vertical telescopic unit this original digital image of stretching, this vertical telescopic unit comprises: a line storage, and this line storage is connected to this frame memory, to store the original scan line of (n+1) bar from this frame memory; One line buffer is connected to this line storage, to store the original scan line of (n) bar; One first linear interpolation is connected to this line storage and this line buffer; And a vertical expansion controller, be connected to this frame memory, this line buffer and this first linear interpolation.This vertical expansion controller is controlled the storage of this original scan line in this line storage and this line buffer, and also control this first linear interpolation and carry out (n) and the linear interpolation of the original scan line of (n+1) bar from this line storage and this line buffer, to produce a remaining inserting scan lines, when obtaining remainder (S) divided by (N-1), (M-N) reach when (n) is the minimum value of satisfy condition (n+1) * (S) 〉=(s) * (N), wherein (s) is positioned at 1 to (S), and this remnants inserting scan lines is inserted between this (n) and the original scan line of (n+1) bar.
For make this vertical telescopic unit at this numerical value (M) than flexible this original digital image of this numerical value (N) hour, this vertical expansion controller comprises:
One first address generator, be connected to this frame memory, control this frame memory to export the article one in this original scan line, for being stored in this line storage, in order to produce first generation device of a numerical value (U), this numerical value is a remainder that is drawn divided by numerical value (M) by numerical value (N);
One first data register;
A first adder device is connected to this first generation device and this first data register, and numerical value and this numerical value (U) addition that is stored in this first data register obtained one and number;
One first calculation element, be connected to this first adder device, this first address generator and this first data register, can with should and the number and this numerical value (M) compare, and make this first address generator control this frame memory, export in this original scan line another, to be stored in this line storage, in this original scan line another, when this and number during less than numerical value (M), from original offset of scan lines one numerical value of being exported by this block diagram memory (V) formerly, and when should and number at least with this numerical value (M) when equating, by original offset of scan lines one numerical value (V+1) formerly that this frame memory is exported, this numerical value (V) equals (N) quotient divided by (M) gained.When this and number at least with this numerical value (M) when equating, this first calculation element in this first data register, store should and number and this numerical value (M) poor, and when should and number than this numerical value (M) hour, this first calculation element stores in this first data register and is somebody's turn to do and counts.
When this numerical value (M ') was bigger than this numerical value (N '), in order to make the flexible purpose scan line from this vertical telescopic unit of this horizontal telescopic unit, this horizontal telescopic unit comprised:
A point register is connected to this first linear interpolation, to store the individual pixel data of the (n '+1) from this scan line of this first linear interpolation;
A point buffer is connected to this register, to store this individual pixel data of (n ') in these scan lines;
One second linear interpolation is connected to this subsides register and this buffer;
A horizontal expansion controller is connected to this line storage, this line buffer, this buffer and this second linear interpolation.
This horizontal expansion controller is controlled the storage of this pixel data in this register and this buffer, and also control this second linear interpolation to carry out linear interpolation from the individual pixel data of this register and this buffer this (n ') and the (n '+1), to produce remaining interpolated pixel data, obtain remainder (S ') divided by (N '-1) and one satisfy condition when (n ') is (n '+1) as (M '-N ') * (S ') 〉=(s ') * during the minimum value of (N '), wherein (s ') is positioned at 1 to (S '), and these remnants interpolated pixel data are inserted between this (n ') and (n '+1) original scan line of bar.
When this numerical value (M ') than this numerical value (N ') hour, in order to make the flexible purpose scan line from this vertical telescopic unit of this horizontal telescopic unit, this horizontal telescopic unit comprises:
One second address generator, be connected to this line storage, control this line storage, to export in this scan line first raw pixel data of one, in order to producing second generation device of a numerical value (U '), this numerical value is a remainder that is drawn divided by numerical value (M ') by numerical value (N ');
One second data register;
A second adder device is connected to this second generation device and this second data register, is obtained one and several mutually with being stored in numerical value in this second data register and this numerical value (U ');
One second calculation element, be connected to this second adder device, this second address generator and this second data register, with should and number and this numerical value (M ') compare, and make this second address generator control this line storage to export another raw pixel data of aforementioned scan line, when this and number during less than numerical value (M '), another raw pixel data of this of this scan line, be to be offset a numerical value (V ') from the raw pixel data of exporting by this line storage formerly, and when should and number at least with this numerical value (M ') when equating, be to be offset a numerical value (V '+1) from the raw pixel data of being exported by this line storage formerly, this numerical value (V ') equals (N ') quotient divided by (M ') gained.When this and number at least with this numerical value (M ') when equating, in this second data register, this second calculation element store should and number and this numerical value (M ') poor, and when should and number than this numerical value (M ') hour, this second calculation element stores and should and count in this second data register.
The output of second linear interpolation of this horizontal telescopic unit can directly be provided for an output device.
Description of drawings
The present invention is described in detail below in conjunction with drawings and Examples:
Fig. 1 is the diagrammatic block circuit diagram of the most preferred embodiment of retractor device of the present invention.
Fig. 2 is a bilinearity adder diagrammatic block circuit diagram in the above-mentioned most preferred embodiment.
Fig. 3 is the diagrammatic block circuit diagram of vertical expansion controller in the above-mentioned most preferred embodiment.
Fig. 4 is the diagrammatic block circuit diagram of the remaining distributor of above-mentioned vertical expansion controller.
Fig. 5 is the diagrammatic block circuit diagram of the α tandem generator of above-mentioned vertical expansion controller.
Fig. 6 is the diagrammatic block circuit diagram of the address generator of above-mentioned vertical expansion controller.
Fig. 7 is the sequential chart of the vertical stretching operation of vertical telescopic unit when N=5 and Δ N=2 of above-mentioned most preferred embodiment.
Fig. 8 is the sequential chart of the vertical stretching operation of above-mentioned vertical telescopic unit when N=5 and Δ N=6.
Fig. 9 is the sequential chart of the vertical compression operation of above-mentioned vertical telescopic unit when N=5 and Δ N=2.
Figure 10 is the sequential chart of the horizontal stretching operation of horizontal telescopic unit when N '=5 and Δ N '=2 of most preferred embodiment.
The sequential chart of the level compression operation that Figure 11 is above-mentioned horizontal telescopic unit when N '=5 and Δ N '=2.
Embodiment
As shown in Figure 1, the most preferred embodiment of the device of evenly flexible digital image size of the present invention comprises a vertical telescopic unit and a horizontal telescopic unit.This vertical telescopic unit can stretch or compress a DID in vertical direction, and includes a line storage 3, line buffer 4,5 and vertical expansion controllers 6 of bilinearity adder (BILINEAR ADDER); This horizontal telescopic unit can stretch or compress a DID in the horizontal direction, and includes a some register 7, some buffer 8, a bilinearity adder 9 and a horizontal expansion controller 10.
During use, by the handled digital picture of device of the present invention is to be stored in the frame memory (FRAME MEMORY) 2 at first, and this digital picture can be from an image decoder or from a source of digital image data 1 such as image capture system.These vertical expansion controller 6 these frame memories 2 of control, the selected scan line that this digital picture is provided is to this line storage 3, these vertical expansion controller 6 these line buffers 4 of control, storage is from the last scan line in this line storage 3, this bilinearity adder 5 receives from the scan-line data of this line storage 3 and this line buffer 4 and according to a pair of weight coefficient α, 1-α from this vertical expansion controller 6, carries out bilinear interpolation.
The output of this bilinearity adder 5 is to be received by this register 7, and these horizontal expansion controller 10 control these buffers 8 are to store one from the pixel data before this register 7.This bilinearity adder 9 receives pixel data from this register 7 and this buffer 8, and carries out bilinear interpolation according to a pair of weight coefficient α, the 1-α from this horizontal expansion controller 10.
Shown in Figure 2 is the circuit block diagram of this bilinearity adder 5, be multiplied by this coefficient 1-α from this line buffer 4 and with the n bar scan line corresponding scanning line data of the digital picture that is stored in this frame memory 2 through a register 501 and a multiplier 502, and be multiplied by factor alpha through a register 503 and a multiplier 504 from this line storage 3 and with the n+1 bar scan line corresponding scanning line data of the digital picture that is stored in this frame memory 2.When this factor alpha is mark (just α is not equal to 1 and also is not equal to 0), the above product that obtains through an adder 505 additions, is then obtained an interpolation scan line.The operation of this bilinearity adder 5 will be described in detail hereinafter.
As shown in Figure 3, this vertical expansion controller 6 includes a programmable registers group 30, one first counting circuit 31, one second counting circuit 32, one the 3rd counting circuit 33, selector 34, remaining distributor 35, a α tandem generator 36 and an address generator 37.
This registers group 30 includes one first register 301, one second register 302 and one the 3rd register 303, this first register 301 is the original scan-line data N that are used for being stored in the digital picture in this frame memory 2, this second register 302 is to be inserted into or deleted amount of scanning beam Δ N in order to storage, and the 3rd register 303 is to identify 38 in order to store an INC/DEC, and above-mentioned INC/DEC sign 38 is to be used to indicate stretching, extension or compression at this DID of vertical direction to be performed.This first counting circuit 31, second counting circuit 32 and the 3rd counting circuit 33 read the content that is stored in this first register 301, second register 302 and the 3rd register 303 respectively, and this first counting circuit 31 is exported Δ N divided by the resulting quotient T of N-1, and this second counting circuit 32 output Δ N are divided by the resulting remainder S of N-1.Therefore, when this digital picture is being done when stretch handling, this quotient T is equivalent to be inserted into the minimum number of the interpolation scan line between per two adjacent scanning lines of this digital picture, and this remainder S is equivalent to be evenly distributed on the sum of the remaining interpolation scan line between the original scan line of this digitized video.The 3rd counting circuit 33 output N are divided by the remainder U of N-Δ N, and when this digital picture was compressed, this remainder U was equivalent to the sum of deleted remaining scan line.
This selector 34 comprises that a reception is from the first input end of the 3rd counting circuit 33 remainder U and reception second input from this second counting circuit 32 remainder S, and this selector 34 comprises a control input end, this control input end receives the INC/DEC sign 38 from the 3rd register 303, and the output 42 of this selector 34 is connected with this remnants distributor 35, and this remnants distributor 35 also receives from the quotient T of this first counting circuit 31 and includes control input end and the control output end 39 that with this α tandem generator 36 and this address generator 37 link to each other of a reception from the INC/DEC sign 38 of the 3rd register 303.When these remnants distributor 35 decisions are carried out remaining interpolation step, and during digital picture is done the compression processing, when are deleted a remaining scan line during this digital picture is done the stretching, extension processing.This α tandem generator 36 receives from the quotient T of this first counting circuit 31 and from the INC/DEC sign 38 of the 3rd register 30c, and produces a save command signal (as Fig. 1) of factor alpha, 1-α and this line buffer 4 of this bilinearity adder.This address generator 37 equally also receives from the 1VC/DEC sign 38 of the 3rd register 303 and provides the line address date to this frame memory 2.
As shown in Figure 4, this remnants distributor 35 comprises the selector 45 of the selector 41 of a counting circuit 40, a dual input, intermediate data register 56, two input adder 43, counting circuit 44, a dual input, a clock modulation circuit 46 and a selector 47.
These counting circuit 40 output N and Δ N differences.This selector 41 has a first input end, that receives these counting circuit 40 outputs and receives second input and from the numerical value of N of first register 301 and receive control input end from the INC/DEC sign 38 of the 3rd register 303.This intermediate data register 56 receives the output 42 (as Fig. 3) of this selector 34 and has an output that is connected to an input of this two-input adder 43.Another input of this adder 43 then receives the output 42 of this selector 34, the output of the output of this adder 43 and this selector 41 is as the input of a counting circuit 44, this counting circuit 44 is the output of the output of this adder 43 being deducted this selector 41, when the output of this adder 43 during more than or equal to the output of this selector 41, this counting circuit 44 produces an enable signal in its control output end 39.This dual input selector 45 comprises that one receives first input end, second input, a control input end that is connected with the control output end 39 of this counting circuit 44 and an output that is connected with this intermediate data register 56 that receives from this adder 43 with the output difference of this selector 41 of this counting circuit 44 of this adder 43.
This clock modulation circuit 46 receives these original incoming line clocks and according to the signal of this control output end 39 and from this original incoming line clock of quotient T modulation of this first counting circuit 31.This original incoming line clock can reading scan line clock, this vertical scanning operation can be output, for being presented at just like on the output device on printer or the computer monitor at this raw image data.When this control output end 39 during at high logic state, these clock modulation circuit 46 outputs one are divided by the T+2 clock, and should have the T+2 time delay doubly of this original incoming line clock divided by the T+2 clock, and when this control output end 39 during at low logical bit state, this clock modulation circuit 46 exports one divided by the T+1 clock, and should have the T+1 time delay doubly of this original incoming line clock divided by the T+1 clock.In addition, the output of this clock modulation circuit 46 and this original incoming line clock are connected with the input of this selector 47, then are used as the control input of this selector 47 from the INC/DEC sign 38 of the 3rd register 30C.This intermediate data register 56 comprises a load end LD, and this load end LD receives the clock signal mClock1 from these selector 47 outputs.
As shown in Figure 5, this α tandem generator 36 comprises a coefficient producer 363, a selector 364 and a subtraction circuit 365.This coefficient producer 363 is connected with the control output end 39 of this counting circuit 44 and receives this original incoming line clock and from the quotient T of this first counting circuit 31.When this control output end 39 during at high logical bit state, this coefficient producer 363 continuous (T+2) individual original incoming line produce respectively in the clock cycle continuous side reaction coefficient 1,1/ (T+2), 2/ (T+2) ..., (T+1)/(T+2).When this control output end 39 during at low logical bit state, this coefficient producer 363 continuous (T+1) individual original incoming line produce respectively in the clock cycle continuous side reaction coefficient 1,1/ (T+1), 2/ (T+1) ..., T/ (T+1).This selector 364 comprises that one is fixed to the control input end that second input and that 1 first input end, receives the output of this coefficient producer 363 receives this INC/DEC sign 38, and output factor α imports as one of this subtraction circuit 365, and another input of this subtraction circuit 365 then is fixed to 1.One output output factor 1-α of this subtraction circuit 365, another output is then exported the save command signal of this line buffer 4 (as Fig. 1).And when this coefficient 1-α equals 0 (α=1), this subtraction circuit 365 produces this save command signal.
As shown in Figure 6, this address generator 37 comprises a counting circuit 371, an adder 372, a selector 373, an adder 374, an address register 375, a latch cicuit 376, a clock modulation circuit 377 and a selector 378.
This counting circuit 371 output N are divided by the resulting quotient V of N-Δ N, this quotient V is equivalent to when this DID is compressed, difference at two selected scan lines of the digital picture of this frame memory 2, this quotient V and this control output 39 inputs as this adder 372, the output of this adder 372 is then as an input of this selector 373, another input of this selector 373 then is fixed to 1, and this INC/DEC sign 38 is then as a control input end of this selector 373.The difference that this selector 373 is produced then is delivered to this adder 374.The output of this adder 374 is connected to this address register 375, the output of this address register 375 is connected to this adder 374 again, this address register 375 has an initial input Start, in order to set article one scan line address in this frame memory 2, and this address register 375 has more a load end LD, in order to the renewal of control next address.
This latch cicuit 376 is sampling is done in this control output end 39 and to keep according to this original incoming line clock, and this clock modulation circuit 377 receives these original incoming line clocks and according to the output of this latch cicuit 376 and from this original incoming line clock of quotient T modulation of this first counting circuit 31.The output of this latch cicuit 376 is when high-order logic state, these clock modulation circuit 377 outputs one are divided by T+2 time delay doubly, when the output of this latch cicuit 376 during at low logical bit state, this clock modulation circuit 377 exports one divided by the T+1 clock, and should have the T+1 time delay doubly of this original incoming line clock divided by the T+1 clock.This selector 378 receives the output of this original incoming line clock and this clock modulation circuit 377, selects clock output mClock2 by this INC/DEC sign 38, and this clock output mClock2 is then received by the load end LD of this address register 375.
The structure of this horizontal expansion controller 10 is with similar at the structure of the vertical expansion controller 6 shown in Fig. 3～6.Inessential difference between this two controller 6,10 exists.For example, in this horizontal expansion controller 10, first register of this programmable register group is the individual pixel data of N ' that is used for being stored in the digital picture of every original scan line in this frame memory 2, and this second register is the individual pixel data of Δ N ' that will be interpolated or delete that is used for storing every scan line.The 3rd register stores INC/DEC sign, and whether this sign is used to refer in the stretching, extension of the digital picture of a horizontal direction or compression and will be performed.This first counting circuit produces corresponding to the quotient T ' that will be inserted in from the interpolated pixel data of the minimal amount between per two pixel datas of the scan-line data of this bilinearity adder 5.When this digital picture was stretched, this second counting circuit produced corresponding to the remainder S ' that will be evenly distributed on from the sum of the remaining interpolated pixel data between the pixel data of the scan-line data of this bilinearity adder 5.When this digital picture was compressed, the 3rd counting circuit produced corresponding to will be from the remainder U ' from the sum of the residual pixels data of the scan-line data deletion of this bilinearity adder 5.Replace a memory command signal, the α tandem generator of this horizontal expansion controller 10 produces a latches command signal to this buffer 8.Inputing to this address generator, this α tandem generator and clock that should the remnants distributor is the original pixels clock.This original pixels clock can be the display dot clock, so that this horizontal stretching operation can be output at this raw image data, for being presented on this output device.The address output of the address register of this horizontal expansion controller 10 is dot addresses that are used to control this line storage 3 and this line buffer 4.Therefore, between extensin period in the horizontal direction, all pixel datas between n and original scan line of n+1 bar and inserting scan lines, if any, as long as by this bilinearity adder.When compression, has only the selected pixel data of a selected original scan line by this bilinearity adder 5 in vertical and horizontal direction.
Therefore, present embodiment can be used to carry out simultaneously stretching, extension or compression and stretching, extension in the horizontal direction or the compression in vertical direction.Move as described below:
A. the explanation of the vertical stretching of most preferred embodiment operation for convenience provides one to have original digital image that five original scan lines and every scan line have five pixel datas and obtained one by stretching, extension and have the scan line of seven clauses and subclauses and the example that every scan line has the purpose digital picture of five pixel datas.
As shown in Figure 3, the programmable registers group 30 of this vertical expansion controller 6 be set in this first register 301 store digital " 5 " at first, store digital " 2 " and in the 3rd register 303, store a logical one in this second register 302; This numeral " 5 " is equivalent to the original scan line quantity N at this raw image data of this frame memory 2, the scan line sum Δ N that this numeral " 2 " is equivalent to be inserted into then indicates this DID will be performed in the stretching, extension of this vertical direction at this logical one of the 3rd register 303.Then, the planning registers group able to programme of this horizontal expansion controller 10 is programmed, point out that five pixel datas are arranged in every original scan line, do not have pixel data to be interpolated every original scan line, and the stretching, extension in the horizontal direction of this original digital image to be performed.This first counting circuit 31 output Δ N are divided by the resulting quotient T of N-1, because Δ N is less than N-1, so this quotient T equals 0.This second counting circuit 32 output Δ N are divided by the resulting remainder S of N-1, and in this example, this remainder S equals 2.33 of the 3rd counting circuits are incoherent, because stretching operating period, this selector 34 provides this remnants distributor 35 of exporting to of this second counting circuit 32, first, second of this horizontal expansion controller 10 and the 3rd counting circuit are output as 0, because do not have horizontal stretching or compression operation to be performed.
As Fig. 1,3, shown in 7, the address register 375 initial line addresses of setting the first original scan line of this original scan line that is stored in this frame memory 2 of this address generator 37, and controlling this frame memory 2 provides the first original scan line of this original scan line to this line storage 3, simultaneously, this intermediate data register 56 deposits this remainder S in, then this adder 43 is again with the content addition of this remainder S and this intermediate data register 56, because this adder 43 is output as 4 and less than N (N equals 5), therefore the control output end 39 of this counting circuit 44 is at low logical bit state, this selector 45 offers this intermediate data register 56 with the output of this adder 43 and the clock input mClock1 of this intermediate data register 56 is provided is a clock divided by T+1, because this quotient T equals 0, so this clock input mClock1 is identical with this original incoming line clock just.
Because this control output end 39 is at low logic state and because this quotient T equals 0, so this coefficient producer 363 provides this numeral " 1 " to give this selector 364, because this INC/DEC sign 38 is at logical one, this selector 364 selects the output of this coefficient producer 363 to be used as weight coefficient α, because this factor alpha equals 1, therefore this coefficient 1-α equals 0, and produce this save command signal, with the first original scan line that this line buffer 4 of convenient control stores from this original scan line of this line storage 3, this bilinearity adder 5 is output as the first original scan line of this original scan line in this stage.
This selector 373 provides one to equal 1 difference to this adder 374, therefore, when next line clock mClock2 arrives, this adder 374 can make the output of this address register 375 increase a unit, control this frame memory 2 by this, the second scan line that this original scan line is provided is to this line storage 3.
When next line clock mClock1 arrives, this intermediate data register 56 stores the previous output (equaling 4) of this adder 43, at this moment, the output of this adder 43 (equaling 6) is greater than N (equaling 5), the control output end 39 that makes this counting circuit 44 is at high logic state, this selector 45 provides the difference of output of the output of this adder 43 and this selector 41 to this intermediate data register, and this clock input mClock1, equal the clock divided by T+2 this moment, has the time of delay of this original incoming line clock twice.
This control output end 39 is at high logic state, and this coefficient producer 363 produces two continuous outputs 1 and 1/2 during a clock mClock (promptly two continuous original incoming line clock).In this first original incoming line clock period, because of this factor alpha equals 1, so second original scan line of these bilinearity adder 5 these original scan lines of output, simultaneously this second original scan line is stored in this line buffer 4, at this second original incoming line clock period, the content of this address register 375 is increased a unit when next clock is imported mClock2, this moment, the output of this coefficient producer 363 equaled 1/2, this factor alpha equals 1/2, this coefficient 1-α equals 1/2, so the command signal generation is not recommended in storage.Therefore, the second original scan line of this original scan line is retained in this line buffer 4, and this bilinearity adder 5 is output as the second original scan line of this original scan line and the bilinear interpolation of the 3rd original scan line in this stage.
The content of this intermediate data register 56 is updated to 1 when next clock input mClock1 arrives, just the difference of this adder 43 and this numeral N.The output of this adder 43 is less than N, make this control output end 39 at low logic state, this selector 45 provides this intermediate data register 56 of exporting to of this adder 43, and the clock input mClock1 that offers this intermediate data register 56 is for divided by the T+1 clock, and equals 1 from the factor alpha of this α tandem generator 36.This bilinearity adder 5 is output as the 3rd original scan line of these original scan lines, and because this factor alpha equals 1, therefore the 3rd original scan line of this original scan line is stored in this line buffer 4.
The follow-up operation of this vertical telescopic unit is to above-mentioned similar till the 5th original scan line is by these bilinearity adder 5 outputs.
Fig. 7 is the time sequential routine figure of above-mentioned most preferred embodiment, wherein N=5 and Δ N=2.
According to the above, these vertical expansion controller 6 these bilinearity adders 5 of control, carry out the n bar of this original scan line and the bilinear interpolation of n+1 bar scan line, wherein this n bar scan line is stored in this line buffer 4, and this n+1 bar scan line is stored in this line storage 3, obtain under a remainder S and the condition of (n+1) * (S) 〉=(s) * (N) of working as divided by N-1 with the convenient Δ N of working as, n is for hour, make one and be inserted in the n bar of this original scan line and the remaining interpolation scan line between the original scan line of n+1 bar, wherein the scope of s is to S from 1.
As shown in Figure 1, owing to there is not the flexible operation of level to be performed, this horizontal this line storage 3 of expansion controller 10 controls and this line buffer 4 provide the pixel data that is stored in it to this bilinearity adder 5 in regular turn.Received by this register 7 from the original of this bilinearity adder 5 and interpolated pixel data, this register 7 provides these original and interpolated pixel data to this bilinearity adder 9 successively.At this moment, this factor alpha often equals 1, and the output of this buffer 8 is ignored by this bilinearity adder 9.The output of this bilinearity adder 9 equates with the output of this bilinearity adder 5 and can directly be provided to this output device (figure does not show).
In this example, N is 0 divided by the resultant quotient T of N-1.If this quotient T is not equal to 0, just Δ N is more than or equal to N-1, this vertical expansion controller 6 is also controlled this bilinearity adder 5 and is carried out the n bar of this original scan line and the bilinear interpolation of the original scan line of n+1 bar, inserts between the n bar and the original scan line of n+1 bar of this original scan line to make T additional continuous interpolation scan line.Fig. 8 is the sequential chart that is moved by the performed sampling vertical stretching of this most preferred embodiment when N=5 and Δ N=6.In this example, this quotient equals 1, and this remainder equals 2, clearly, except two remaining interpolation scan lines, an additional inserting scan lines is arranged all between per two adjacent scanning lines of this original scan line.
B. in following example, be one to have five original scan lines and every scan line has the original digital image of five pixel datas to be compressed, can obtain one and have the scan line of three clauses and subclauses and the purpose digital picture that every scan line has five pixel datas.
As shown in Figure 3, the registers group 30 of this programming be set in this first register 301 numerical value storage " 5 ", numerical value storage " 2 " and in the 3rd register 303, store a logical zero in this second register 302.This numerical value " 5 " is equivalent to the original scan line quantity N of this raw image data in this frame memory 2, and this numerical value " 2 " is equivalent to deleted scan line sum Δ N, in this logic of the 3rd register 303.Then indicate the execution squeeze operation of this DID.Then the planning registers group able to programme of this horizontal expansion controller 10 be programmed point out in every original scan line be five pixel datas are arranged, do not have pixel data to be interpolated in every original scan line, and original digital image stretching, extension in the horizontal direction be to be performed.
In the time of during the squeeze operation, the output of this first and second counting circuit 31,32 is incoherent, and the 3rd counting circuit 33 output N are divided by the resulting remainder U of N-Δ N, and wherein N-Δ N is the number that is retained this original scan line, in the present embodiment, this remainder U equals 2.This selector 34 provides this remnants distributor 35 of exporting to of the 3rd counting circuit 33.
As Fig. 1,3,6, shown in 9, the address register 375 of this address generator 37 is set the line address of the first original scan line that is stored in this original scan line in this frame memory 2 at first, and open the initial line clock period one and control this frame memory 2 and provide the first original scan line of this original scan line to this line storage 3, simultaneously, this remainder U is stored in this intermediate data register 56, then this adder 43 is again with the content addition of this quotient and this intermediate data register 56, this counting circuit 44 will deduct the numerical value of N-Δ N from this selector 41 from the output of this adder 43, because the output of this adder 43 ' equals 4 and greater than N-Δ N (equaling 3) at this moment, so the control output end 39 of this counting circuit 44 is in high logic state.This selector 45 provides difference between the output of the output of this adder 43 and this selector 41 to this intermediate data register 56, and this original line clock is supplied to this intermediate data register 56 by this selector 47.
Shown in Fig. 3,5, because a logical zero is stored in the 3rd register 303, therefore to keep this factor alpha be 1 to this selector 364, and therefore coefficient 1-α equals 0, thereby this save command signal is produced always, so that this line buffer 4 of start stores an original scan line by this line storage 3 constantly, in addition, the output of this bilinearity adder 5 is the output of this line storage 3 always.
As shown in Figure 6, this counting circuit 371 output N are divided by the resulting quotient V of N-Δ N, in this example, this quotient V equals 1, the instant logic state of this adder 372 generation this quotient V and this control output end 39 and several, the logic state of this moment is a high logic state, this selector 373 is selected the output (equaling 2) of this adder 372, and provide identical this adder 374 of exporting to, therefore, the output of this address register 375 increases by two units when next clock input mClock2 arrives, control this frame memory 2 by this, and the 3rd original scan line that these original scan lines are provided is to this line storage 3.
As shown in Figure 4, arrive up to next line clock, this intermediate data register 56 stores the last difference " 1 " that is calculated by this counting circuit 44, at this moment, the output of this adder 43 (equaling 3) equals the output of this selector 41, the control output end 39 of this counting circuit 44 is at high logic state, and this selector 45 provides difference between the output of the output of this adder 43 and this selector 41 to this intermediate data register 56.
As shown in Figure 6, this adder 372 produce again this quotient V and this control output end 39 instant logic state and the number; The output of this adder 372 (equaling 2) is provided to this adder 374 by this selector 373, therefore, when the output of this address register 375 arrives at the mClock2 of clock input instantly, to be increased two units again, controlling this frame memory 2 by this provides the Wuyuan beginning scan line of this original scan line to this line storage 3.Fig. 9 is the sequential chart with this most preferred embodiment vertical compression operation, just N=5 and Δ N=2.With regard to this example, therefore the operation of horizontal telescopic unit is no longer heavily covered with above-mentioned identical.
From the above, the selecteed scan line in this original scan line of 2 output of address generator 37 these frame memories of control of this vertical expansion controller 6.And this original scan line that is not output in this frame memory 2 in fact is abandoned, and, when the output of the adder 43 of this remnants distributor 35 during less than this difference N-Δ N, is V by the original scan line that is output in this frame memory 2 with difference by the original scan line of this frame memory 2 outputs, when the output of adder 43 equals this difference N-Δ N at least, be V+1 with difference value by the original scan line of this frame memory 2 outputs by the original scan line that is output in this frame memory 2.
C. in the horizontal stretching operating instruction of following examples, have five original scan lines and every scan line has the original digital image of five pixel datas to be stretched, can obtain scan line and every the scan line with five clauses and subclauses has seven pixel datas.
It is to be programmed to point out in this frame memory 2 it is to have five original scan lines and this original digital image to be performed in the stretching, extension of vertical direction that the programmable register group 30 of this vertical expansion controller 6 begins.Then the programmable register group of this horizontal expansion controller 10 by kind numerical value storage " 5 " this first register, numerical value " 2 " this second register, and logical one be programmed at the 3rd register.This numerical value " 5 " is corresponding to the quantity N ' of the pixel data in every original scan line in this frame memory 2.The total amount Δ N ' of the pixel data that this numerical value " 2 " will be interpolated corresponding to every scan line.Logical one in the 3rd register points out that the stretching, extension in the horizontal direction of this initial numberical data is to be performed.
First, second of this vertical expansion controller 6 and the 3rd counting circuit 31,32,33 are output as 0, because do not have vertical stretching or compression operation to be performed.First counting circuit of this horizontal expansion controller 10 is exported by Δ N ' divided by the resulting quotient T ' of N '-1.Second counting circuit of this horizontal expansion controller 10 is exported by Δ N ' divided by the resulting quotient S ' of N '-1.In the present embodiment, this remainder S ' equals 2.The output of the 3rd counting circuit of this horizontal expansion controller 10 is that it doesn't matter, because the output of this second counting circuit is to be provided to this remnants distributor at the horizontal stretching run duration.
Owing to there is not vertical stretching operation to be performed, these vertical expansion controller 6 these frame memories 2 of control provide this original scan line to this line storage 3 in regular turn.This horizontal expansion controller 10 controls this line storage 3 and this line buffer 4 provide the pixel data that is stored in it to this bilinearity adder 5 in regular turn.At this moment, often equal 1 from the factor alpha of this vertical expansion controller 6, and the output of this line buffer 4 is ignored by this bilinearity adder 5.The output of this bilinearity adder 5 equates with the output of this line storage 3.
As mentioned above, the stretching, extension operation of this horizontal telescopic unit is similar with the stretching, extension operation of this vertical telescopic unit in fact, but it is different with this vertical expansion controller 6, these horizontal expansion controller 10 these bilinearity adders 9 of control are carried out the individual raw pixel data of n ' that is stored in this buffer 8, and be stored in the bilinear interpolation of n '+1 raw pixel data in this register 7, can produce one and obtain a remainder S ' divided by N '-1 as Δ N ', as n ' during for the minimum value of satisfy condition (n '+1) * (s ') 〉=(s ') * (N '), wherein (s ') scope is the remaining interpolated pixel data that are inserted between this n ' and n '+1 raw pixel data from 1 to (S ').Therefore, equal 5,2 and 2 respectively with regard to N ', Δ N ' and S ', remaining interpolated pixel data will be inserted between second and the 3rd raw pixel data of one scan line and between the 4th and the 5th raw pixel data.
This horizontal expansion controller 10 is initial set the scan-line data that is stored in this line storage 3 first pixel data dot address and control this line storage 3, provide this first pixel data to this bilinearity adder 5, receive by this register 7 during the pixel clock that can together begin.Factor alpha from this horizontal expansion controller 10 equals 1, and this latches command signal produces this buffer of may command 8 and comes Chu Lingcun from this first raw pixel data of this register 7 within it.In this first raw pixel data of output of this bilinearity adder 9 of this stage, and can directly be provided to this output device (figure does not show).
At this moment, these horizontal expansion controller 10 these line storages 3 of control provide second raw pixel data to this bilinearity adder 5, receive for this register 7.This horizontal expansion controller 10 produces two side reaction coefficients 1 and 1/2 continuously in two continuous original pixels clocks.In this first original pixels clock, these bilinearity adder 9 these second raw pixel data of output, and also in the identical time, the latter is stored in this buffer 8, because this factor alpha equals 1.In this second original pixels clock, this line storage 3 provides the 3rd raw pixel data to this bilinearity adder 5, receives for this register 7.This factor alpha is to equal 1/2 now, and this second raw pixel data is still in this buffer 8.In this stage, this bilinearity adder 9 is output as the bilinear interpolation of this second and the 3rd raw pixel data.
At next original pixels clock period, return 1 from the factor alpha of this horizontal expansion controller 10, and the output of this bilinearity adder 9 side by side is stored in the 3rd raw pixel data in this buffer 8.
The operation of the back of this horizontal telescopic unit is to aforementioned similar, till the 5th raw pixel data of one scan line exported by this bilinearity adder 9.
Figure 10 is the sequential chart of the horizontal stretching operation of most preferred embodiment, just N '=5 and Δ N '=2.
In this example, be 0 divided by the quotient T ' of N '-1 gained by Δ N '.If this quotient T ' is not 0, that Δ N ' be greater than or equate that with N '-1 these horizontal expansion bend 10 these bilinearity adders 9 of control carry out the n ' of one scan line and the bilinear interpolation of n '+1 raw pixel data can produce the extra quantity T ' that is inserted in the continuous interpolated pixel data between this n ' and n '+1 raw pixel data.
D. one has five original scan lines and every scan line the original digital image of five pixel datas is arranged is to be compressed, and can obtain one and have the scan line of five clauses and subclauses and the purpose digital picture that every scan line has three pixel datas.
The programmable register group 30 of this vertical expansion controller 6 be programmed at first point out in this frame memory 2 be five original scan lines are arranged, do not have scan line to be interpolated, and this original digital image be to be performed in the stretching, extension of vertical direction.The programmable register group of this horizontal expansion controller 10 by numerical value storage " 5 " this first register, numerical value " 2 " this second register, and logical zero be programmed at the 3rd register.This numerical value " 5 " is the quantity N ' corresponding to the pixel data of every original scan line of the digital picture in this frame memory 2.This numerical value " 2 " is the total amount Δ N ' that wants deleted pixel data corresponding to every scan line.Logical zero in the 3rd register can point out that the compression in the horizontal direction of this initial numberical data will be performed.
First, second of this vertical expansion controller 6 and the 3rd counting circuit 31,32,33 are output as 0, because do not have vertical stretching or compression operation to be performed, therefore, these vertical expansion controller 6 these frame memories 2 of control provide this original scan line to this line storage 3 in regular turn.This horizontal this line storage 3 of expansion controller 10 controls and this line buffer 4 provide the selecteed pixel data that is stored within it to this bilinearity adder 5.With present embodiment, be often to equal 1 from the factor alpha of this vertical expansion controller 6, and the output of this line buffer 4 is ignored by this bilinearity adder 5.The output of this bilinearity adder 5 equates with the output of this line storage 3.
The compression operation of this horizontal telescopic unit is similar with the compression operation of this vertical telescopic unit in fact, but, in this horizontal telescopic unit, 4 selecteed raw pixel data of output of this horizontal this line storage 3 of expansion controller 10 controls and this line buffer, will be by the raw pixel data of this line storage 3 and 4 outputs of this line buffer, when the output of the adder of the remaining distributor of this horizontal expansion controller 10 during less than poor (N '-Δ N '), only formerly the raw pixel data of being exported by this line storage 3 and this line buffer 4 is offset a numerical value V ', and when other states, only formerly the raw pixel data of being exported by this line storage 3 and this line buffer 4 is offset numerical value V '+1, and this numerical value V ' is that N ' is divided by N '-resulting quotient of Δ N '.
The output of first and second counting circuits of this horizontal expansion controller 10 is that it doesn't matter at this level compression run duration.The output of the 3rd counting circuit is by the remainder U ' of N ' divided by N '-Δ N ' gained, N '-Δ N ' is that every scan line is wanted maintained raw pixel data quantity, in the present embodiment, this remainder U ' equals 2 and be the remaining distributor that is provided to this horizontal expansion controller 10.
This horizontal expansion controller 10 is the dot address of setting first pixel data that is stored in the one scan line data in this line storage 3 at first, and control this line storage 3 begins to provide this first pixel data to this bilinearity adder 5 during the pixel clock together, because a logical zero is to be stored in the 3rd register of this horizontal expansion controller 10, factor alpha from this horizontal expansion controller 10 is maintained at 1, therefore, this buffer 8 is to be used to continue the pixel data of storage from this register 7, and the output of this bilinearity adder 9 often is the output of this register 7.
At this moment, the output of the adder of the remaining distributor of this horizontal expansion controller 10 is bigger than this is poor (N '-Δ N '), causes the result of shift value (V '+1) or 2 by this.This horizontal this line storage 3 of expansion controller 10 controls and this line buffer 4 provide the 3rd pixel data of the scan-line data that is stored within it to receive for this register 7 to this bilinearity adder 5.
When next pixel clock arrived, the output of the adder of the remaining distributor of this horizontal expansion controller 10 equaled that this is poor (N '-Δ N '), causes the result of a shift value (V ,+1) or 2 by this.The 5th pixel data that this horizontal this line storage 3 of expansion controller 10 controls and this line buffer 4 provide the scan-line data that is stored within it receives for this register 7 to this bilinearity adder 5.
Figure 11 is the sequential chart of the level compression operation of present embodiment, just N '=5 and Δ N '=2.
In sum, device of the present invention is a kind of flexible dedicated hardware device of instant two dimension of allowing digital image size, because of the storage storage being required few reason of using less treatment step that reaches, so it is quite cheap, and result with greater efficiency, the output of this vertical telescopic unit need not be stored under the intermediate frame buffer, directly be provided to this horizontal telescopic unit, and because the output of this horizontal telescopic unit need not be stored under the output frame buffer, directly be provided to an output device, so the present invention is well suited for doing on-the-spot Video Applications.
Claims (4)
1. even device of flexible digital image size, this device comprises one in order to store this original digital image frame memory (2) within it, this original digital image has the continuous original scan line of N bar and every individual continuous raw pixel data of original scan line N ', this device also comprises one in order to stretch this original digital image to obtain the vertical telescopic unit of the continuous scan line of M bar in vertical direction, and horizontal telescopic unit that obtains the individual continuous pixel data of every scan line M ' in order to flexible scan line in the horizontal direction from this vertical telescopic unit, this numerical value M is bigger than this numerical value of N, this numerical value M ' is characterized in that than this numerical value of N ' little:
This vertical telescopic unit comprises:
A line storage (3) is connected to this frame memory (2) and stores from the original scan line of n+1 bar of this frame memory (2) within it;
A line buffer (4) is connected to this line storage (3) and stores the original scan line of n bar within it;
A bilinearity adder (5) is connected to this line storage (3) and this line buffer (4);
A vertical expansion controller (6) is connected to this frame memory (2), this line buffer (4) and this bilinearity adder (5);
This vertical expansion controller this original scan line of control storage in this line storage (3) and this line buffer (4), this vertical expansion controller is also controlled this bilinearity adder and is carried out from the n+1 of this line storage (3) and this line buffer (4) and the linear interpolation of the original scan line of n bar, to produce a remaining inserting scan lines, when obtaining remainder S divided by N-1, M-N reaches when n is the minimum value of (n+1) * S 〉=s * N that satisfies condition, wherein s is from 1 to S, and this remnants inserting scan lines is inserted between this n and the original scan line of n+1 bar;
This horizontal telescopic unit comprises a horizontal expansion controller (10), and this horizontal expansion controller (10) also comprises:
An address generator (37) is connected to this line storage (3) and this line buffer (4), controls this line storage (3) and this line buffer (4) and exports first raw pixel data in this n+1 and the n bar scan line respectively;
Generation device (33) in order to produce a numerical value U ', this numerical value are a remainder by numerical value of N ' drawn divided by numerical value M ';
A data register (56);
Adder (43) is connected to this generation device (33) and this data register (56), and the numerical value that will be stored in this data register (56) is obtained one and several mutually with this numerical value U ';
Counting circuit (44), be connected to this adder (43), this address generator (37) and this data register (56), to be somebody's turn to do and count and this numerical value M ' will compare and drive this address generator (37) and control this line storage (3) and this line buffer (4) and export another raw pixel data in this scan line, when this and number less than numerical value M ' time, this another raw pixel data is the previous raw pixel data individual pixel data of being exported by this line storage (3) and this line buffer (4) of V ' afterwards, and when should and number when equating with this numerical value M ' at least, be previous raw pixel data V '+1 pixel data afterwards of being exported by this line storage (3) and this line buffer (4), this numerical value V ' is equal to the quotient of N ' divided by M ' gained;
When this equates with this numerical value M ' at least with number, this counting circuit (44) stores the difference of this and number and this numerical value M ' in this data register (56), and when should and number system than this numerical value M ' hour, this counting circuit (44) stores and should and count in this data register (56);
The output of this horizontal telescopic unit can directly be provided to an output device thus;
As M-N during more than or equal to N-1, this vertical expansion controller (6) is further controlled the linear interpolation that this bilinearity adder (5) carries out n and the original scan line of n+1 bar and is produced the continuous inserting scan lines of an additional number T, when M-N is bigger than N-1, this continuous inserting scan lines is inserted between this n and the original scan line of n+1 bar, and this numerical value T is and is equated divided by the quotient of N-1 gained by M-N.
2. even device of flexible digital image size, this device comprises one in order to store this original digital image frame memory (2) within it, this original digital image has the continuous original scan line of N bar and every individual continuous raw pixel data of original scan line N ', this device also comprises one in order to obtain the vertical telescopic unit of the continuous scan line of M bar in flexible this original digital image of vertical direction, and one obtain the horizontal telescopic unit of the individual continuous pixel data of every scan line M ' in order to flexible scan line from this vertical telescopic unit in the horizontal direction, this numerical value M is littler than this numerical value of N, this numerical value M ' is characterized in that than this numerical value of N ' big:
This vertical telescopic unit comprises a vertical expansion controller (6) and is connected to a line storage (3) of this frame memory (2) that this vertical expansion controller (6) comprising:
An address generator (37) is connected to this frame memory (2), controls this frame memory (2) and exports the original scan line of this original scan line article one wherein for being stored in this line storage (3);
In order to the generation device (33) that produces a numerical value U, this numerical value is a remainder that is drawn divided by numerical value M by numerical value of N;
A data register (56);
Adder (43) is connected to this generation device (33) and this data register (56), and the numerical value that will be stored in this data register (56) is obtained one and several mutually with this numerical value U;
Counting circuit (44), be connected to this adder (43), this address generator (37) and this data register (56), to be somebody's turn to do and count and this numerical value M will compare and drive this address generator (37) and control this frame memory (2) and export another original scan line in this original scan line for being stored in this line storage (3), when this and number during less than numerical value M, this another original scan line is last the original scan line V bar scan line of being exported by this frame memory (2) afterwards, and when should and number when equating with this numerical value M at least, be last the original scan line V+1 bar scan line of being exported by this frame memory (2) afterwards, this numerical value V is equal to the quotient of N divided by the M gained;
When this equates with this numerical value M at least with number, this counting circuit (44) stores the difference of this and number and this numerical value M in this data register (56), and when should and number than this numerical value M hour, this counting circuit (44) stores and should and count in this data register (56);
This horizontal telescopic unit comprises:
A point register (7) stores from this scan line n '+1 pixel data of one wherein of this line storage (3) within it;
A point buffer (8) is connected to this register (7) and stores from the individual pixel data of n ' in this scan line of this line storage (3) within it;
A bilinearity adder (9) is connected to this register (7) and this buffer (8);
A horizontal expansion controller (10) is connected to this line storage (3), this buffer (8) and this bilinearity adder (9);
This horizontal expansion controller is controlled the storage of this pixel data in this register (7) and this buffer (8), this horizontal expansion controller (10) is also controlled the linear interpolation that this bilinearity adder (9) carries out from this n+1 ' of this register (7) and this buffer (8) and the individual pixel data of n ' and is produced remaining interpolated pixel data, when M '-N ' obtains remainder S ' divided by N '-1 and when n ' is one and satisfies condition the minimum value of (n '+1) * S ' 〉=s ' * N ', wherein s ' is from 1 to S ', and these remnants interpolated pixel data are inserted between this n ' and the n '+1 original scan line;
The output of this bilinearity adder (9) can directly be provided to an output device by this.
3. the device of evenly flexible digital image size as claimed in claim 2 is characterized in that:
As M '-N ' during more than or equal to N '-1 ', this horizontal expansion controller (10) can further be controlled this bilinearity adder (9) and carry out linear interpolation from the n ' of this scan line of this line storage (3) and n '+1 pixel data to produce the continuous interpolated pixel data of an additional number T ', when M '-N ' is bigger than N '-1, these continuous interpolated pixel data that produce from this linear interpolation (9) are inserted between this n ' and n '+1 pixel data, and this numerical value T ' is and equates divided by the quotient of N '-1 gained with M '-N '.
4. even device of flexible digital image size, comprise one in order to store this original digital image frame memory within it, this original digital image has the continuous original scan line of N bar and every individual continuous raw pixel data of original scan line N ', this device more comprises one in order to obtain the vertical telescopic unit of the continuous scan line of M bar in flexible this original digital image of vertical direction, and horizontal telescopic unit that obtains the individual continuous purpose pixel data of every scan line M ' in order to flexible scan line in the horizontal direction from this vertical telescopic unit, this numerical value M is littler than this numerical value of N, this numerical value M ' is characterized in that than this numerical value of N ' little:
This vertical telescopic unit comprises a vertical expansion controller and is connected to a line storage of this frame memory that this vertical expansion controller (6) comprising:
First address generator is connected to this frame memory, controls this frame memory and exports the original scan line of this original scan line article one wherein for being stored in this line storage;
One in order to produce first generation device of a numerical value U, and this numerical value is a remainder that is drawn divided by numerical value M by numerical value of N;
First data register;
First adder is connected to this first generation device and this first data register, and numerical value and this numerical value U addition that is stored in this first data register obtained one and several;
First counting circuit is connected to this first adder, this first address generator and this first data register;
This and number and this numerical value M are compared and drive this first address generator control in this frame memory and this original scan line of output another for being stored in this line storage, when this and number during less than numerical value M, this another original scan line is last the original scan line V bar scan line of being exported by this frame memory afterwards, and when should and number when equating with this numerical value M at least, be last the original scan line V+1 bar scan line of being exported by this frame memory afterwards, this numerical value V is equal to the quotient divided by the M gained by N;
When this and number equated with this numerical value M at least, this first counting circuit stored the difference of this and number and this numerical value M in this first data register, and when should and number than this numerical value M hour, this first counting circuit stores and is somebody's turn to do and counts in this first data register;
This horizontal telescopic unit comprises a horizontal expansion controller, and this horizontal expansion controller comprises:
Second address generator is connected to this line storage, controls this line storage and exports wherein first raw pixel data of one of this scan line;
In order to producing second generation device of a numerical value U ', this numerical value is a remainder by numerical value of N ' drawn divided by numerical value M ';
Second data register;
Second adder is connected to this second generation device and this second data register, and the numerical value that is stored in this second data register is obtained one and several mutually with this numerical value U ';
Second counting circuit is connected to this second adder, this second address generator and this second data register; This and number and this numerical value M ' are compared and drive this second address generator to be controlled this line storage and exports another raw pixel data in this scan line, when this and number less than numerical value M ' time, another raw pixel data of this of this scan line, the raw pixel data of exporting from this line storage immediately following formerly is offset a numerical value V ', and when should and number when equating with this numerical value M ' at least, only formerly the raw pixel data of exporting from this line storage is offset numerical value V '+1, and this numerical value V ' is equal to the quotient of N ' divided by M ' gained;
When this equates with this numerical value M ' at least with number, this second counting circuit stores the difference of this and number and this numerical value M ' in this second data register, and when should and number than this numerical value M ' hour, this second counting circuit stores and should and count in this second data register, and then the output of this horizontal telescopic unit can directly be provided to an output device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00106548 CN1127846C (en) | 1995-07-31 | 2000-04-11 | Device capable of uniformly magnifying and contracting image size |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95109686.9 | 1995-07-31 | ||
| CN95109686A CN1110017C (en) | 1995-07-31 | 1995-07-31 | Method for homogeonously stretching-out and drawing-back size of digital picture and apparatus thereof |
| CN 00106548 CN1127846C (en) | 1995-07-31 | 2000-04-11 | Device capable of uniformly magnifying and contracting image size |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96106993A Division CN1061500C (en) | 1995-07-31 | 1996-07-31 | Device capable of uniformly adjusting digital image size |
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| Publication Number | Publication Date |
|---|---|
| CN1272746A CN1272746A (en) | 2000-11-08 |
| CN1127846C true CN1127846C (en) | 2003-11-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00106548 Expired - Lifetime CN1127846C (en) | 1995-07-31 | 2000-04-11 | Device capable of uniformly magnifying and contracting image size |
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| CN (1) | CN1127846C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100395811C (en) * | 2005-03-29 | 2008-06-18 | 威盛电子股份有限公司 | Programmable image size conversion method and device |
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2000
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100395811C (en) * | 2005-03-29 | 2008-06-18 | 威盛电子股份有限公司 | Programmable image size conversion method and device |
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| CN1272746A (en) | 2000-11-08 |
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