CN112783571A

CN112783571A - PCIE resource distribution system and method

Info

Publication number: CN112783571A
Application number: CN202110091090.XA
Authority: CN
Inventors: 王树明
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-01-22
Filing date: 2021-01-22
Publication date: 2021-05-11

Abstract

The invention provides a PCIE resource distribution system and a method thereof, wherein the system comprises a transfer board, and the transfer board comprises: the CPLD is configured to receive the board card type signal, acquire the board card type based on the board card type signal, and send at least one control signal based on the board card type and a PCIE resource allocation table, wherein the PCIE resource allocation table is used for storing a plurality of preset board card types and PCIE working modes mapped by the board card types; and each Retimer is configured to receive a respective control signal from the CPLD to load corresponding firmware, and perform PCIE interface allocation based on a loading completion result, where each firmware corresponds to one PCIE operating mode. The invention realizes the allocation of different working modes of the PCIe port configured with the Retimer, meets the requirement of adapting to different PCIE board cards to expand PCIe external equipment, increases the flexibility of the system for expanding the PCIe equipment, and enhances the driving capability of a PCIE link of the system.

Description

PCIE resource distribution system and method

Technical Field

The present invention relates to the field of PCIE technologies, and in particular, to a PCIE resource allocation system and method.

Background

Semiconductor integrated circuit technology is rapidly developed, and more transistors can be integrated on a wafer, so that more IO interfaces can be expanded by a CPU chip, such as a new generation of Intel and AMD type CPUs, and compared with the external PCIe interface, the external PCIe interface is improved by a lot. The increase in the number of PCIe interfaces means a great increase in the number of external device resources that can be accessed by one CPU and in flexibility. While the number of IOs has increased, PCIe rates have increased, for example, from PCIe Gen3.08GT/s to PCIe Gen4.016GT/s or even to the less popular Gen5.032GT/s. The increase in PCIe bus rate causes losses in the signal path to be more severe than ever. PCIe IO resources are increased, so that a CPU can access more external devices, and the flexibility of system configuration is increased; however, the signal loss caused by the PCIe rate increase also limits the length of the signal link, which brings inconvenience to the actual application of the IO resource. The PCIe Gen4.0 rate is limited to be changed, when a PCIe interface of a mainboard CPU expands external equipment, the wiring length is shortened, the layout of the mainboard and the adaptability of the board card length are reduced, and the influence on the system structural design and the heat dissipation design is not negligible.

In addition to changing the motherboard architecture, as shown in the schematic diagram of the conventional PCIE resource allocation system shown in fig. 1, a driver/timer/Switch is connected in series between the CPU and the external PCIE device, and the PCIE link length is increased by using the driving capability of the driver/timer/Switch registers: (1) the method of the Redriver is only applied to the physical layer, and the using method is simple; (2) by using the Reitmer mode, the PCIe bus driving capacity can be increased, the PCIe link length is prolonged, the Reitmer is transparent under the system, invisible under the PCIe equipment of the system, and the adaptation influence degree on system software is small; (3) by using the switch mode, on one hand, the driving capability of the switch Serdes can be utilized to increase the PCIe link length, and on the other hand, PCIe interface resources with different quantities can be developed.

The technical scheme of timer/Switch can realize basic application requirements under certain occasions, but has the following disadvantages:

(1) by using a Redriver mode, the driving parameters of the Redriver can only be fixedly used in a unique link, and when different external PCIe devices are accessed, the problem that link/card loss cannot be caused due to the fact that the parameters are not suitable any more is possible;

(2) by using a timer mode, the Serdes capability is strong, the problem of limitation of a driver does not exist, but in the current general design method, the timer uses a single configuration file, has unique functions, is only suitable for being used under a specific scene and a specific configuration, has small delay and low reuse rate;

(3) by using the Switch mode, due to the Switch working principle, the PCIe bus of the system is seen in the Switch device, and due to the existence of the Switch between the CPU and the external PCIe device, the delay is large, the bandwidth is influenced, the bus depth between the CPU and the external PCIe device is increased, problems exist in the adaptation of some application software models, and the middle serial Switch chip is not allowed in some scenes.

Disclosure of Invention

In view of this, the present invention provides a PCIE resource allocation system and method, so as to solve the problem that, in the prior art, when a CPU PCIE interface of a motherboard expands an external device, a PCIE gen4.0 bus has weak driving capability.

Based on the above object, the present invention provides a PCIE resource allocation system, including a patch panel, where the patch panel includes:

the CPLD is configured to receive the board card type signal, acquire the board card type based on the board card type signal and send at least one control signal based on the board card type and a PCIE resource allocation table, wherein the PCIE resource allocation table is used for storing a plurality of preset board card types and PCIE working modes mapped by the board card types; and

and each Retimer is configured to receive a respective control signal from the CPLD to load corresponding firmware, and perform PCIE interface allocation based on a loading completion result, where each firmware corresponds to one PCIE operating mode.

In some embodiments, the adapter board further comprises a plurality of EEPROMs connected to the CPLD and the timer, each EEPROM being used for storing a configuration file of the firmware.

In some embodiments, the interposer further includes a plurality of MUX chips respectively connected to the EEPROMs, and configured to accept control of the CPLD to enable each timer to access the corresponding EEPROM.

In some embodiments, the MUX chip is further configured to accept control of the CPLD to refresh the firmware of the EEPROMs.

In some embodiments, the system further comprises a PCIE card configured to send a card-type signal.

In some embodiments, the system further includes a motherboard configured to receive the board type signal sent by the CPLD, and configure a corresponding CPU PCIE port mode based on the board type signal and the PCIE resource allocation table, where the PCIE resource allocation table further includes a CPU PCIE port mode mapped to each board type.

In some embodiments, the patch panel further includes a connector configured to accept a refresh of firmware of the CPLD by a BMC of the motherboard.

In some embodiments, each Retimer is further configured to output a respective load complete signal based on the load complete result.

In some embodiments, the CPLD is further configured to receive each load completion signal, and in response to receiving all load completion signals, send a power-on signal to the motherboard to cause the motherboard to perform power-on initialization.

In another aspect of the present invention, a PCIE resource allocation method is further provided, including the following steps:

receiving a board card type signal through the CPLD, acquiring the board card type based on the board card type signal, and sending at least one control signal based on the board card type and a PCIE resource allocation table, wherein the PCIE resource allocation table is used for storing a plurality of preset board card types and PCIE working modes mapped by the board card types;

and receiving each control signal from the CPLD through the corresponding timer to load corresponding firmware, and realizing PCIE interface allocation based on a loading completion result, wherein each firmware corresponds to a PCIE working mode.

The invention has at least the following beneficial technical effects:

1. according to the invention, the PCIE resource distribution table is set, the mapping relation among the PCIE board card type, the Retimer and a plurality of PCIE working modes is established, the distribution of different working modes of the PCIe port configured with the Retimer is realized, the requirement of adapting to different PCIE board cards to expand PCIe external equipment is met, and the flexibility of the system for expanding the PCIe equipment is increased;

2. through setting up the keysets that can adapt to multiple PCIE mode of operation automatically, can be according to the type difference of the inside interconnection PCIE integrated circuit board of server, the firmware of automatic switch timer loading can conveniently insert in the system architecture of difference, reinforcing system PCIE link driving force.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

Fig. 1 is a schematic diagram of a conventional PCIE resource allocation system according to the prior art;

FIG. 2 is a schematic block diagram of an interposer provided in accordance with an embodiment of the present invention;

fig. 3 is a schematic topology diagram of a PCIE resource allocation system according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a PCIE resource allocation method according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two non-identical entities with the same name or different parameters, and it is understood that "first" and "second" are only used for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements does not include all of the other steps or elements inherent in the list.

Based on the above purpose, a first aspect of the embodiments of the present invention provides an embodiment of a PCIE resource allocation system. Fig. 2 is a schematic block diagram of an interposer provided according to an embodiment of the present invention. As shown in fig. 2, an embodiment of the present invention includes an interposer that includes a CPLD and at least one timer. The CPLD is configured to receive a board card type signal, acquire the board card type based on the board card type signal, and send at least one control signal based on the board card type and a PCIE resource allocation table, wherein the PCIE resource allocation table is used for storing a plurality of preset board card types and PCIE working modes mapped by the board card types. Each timer configuration is used for receiving respective control signals from the CPLD to load corresponding firmware, and realizing PCIE interface allocation based on a loading completion result, wherein each firmware corresponds to a PCIE working mode.

Fig. 2 shows a schematic block diagram of the patch panel, and as shown in fig. 2, taking 2 timers as an example, two PCIe gen4.0 timer chips are designed on the patch panel, each timer provides a PCIe gen4.0 x16 lane interface to the upstream and provides a PCIe gen4.0 x16 interface to the downstream. The PCIe upstream and downstream directions may be configured via firmware and are not fixed. The Retimer chip inputs a set of 100MHz for the Retimer PCIe reference clock, and the Retimer plays a role of buffer and outputs a set of 100HMz for the back-end device to use. The high-speed signal of the Retimer comprises a PCIe signal and a 100MHz signal, and is connected with the outside through a board end connector CONN-1/CONN-2/CONN-4/CONN-5, and the connector is in a slim line x8 connector form, so that the Retimer is wide in application and good in universality. Retimer represents a Retimer; PCIE stands for PCI-Express, a high speed serial computer expansion bus standard.

Table 1 shows a PCIE resource allocation table, where x16, 2 × x8, and 4 × x4 in the table indicate PCIE operating modes, i.e., PCIE data line widths. As shown in Table 1, different Board Type codes are defined, which respectively represent the PCIe lane width port resources required by different external PCIe boards for expansion, and the corresponding Retimer-A/Retimer-B.

Table 1PCIE resource allocation table

The embodiment of the invention establishes the mapping relation among the types of the PCIE board cards, the Retimer and a plurality of PCIE working modes by setting the PCIE resource distribution table, realizes the distribution of different working modes of the PCIe port for configuring the Retimer, meets the requirement of adapting to different PCIE board cards to expand PCIe external equipment, and increases the flexibility of the system for expanding the PCIe equipment; through setting up the keysets that can adapt to multiple PCIE mode of operation automatically, can be according to the type difference of the inside interconnection PCIE integrated circuit board of server, the firmware of automatic switch timer loading can conveniently insert in the system architecture of difference, reinforcing system PCIE link driving force.

Fig. 2 shows a schematic block diagram of an adapter board, and as shown in fig. 2, 3 sets of EEPROM memory chips, respectively, EEPROM-0, EEPROM-1, and EEPROM-2, are designed on the adapter board, and are respectively used for storing firmware of a Retimer, and the Retimer can access a firmware configuration file loading an EEPROM through an I2C bus. As in the timer firmware working definition of table 2, 3 EEPROMs store 3 different firmware profiles that are conventionally used: firmware stored in eeprom-0 can configure a timer to work in an upstream and downstream x16 lane mode; firmware stored in eeprom-1 can configure the timer to work in an uplink and downlink 2 x8 lane mode; the firmware configurable Retimer stored in eeprom-2 works in 4 × 4lane mode. The Retimer can be defined to operate in different PCIe modes of operation when it is controlled to load different EEPROM firmware. The modularized design scheme can be easily adapted to different application scenes and different Retimer working mode requirements, so that one set of hardware can perfectly deal with the switching of various Retimer working modes. And the firmware stored by the EEPROM can be flexibly configured according to the needs, so that the timer is not limited to a single application mode and application scene.

TABLE 2 Retimer firmware job definitions

EEPROM	Timer mode of operation
		eeprom-0	Retimer works in x16 mode
eeprom-1	The Retimer works in 2 × 8 mode
		eeprom-2	The Retimer works in 4 × 4 mode

As shown in FIG. 2, 3 MUX chips are arranged on the adapter plate, wherein the MUX chips are MUX-0, MUX-1 and MUX-2, and when the MUX chips are used for the Retimer to access the EEPROM, the first CPLD controls the communication of each MUX chip through 3 sets of SEL [1:0] selection signals, so that the Retimer is controlled to access different EEPROMs. Table 3 is a table of the relationship between the preset SEL [1:0] select signals and the MUX channels it controls.

TABLE 3 SEL [1:0] selection signals vs. MUX channel controlled

SEL[1]	SEL[0]	MUX channel correspondence
			0	0	A＝B
0	1	A＝C
			1	0	A＝D

As shown in table 3 and fig. 2, when it is necessary to control Retimer-a to access eeprom-0, CPLD sets the first set SEL [1:0] to 01, then the a channel of MUX-0 chip is communicated with the C channel, and Retimer-a can access eeprom-0 through I2C; at this time, the CPLD outputs the 2 nd and 3 rd sets SEL [1:0] to 10, the a channel of the MUX-1/MUX-2 chip is communicated with the D channel, eeprom-1 and eeprom-2 are in an idle state, and the Retimer does not access the channels; similarly, MUX-1/MUX-2 can be controlled by the CPLD to enable Retimer-A to access eeprom-1, eeprom-2. Similarly, the CPLD can control the MUX to communicate to make the Retimer-B access to a different EEPROM.

The method is characterized in that 3 groups of EEPROMs are integrated to store different Retimer firmware and 3 groups of MUX multiplexers, a CPLD control logic of Retimer cooperative loading firmware is designed by utilizing a Retimer chip default signal, a CTRL loading control signal and a CPML loading finishing signal, so that the order work of two groups of retimers is not influenced mutually, the number of EEPROMs occupied by different firmware storage is reduced, and the competition of two retimers on an I2C bus is avoided.

As shown in FIG. 2, a group of I2C leading to 3 groups of EEPROM chips is provided, when the EEPROM firmware needs to be refreshed, the BMC writes different SEL [1:0] control information into the CPLD through I2C, the CPLD can control SEL [1:0] to enable MUX-0/MUX-1/MUX-2 respectively to select the corresponding EEPROM, and then the BMC I2C transmits the firmware data to the EEPROM through CPLD I2C, thereby realizing independent refreshing action. For example, when an eeprom-0 is to be refreshed, the CPLD outputs the 1 st set SEL [1:0] as 00, the a channel of MUX-0 is communicated with the B channel, CPLD I2C can access eeprom-0, while the CPLD outputs the 2 nd set SEL [1:0] as 10, the a channel of the MUX-1/MUX-2 chip is communicated with the D channel, and eeprom-1/eeprom-2 is in an idle state; similarly, the CPLD selects eeprom-1/eeprom-2 by controlling 3 sets of SEL [1:0] signals. It should be noted that, when the system is powered on, the CPLD preferentially processes the timing sequence of the timer loading the firmware, and when the timer completes initialization, the relevant refresh action is allowed to be performed on the EEPROM.

In some embodiments, the system further comprises a PCIE card configured to send a card-type signal. Fig. 3 is a schematic view of a topology of a PCIE resource allocation system, and as shown in fig. 3, when the adapter card is interconnected with the motherboard and the PCIE Board, a Board Type signal (Board Type signal) designed by the PCIE Board is input to the CPLD through the CONN-3 connector. The CPLD can judge the current connected Board card according to the Board Type, select the working mode of the timer-A and the timer-B through the PCIe resource allocation table, and further select the EEPROM firmware which allows the timer to load the matching when the timer is electrified for initialization. Meanwhile, the CPLD sends the Board Type upwards to the mainboard through CONN-0, and the BIOS configures the corresponding CPU PCIe port bifurcation according to the Board Type.

As shown in fig. 3, from the viewpoint of resource balance, 2 timers are integrated on the patch panel, and the 2 timers can be connected to two CPUs of the motherboard of the general 2S node upward or connected to two PCIe ports of one CPU. The adapter board can be connected to a PCIe board card in a descending mode and used for installing equipment such as NIC/HCA/GPU cards with standard sizes and an NMVE backboard and used for expanding NVME SSD hard disk equipment. And the CPLD on the adapter board interacts with the CPLD responsible for the control signal of the mainboard, and transmits the control signal sent by the CPLD to the downlink PCIe board card or the NVME backboard.

In some embodiments, the system further includes a motherboard configured to receive the board type signal sent by the CPLD, and configure a corresponding CPU PCIE port mode based on the board type signal and the PCIE resource allocation table, where the PCIE resource allocation table further includes a CPU PCIE port mode mapped to each board type. The PCIE resource allocation table shown in table 1 defines different Board Type codes, which respectively represent PCIE lane width port resources required by different external PCIE boards for expansion and the configuration state of the corresponding upstream CPU PCIE port mode.

In some embodiments, the patch panel further includes a connector configured to accept a refresh of firmware of the CPLD by a BMC of the motherboard. An I2C interface which is designed by the CPLD and is interconnected with an external BMC is connected to the mainboard through a CONN-0 connector, and the refreshing of the BMC on the CPLD firmware can be supported. By setting a group of I2C between the BMC-CPLD and the BMC-CPLD-EEPROM and defining on a software protocol, the BMC can refresh the CPLD so as to modify the mapping relation between the Board Type code and the Retimer firmware and the EEPROM; meanwhile, the BMC can refresh the EEPROM through the CPLD, further defines the working mode of the Retimer chip, and increases the flexible adaptability of the Retimer to an external PCIe board card.

In some embodiments, each Retimer is further configured to output a respective load complete signal based on the load complete result. In some embodiments, the CPLD is further configured to receive each load completion signal, and in response to receiving all the load completion signals, send a power-on signal to the motherboard to enable the motherboard to perform power-on initialization.

As shown in fig. 3, the CPLD module is designed as a main control unit for controlling the timer power-on logic and the initialization configuration logic. The main body is as follows: the CPLD releases chip reset by controlling a Retimer RST pin, and enables internal logic of the chip; the CPLD can control a CTRL pin of the timer to enable the timer to load EEPROM firmware, and the CPLD can accept a CMPL pin output by the timer to judge whether the timer is loaded completely. The adapter Board controls the power-on time sequence and firmware initialization of the timer unit by using the CPLD control logic unit, can flexibly set the corresponding relation in the CPLD firmware according to the defined EEPROM firmware Type and Board Type, does not need human intervention, and can automatically complete the adaptation after the system is started.

As shown in fig. 2 and fig. 3, the CPLD is also responsible for forwarding the power-on enable signal PWREN and the PERST PCIe reset signal of the motherboard CPLD timing control signal PWREN to the downstream external PCIe board, and forwarding the power-on completion signal PWRGD of the PCIe board and the Retimer adapter board to the motherboard CPLD for controlling the timing of the whole motherboard CPLD.

When a PCIE resource allocation system is powered on and started up, the system enters an initialization stage and executes the following steps:

(1) the mainboard CPLD issues a PWREN electrifying enabling signal, and after the adapter board CPLD receives the signal, the PWREN signal is firstly issued to the downlink PCIE board card, and a PWRGD electrifying finishing signal output by the downlink PCIE board card is waited;

(2) when the adapter Board CPLD receives a PWRGD electrification completion signal fed back by the downlink PCIE Board card, the CPLD searches a firmware Type to be loaded by a timer-A/timer-B in an internal FLASH storage area of the CPLD according to the Board Type code.

(3) The patch panel CPLD first releases the rst (chip reset) signal of timer-a/timer-B. And the CPLD controls the SEL [1:0] signal to enable the MUX corresponding to the eeprom according to the type of the timer-A firmware retrieved from the last state, then the CPLD controls the validity of the timer-A CRTL signal, and the timer-A carries out a firmware loading process. After the loading of the Retimer-A is finished, the CMPL is input to the CPLD, and the CPLD transfers the state to the initialization process of the Retimer-B. As with the Retimer-A, the CPLD respectively controls SEL [1:0] to enable the MUX chip and enable the CTRL signal to start Retimer-B load firmware, and finally the Retimer-B outputs CMPL load to be completed to the CPLD.

(4) And the adapter board CPLD receives the signal of the reset-B initialization completion, sends a PWRGD signal to the mainboard CPLD, and the mainboard CPLD continues to carry out power-on initialization of the whole machine.

(5) When the main board CPLD sends out a system reset signal PERST, the switching board CPLD respectively outputs the PERST to the timer-A/timer-B and the downlink PCIE board card, and the PCIe equipment reset of the whole external equipment is completed.

(6) In the process of initializing the adapter Board, the CPLD of the adapter Board can also upload the Board Type signal to the mainboard, and the BIOS of the mainboard can configure the state of the corresponding CPU PCIe port mode according to the analyzed codes.

In a second aspect of the embodiments of the present invention, a PCIE resource allocation method is further provided. Fig. 4 is a schematic diagram illustrating an embodiment of a PCIE resource allocation method provided in the present invention. A PCIE resource allocation method comprises the following steps:

step S1, receiving a board card type signal through a CPLD, acquiring the board card type based on the board card type signal, and sending at least one control signal based on the board card type and a PCIE resource allocation table, wherein the PCIE resource allocation table is used for storing a plurality of preset board card types and PCIE working modes mapped by the board card types;

step S2, receiving each control signal from the CPLD through the corresponding timer to load the corresponding firmware, and implementing PCIE interface allocation based on the loading completion result, where each firmware corresponds to one PCIE operating mode.

According to the PCIE resource distribution method provided by the embodiment of the invention, the PCIE board card type, the Retimer and the mapping relation of a plurality of PCIE working modes are established by setting the PCIE resource distribution table, the distribution of different working modes of a PCIe port configured with the Retimer is realized, the requirement of adapting to different PCIE board cards to expand PCIe external equipment is met, and the flexibility of a system for expanding the PCIe equipment is increased; through setting up the keysets that can adapt to multiple PCIE mode of operation automatically, can be according to the type difference of the inside interconnection PCIE integrated circuit board of server, the firmware of automatic switch timer loading can conveniently insert in the system architecture of difference, reinforcing system PCIE link driving force.

Finally, it should be noted that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A PCIE resource distribution system is characterized by comprising a patch panel, wherein the patch panel comprises:

the CPLD is configured to receive a board card type signal, acquire the board card type based on the board card type signal and send at least one control signal based on the board card type and a PCIE resource allocation table, wherein the PCIE resource allocation table is used for storing a plurality of preset board card types and PCIE working modes mapped by the board card types; and

2. The system of claim 1, wherein the adapter board further comprises a plurality of EEPROMs connected to the CPLD and the timer, each of the EEPROMs being configured to store a configuration file of the firmware.

3. The system of claim 2, wherein the adapter board further comprises a plurality of MUX chips respectively connected to the EEPROMs, and configured to accept control of the CPLD to enable each Retimer to access the corresponding EEPROM.

4. The system of claim 3, wherein the MUX chip is further configured to accept control of the CPLD to refresh firmware of the EEPROMs.

5. The system of claim 1, further comprising a PCIE board configured to transmit the board type signal.

6. The system according to claim 1, further comprising a motherboard configured to receive the board type signal sent by the CPLD, and configure a corresponding CPU PCIE port mode based on the board type signal and the PCIE resource allocation table, wherein the PCIE resource allocation table further includes a CPU PCIE port mode mapped to each board type.

7. The system of claim 6, wherein the patch panel further comprises a connector configured to accept a refresh of firmware of the CPLD by a BMC of the motherboard.

8. The system of claim 6, wherein each Retimer is further configured to output a respective load complete signal based on the load complete result.

9. The system of claim 8, wherein the CPLD is further configured to receive load complete signals and, in response to receiving all load complete signals, send a power-on signal to the motherboard to cause power-on initialization of the motherboard.

10. A PCIE resource allocation method is characterized by comprising the following steps:

receiving a board card type signal through a CPLD, acquiring the board card type based on the board card type signal, and sending at least one control signal based on the board card type and a PCIE resource allocation table, wherein the PCIE resource allocation table is used for storing a plurality of preset board card types and PCIE working modes mapped by the board card types;