CN112782463A - Voltage detection method and voltage sensing device - Google Patents
Voltage detection method and voltage sensing device Download PDFInfo
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- CN112782463A CN112782463A CN202011593583.5A CN202011593583A CN112782463A CN 112782463 A CN112782463 A CN 112782463A CN 202011593583 A CN202011593583 A CN 202011593583A CN 112782463 A CN112782463 A CN 112782463A
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Abstract
Disclosed herein are a voltage detection method and a voltage sensing apparatus. The method comprises the steps of generating a first differential voltage according to a first current source and generating a second differential voltage according to a second current source; determining a feedback signal Kadc corresponding to the voltage to be measured according to the voltage to be measured, the first differential voltage, the second differential voltage and a preset first gain coefficient, so that the average value Kadc _ va of the feedback signal Kadc is in accordance with a preset feedback relation; determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured; the first differential voltage, the second differential voltage, the preset first gain coefficient and the band gap reference voltage meet a preset band gap reference voltage relation. According to the scheme provided by the embodiment of the disclosure, the average value of the feedback signal representing the average value of the voltage to be measured is generated, and the digital value of the voltage to be measured is further determined.
Description
Technical Field
The present disclosure relates to, but not limited to, the field of sensors, and in particular, to a voltage detection method and a voltage sensing device.
Background
As chip manufacturing processes advance, chips are developed toward smaller sizes and lower power supply voltages. In order to avoid the negative influence on the performance of the chip caused by the excessively high input voltage of the chip, a voltage sensor needs to be integrated inside the chip so as to monitor the input voltage of the chip in real time.
At present, a commonly used structure for integrating a voltage sensor inside a chip is to use a bandgap reference circuit or an off-chip reference voltage source as a reference voltage source of an ADC, quantize an input voltage through an Analog-to-digital converter (ADC, or referred to as an a/D converter for short), and achieve a voltage detection purpose through a corresponding relationship between a voltage and a reference voltage. This approach has the following drawbacks: (1) the cost is increased due to the arrangement of the band-gap reference circuit and the like, more chip area is consumed, and larger power consumption is brought; (2) because the random manufacturing deviation of the bandgap reference circuit causes a large error of the voltage sensor and has low precision, for some high-precision applications, the chip needs to be further equipped with an off-chip reference voltage source, thereby increasing the cost additionally.
In view of the above problems, new solutions are to be proposed.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the disclosure provides a voltage detection method and a voltage sensing device, which can avoid the use of a band gap reference circuit and an off-chip reference voltage source so as to reduce cost and power consumption.
The embodiment of the disclosure provides a voltage detection method, which includes:
generating a first differential voltage according to a first current source and a second differential voltage according to a second current source;
determining a feedback signal Kadc corresponding to the voltage to be measured according to the voltage to be measured V (vsp, vsn), the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain coefficient kvbg, and enabling the average value of the feedback signal Kadc to be equal to the average value
Determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured;
wherein the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg satisfy the following bandgap reference voltage relationship:
the bandgap reference voltage Vbg ═ V (vbep, vben) + kvbg × (dvbp, dvbn).
The embodiment of the present disclosure further provides a voltage sensing device, including:
a differential voltage generation module configured to: generating a first differential voltage according to a first current source and a second differential voltage according to a second current source;
a first feedback module configured to: determining a feedback signal Kadc according to the voltage V (vsp, vsn) to be measured, the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg, so that an average value Kadc _ va of the feedback signal Kadc satisfies the following feedback relationship:
V(vsp，vsn)-Kadc_va*V(vbep，vben)-Kadc_va*kvbg*V(dvbep，dvben)＝0；
a voltage determination module configured to: determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured;
wherein the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg satisfy the following bandgap reference voltage relationship:
the bandgap reference voltage Vbg ═ V (vbep, vben) + kvbg × (dvbp, dvbn).
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
FIG. 1 is a flow chart of a voltage detection method according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a linear curve of the average value KAdc va of the feedback signal and the voltage V to be measured in the embodiment of the present disclosure;
FIG. 3 is a timing diagram of a multi-phase non-overlapping clock signal according to an embodiment of the present disclosure;
fig. 4a is a schematic structural diagram of a first differential circuit in an embodiment of the present disclosure;
FIG. 4b is a schematic diagram of a first differential circuit according to another embodiment of the present disclosure;
fig. 5a is a schematic structural diagram of a second differential circuit in an embodiment of the present disclosure;
FIG. 5b is a schematic diagram of a second differential circuit according to another embodiment of the present disclosure;
FIG. 6 is a schematic structural diagram of a voltage regulation module to be tested according to an embodiment of the present disclosure;
FIG. 7 is a schematic structural diagram of a first feedback module according to an embodiment of the disclosure;
fig. 8 is a schematic structural diagram of a voltage determination module in an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The embodiment of the present disclosure provides a method for detecting voltage, a flow of which is shown in fig. 1, including:
step 11, determining a feedback signal Kadc corresponding to the voltage to be measured according to the voltage V (vsp, vsn), the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain coefficient kvbg, wherein an average value Kadc _ va of the feedback signal Kadc satisfies the following feedback relationship in terms of a final effect of the whole system:
V(vsp，vsn)-Kadc_va*V(vbep，vben)-Kadc_va*kvbg*V(dvbep，dvben)＝0 (1)；
and step 12, determining the digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured.
Wherein vbep is a positive terminal voltage of the first differential voltage, and vben is a negative terminal voltage of the first differential voltage; the dvbep is the positive terminal voltage of the second differential voltage, and the dvben is the negative terminal voltage of the second differential voltage; and vsp is the positive end voltage of the voltage to be measured, and vsn is the negative end voltage of the voltage to be measured.
The first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg satisfy the following bandgap reference voltage relationship:
the bandgap reference voltage Vbg ═ V (vbep, vben) + kvbg × (dvbep, dvben) (2).
The bandgap reference voltage Vbg is a constant associated with the semiconductor material.
The formula (1) is modified to obtain:
the feedback signal
According to (2) (3):
V(vsp，vsn)＝Kadc_va*Vbg (4)
further, it is obtained that:
where V (vsp, vsn) is a voltage to be measured, and the bandgap reference voltage Vbg is a constant associated with the semiconductor material. Therefore, the corresponding value of the voltage to be measured can be obtained according to Kadc _ va. As shown in fig. 2, Kadc _ va is a value that is linear with the voltage to be measured, and one voltage value to be measured corresponds to one Kadc _ va value. The average value Kadc _ va of the feedback signal determined according to the relation (1) can represent the value of the voltage to be measured.
Since the voltage V (vsp, vsn) to be detected, the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvben), the preset first gain factor kvbg and the average value Kadc _ va of the feedback signal satisfy the equation relationship (1) (by the transformed equation (3)), it can be seen that the denominator thereof is the bandgap reference voltage Vbg, which is a constant related to the semiconductor material, so that the bandgap reference voltage Vbg is determined and kept stable when the circuit \ chip \ integrated device for the voltage to be detected is certain, and the average value Kadc _ va of the feedback signal can be used as data representing the value of the voltage to be detected.
In some exemplary embodiments, the preset first gain factor kvbg is 7. When the scheme disclosed by the invention is implemented by adopting different circuits, the preset first gain coefficient kvbg needs to be correspondingly adjusted to meet the equation relation of the step (2).
In some exemplary embodiments, the bandgap reference voltage Vbg is 1.26V.
In some exemplary embodiments, the determining, according to the voltage to be measured, the first differential voltage, the second differential voltage, and a preset first gain coefficient, a feedback signal corresponding to the voltage to be measured includes:
determining a first transient voltage according to the voltage to be measured, the first differential voltage, the second differential voltage and the first gain coefficient;
and accumulating and summing the first transient voltage according to a clock signal, and comparing the summed result with a preset differential voltage reference to obtain the feedback signal.
In some exemplary embodiments, the clock signal is a multi-phase non-overlap clock signal generated by the clock module according to the input clock signal ADC _ clk _ i, as shown in fig. 3.
The clock signals (multiphase non-overlapping clock signals) are divided into two groups, wherein 1-n phase clocks are one group, and each latter phase clock in the group of clocks is delayed by a first preset delay time td compared with the rising edge of the former phase clock; the n +1 th-2 n phase clocks are a group, and each next phase clock in the group of clocks is delayed by a first preset delay time td compared with the rising edge of the previous phase clock;
the rising edge of the first phase clock of the second group of clocks is delayed by a first preset delay time td from the falling edge of the last phase clock of the first group of clocks; the rising edge of the first phase clock of the first set of clocks is delayed by a first preset delay time td from the falling edge of the last phase clock of the second set of clocks.
In some exemplary embodiments, quantizing the result of the accumulated summation of the first transient voltages to obtain the feedback signal includes: comparing the summed result with a differential voltage reference to obtain the feedback signal; wherein the differential voltage reference is 0.
It can be seen that the average value of the feedback signal corresponds to the average value of the voltage to be measured. In order to satisfy the feedback relationship (relation 1), the determined feedback signal Kadc is a 1-bit stream that can represent the voltage to be measured, and the conversion of the 1-bit stream into the final voltage digitized value output requires a relevant filtering process. After the 1bit stream corresponding to the feedback signal Kadc is subjected to relevant filtering processing, out-of-band noise and/or other signal interference is removed, and the voltage to be measured can be more accurately represented by the obtained feedback signal average value Kadc _ va. Those skilled in the art will appreciate that this process may be considered as further averaging the feedback signal Kadc to obtain an average Kadc _ va.
In some exemplary embodiments, the determining the digitized value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured includes:
according to a preset cut-off frequency, low-pass filtering is carried out on a feedback signal Kadc corresponding to the voltage to be measured, and multi-bit filtering data are obtained; and the multi-bit filtering data is the average value representation of the voltage to be measured. According to the direct proportion relation between the voltage to be measured and the average value of the feedback signal, the filtering data of multiple bits and the voltage to be measured are in a linear relation.
Because the multi-bit filtering data and the voltage to be detected are in a linear relation, the filtering data can be amplified according to a preset voltage detection gain and added with a preset voltage detection offset to obtain a voltage value corresponding to the voltage to be detected. Wherein the voltage detection gain and the voltage detection offset are determined according to a manufacturing process of the related implementation circuit.
In some exemplary embodiments, the set cutoff frequency may be set to 1/128 degrees of the clock signal frequency, the cutoff frequency not exceeding 1/2 degrees of the clock frequency at maximum.
In some exemplary embodiments, the generating the first differential voltage according to the first current source includes:
generating the first differential voltage according to the first current source and the first transistor
Wherein ICIs the collector current of the first transistor, ISIs the first transistor reverse saturation current.
In some exemplary embodiments, said generating a second differential voltage according to a second current source comprises:
generating the second differential voltage according to the second current source, the second transistor and the third transistor
Where K is the Boltzmann constant, T is the absolute temperature, and q is the unit electron charge. I isS1And IS0Reverse saturation currents, I, of the third and second transistors, respectivelyE1And IE0Emitter currents of the third transistor and the second transistor, respectively.
In some exemplary embodiments, the second differential voltage V (dvbep, dvben) ═ V (dvbep) -V (dvben);
to obtain
In some exemplary embodiments, IS1And IS0In a certain proportional relationship, IE1And IE0In a certain proportion relation with each other,
is a constant.
In some exemplary embodiments, the second current source is M pieces of second current sources with the same size; according to a preset clock relationship, P of the M currents flow through the second transistor, and the rest M-P currents flow through the third transistor; the predetermined clock relationship ensures that the voltage difference generated by the M-P branch current flowing through the third transistor is transmitted to the dvbep end, and the voltage difference generated by the P branch current flowing through the second transistor is transmitted to the dvben end.
Accordingly, the number of the first and second electrodes,
equal to (M-P)/P; i isS1And IS0Is a value related to the size of the second transistor and the third transistor, and when the transistor size ratio is determined,
is determined.
When the second transistor and the third transistor are the same size transistor or have the same specification (i.e., the second transistor and the third transistor are the same size transistor or have the same specification)
) Generating a second differential voltage from a second current source, comprising:
the second differential voltage
In some exemplary embodiments, when P ═ 1,
the generating a second differential voltage from a second current source includes:
the second differential voltage
In some exemplary embodiments, before determining the feedback signal corresponding to the voltage to be measured, the method further includes:
and judging whether the voltage to be measured is within a preset voltage range, and when the voltage to be measured is determined to exceed the preset voltage range, carrying out amplitude adjustment on the voltage to be measured according to a preset voltage amplitude gain to obtain the adjusted voltage to be measured. I.e. the adjusted voltage to be measured
V(vsp，vsn)＝gain*V(voltage_sensp，voltage_sensn)；
The Voltage-sensing circuit comprises a Voltage-sensing circuit, a Voltage-sensing circuit and a gain circuit, wherein V (Voltage _ senp, Voltage _ senn) is a Voltage to be detected before adjustment, Voltage _ senp and Voltage _ senn are a positive input end and a negative input end of a Voltage signal to be detected before adjustment, and gain is a preset Voltage amplitude gain.
The embodiment of the present disclosure further provides a voltage sensing device, including:
a differential voltage generation module configured to: generating a first differential voltage according to a first current source and a second differential voltage according to a second current source;
a first feedback module configured to: determining a feedback signal Kadc according to the voltage V (vsp, vsn) to be measured, the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg, so that an average value Kadc _ va of the feedback signal satisfies the following relation:
V(vsp，vsn)-Kadc_va*V(vbep，vben)-Kadc_va*kvbg*V(dvbep，dvben)＝0 (1)；
a voltage determination module configured to: determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured;
wherein vbep is a positive terminal voltage of the first differential voltage, and vben is a negative terminal voltage of the first differential voltage; the dvbep is the positive terminal voltage of the second differential voltage, and the dvben is the negative terminal voltage of the second differential voltage; and vsp is the positive end voltage of the voltage to be measured, and vsn is the negative end voltage of the voltage to be measured.
The first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg satisfy the following bandgap reference voltage relationship:
the bandgap reference voltage Vbg ═ V (vbep, vben) + kvbg × (dvbp, dvbn). (2)
In some exemplary embodiments, the apparatus further comprises a clock module configured to generate the multi-phase non-overlapping clock signal Adc _ clk and the clock reference signal CK _ vref according to an input clock signal. In some exemplary embodiments, the multi-phase non-overlapping clock signals are generated as shown in FIG. 3.
Dividing the multiphase non-overlapping clock signals into two groups, wherein 1-n phase clocks are one group, and each latter phase clock in the group of clocks is delayed by a first preset delay time td compared with the rising edge of the former phase clock; the n +1 th-2 n phase clocks are a group, and each next phase clock in the group of clocks is delayed by a first preset delay time td compared with the rising edge of the previous phase clock;
the rising edge of the first phase clock of the second group of clocks is delayed by a first preset delay time td from the falling edge of the last phase clock of the first group of clocks; the rising edge of the first phase clock of the first set of clocks is delayed by a first preset delay time td from the falling edge of the last phase clock of the second set of clocks.
In some exemplary embodiments, the voltage determination module is further configured to:
according to a preset cut-off frequency, low-pass filtering is carried out on a feedback signal corresponding to the voltage to be measured, and multi-bit filtering data are obtained; the multi-bit filtering data is an average value representation of the voltage to be measured;
and amplifying the filtering data according to a preset voltage detection gain, adding the amplified filtering data with a preset voltage detection offset, and determining a digital value of the voltage to be detected.
In some exemplary embodiments, the differential voltage generation module includes a first differential circuit and a second differential circuit:
the first differential circuit is configured to generate the first differential voltage based on the first current source and the first transistor
Wherein ICIs the collector current of the first transistor, ISIs the first transistor reverse saturation current.
In some exemplary embodiments, the second differential circuit is configured to generate the second differential voltage according to the second current source and a second transistor and a third transistor.
Wherein the second differential circuit generates two different Vbe voltage outputs, denoted dvbep and dvben.
dvbep and dvben can be represented by the following formulas:
dvbep and dvben yield a differential voltage value V (dvbep, dvben) that can be expressed by the following equation:
where K is the Boltzmann constant, T is the absolute temperature, and q is the unit electron charge. I isS1And IS0Reverse saturation currents, I, of the third and second transistors, respectivelyE1And IE0Emitter currents of the third transistor and the second transistor, respectively.
In some exemplary embodiments, IS1And IS0In a certain proportional relationship, IE1And IE0In a certain proportional relationship. By alternating the current sources through the two BJTs and alternating the source of VBE. The generated reference voltages (differential voltages) are sent to the first feedback module for averaging operation, so that the purpose of eliminating deviation and mismatch between BJTs and between current sources is achieved.
In some exemplary embodiments, the second current source is M pieces of second current sources with the same size;
according to a preset clock relationship, P of the M currents flow through the second transistor, and the rest M-P currents flow through the third transistor; the predetermined clock relationship ensures that the voltage difference generated by the M-P branch current flowing through the third transistor is transmitted to the dvbep end, and the voltage difference generated by the P branch current flowing through the second transistor is transmitted to the dvben end.
Accordingly, the number of the first and second electrodes,
equal to (M-P)/P; i isS1And IS0Is a value related to the size of the second transistor and the third transistor, and when the transistor size ratio is determined,
is determined.
When the second transistor and the third transistor are the same transistor or have the same specification, the generating a second differential voltage according to the second current source includes:
the second differential voltage
In some exemplary embodiments, when P ═ 1,
the second differential voltage
In some exemplary embodiments, the first differential circuit is configured to generate the first differential voltage from the first current source;
wherein the first differential circuit has a first transistor; the first current source provides current to the first transistor; the first current source is connected with an emitter of the first transistor to form a first output node, a base of the first transistor is connected with a collector of the first transistor and grounded to form a second output node, and the first differential voltage is output from the first output node and the second output node;
alternatively, the first differential circuit has a first transistor; the first current source provides current to the first transistor; the first current source is connected to a collector of the first transistor and a base of the first transistor to form a first output node, an emitter of the first transistor is grounded to form a second output node, and the first differential voltage is output from the first output node and the second output node.
The second differential circuit is configured to generate the second differential voltage from the second current source;
wherein the second differential circuit has a second transistor, a third transistor, a clock driving unit, a first control switch, and a second control switch;
the second current source is M second current sources with the same size;
the clock driving unit is used for accessing a clock reference signal and generating a clock driving control signal according to the clock reference signal;
the M second current sources with the same size are connected with the first control switch and used for providing M currents;
a first output end of the first control switch is connected with an emitter of the second transistor and a first input end of the second control switch, a second output end of the first control switch is connected with an emitter of the third transistor and a second input end of the second control switch, the first control switch is used for respectively enabling P branch currents in the M branch currents to flow into the second transistor and the rest (M-P) branch currents to flow into the third transistor under the control of the clock driving control signal, M is not less than 2, P is not less than 1, and M is greater than P;
the base of the second transistor is connected with the collector of the second transistor and grounded, the base of the third transistor is connected with the collector of the third transistor and grounded, and the output end of the second control switch is used for outputting the second differential voltage.
In some exemplary embodiments, as shown in fig. 4a, the first differential circuit has a first transistor Q0; the first current source Ibias0 provides current to the first transistor Q0; the first current source Ibias0 is connected to the emitter of the first transistor Q0 to form a first output node vbep, the base of the first transistor Q0 is connected to the collector of the first transistor Q0 and to ground to form a second output node vben, and the first differential voltage V (vbep, vben) is output from the first output node vbep and the second output node vben.
In some exemplary embodiments, as shown in fig. 4b, the first differential circuit has a first transistor Q0; the first current source Ibias0 provides current to the first transistor Q0; the first current source Ibias0 is connected to the collector of the first transistor Q0 and the base of the first transistor Q0 to form a first output node vbep, the emitter of the first transistor Q0 is grounded to form a second output node vben, and the first differential voltage V (vbep, vben) is output from the first output node vbep and the second output node vben.
The first transistor is a BJT, and may be a PNP type or an NPN type.
In some exemplary embodiments, as shown in fig. 5a, the second differential circuit 50 has a second transistor Q1, a third transistor Q2, a clock driving unit 501, a first control switch 502, and a second control switch 503;
the second current source is M second current sources I0< M-1: 0 >;
the clock driving unit is used for accessing a clock reference signal Ck _ vref and generating a clock driving control signal Ctl < m-1: 0> according to the clock reference signal;
the M second current sources with the same size are all connected to the first control switch 502 for providing M currents;
a first output end of the first control switch 502 is connected to an emitter of the second transistor Q1 and a first input end of the second control switch 503, a second output end of the first control switch 502 is connected to an emitter of the third transistor Q2 and a second input end of the second control switch 503, the first control switch 502 is used for respectively enabling P branch currents of the M branch currents to flow into the second transistor Q1 and the rest (M-P) branch currents to flow into the third transistor Q2 under the control of the clock driving control signal, wherein M is greater than or equal to 2, P is greater than or equal to 1, and M is greater than P;
the base of the second transistor Q1 is connected to the collector of the second transistor Q1 and ground, the base of the third transistor Q2 is connected to the collector of the third transistor Q2 and ground, and the output terminal of the second control switch 503 is used to output the second differential voltage V (dvbep, dvben).
In some exemplary embodiments, as shown in fig. 5b, the second differential circuit 50 has a second transistor Q1, a third transistor Q2, a clock driving unit 501, a first control switch 502, and a second control switch 503;
the second current source is M second current sources I0 with the same size, wherein the current sources I0 are more than M-1: 0 >;
the clock driving unit is used for accessing a clock reference signal Ck _ vref and generating a clock driving control signal Ctl < m-1 according to the clock reference signal: 0 >;
the M second current sources with the same size are all connected to the first control switch 502 for providing M currents;
a first output end of the first control switch 502 is connected to a collector and a base of the second transistor Q1 and a first input end of the second control switch 503, a second output end of the first control switch 502 is connected to a collector and a base of the third transistor Q2 and a second input end of the second control switch 503, the first control switch 502 is used for respectively enabling P branch currents of the M branch currents to flow into the second transistor Q1 and enabling the rest (M-P) branch currents to flow into the third transistor Q2 under the control of the clock driving control signal, wherein M is not less than 2, P is not less than 1, and M is more than P;
the emitter of the second transistor Q1 is grounded, the emitter of the third transistor Q2 is grounded, and the output terminal of the second control switch 503 is used for outputting the second differential voltage V (dvbep, dvben).
The second transistor and the third transistor are BJTs, and may be of PNP type or NPN type.
In some exemplary embodiments, where P is 1, then in conjunction with fig. 5a or 5b, one of the M currents is driven into Q1 and the remaining M-1 current is driven into Q2, respectively, under a clock driven by the reference clock signal ck _ vref. Say: at the 1 st moment, the 1 st branch current enters Q1, and the 2 nd to M branch currents enter Q2; at the 2 nd moment, the 2 nd branch current enters Q1, and the 1 st, 3 rd to M th branch currents enter Q2; by analogy, at the M-th moment, the M-th current enters Q1, and the 1-M-1-th current enters Q2. At the above 1 st to M th time points, the Vbe voltage of Q1 is connected to dvben, and the Vbe voltage of Q2 is connected to dvbep. Then, at the M +1 th moment, the 1 st branch current enters Q2, and the 2 nd to M th branch currents enter Q1; at the moment M +2, the 2 nd branch current enters Q2, and the 1 st, 3 rd-M branch currents enter Q1; by analogy, the M current enters Q2 at the 2M time, and the 1 st to M-1 current enters Q1. At the above M +1 to 2 × M times, the Vbe voltage of Q2 is connected to dvben, and the Vbe voltage of Q1 is connected to dvbep. In this implementation, Q1 and Q2 are the same size and the M current sources are the same size when manufacturing variations are not taken into account.
Thus V (dvbep, dvben) can be expressed as the following equation:
if manufacturing variations are taken into account, then the average over 2 × M moments can be expressed as follows:
thereby obtaining:
Δkindicates the mismatch ratio at the k-th configuration. This mismatch ratio follows a gaussian distribution. Thus, it is possible to provide
Therefore, it is possible to obtain:
in some exemplary embodiments, the differential voltage generation module further includes: and the voltage adjustment module to be measured is set to judge whether the voltage to be measured is within a preset voltage range or not, and when the voltage to be measured is determined to exceed the preset voltage range, the voltage to be measured is subjected to amplitude adjustment according to preset voltage amplitude gain to obtain the adjusted voltage to be measured. As shown in fig. 6, the relationship between the input voltage V (voltage _ senp, voltage _ senn) before adjustment (differential form) and the output voltage V (vsp, vsn) after adjustment satisfies the following relational expression:
V(vsp，vsn)＝gain*V(voltage_sensp，voltage_sensn)；
the Voltage _ sensp and the Voltage _ senn are positive and negative input ends of a Voltage signal to be detected before adjustment, and gain is a preset Voltage amplitude gain.
In some exemplary embodiments, the first feedback module includes an arithmetic operation unit, a mean unit, and a quantization unit.
The arithmetic operation unit is configured to perform the following operation according to a voltage to be measured V (vsp, vsn), the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvben), the first gain coefficient kvbg and a feedback signal Kadc fed back by the quantization unit to obtain a first transient voltage Vt;
Vt＝V(vsp，vsn)+Kadc*V(vben，vbep)-Kadc*kvbg*V(dvbep，dvben) (12)
when V (vben, vbep) — V (vbep, vben), the deformation is
Vt＝V(vsp，vsn)-Kadc*V(vbep，vben)-Kadc*kvbg*V(dvbep，dvben) (12’)
The mean unit is configured to perform cumulative summation on the first transient voltage Vt according to a clock signal;
the quantization unit is configured to quantize according to the accumulated summation result of the averaging unit to obtain the feedback signal, and includes: and comparing the accumulated and summed result with a differential voltage reference to obtain the feedback signal Kadc.
In some exemplary embodiments, as shown in fig. 7, the arithmetic operation unit includes a first multiplexer U1, a second multiplexer U2, a first gain amplifier U3, and a first accumulator U4; the first multiplexer U1 is configured to selectively output the inverted first differential voltage and the 0V voltage signal according to control of the feedback signal; the second multiplexer U2 is used for selectively outputting the second differential voltage and the 0V voltage signal according to the control of the feedback signal; the first gain amplifier U3 is connected to the second multiplexer U2, and is configured to gain amplify the output of the second multiplexer U2 by a preset first gain factor kvbg; one positive phase input end of the first accumulator U4 is connected to the output end of the first multiplexer U1, the other positive phase input end of the first accumulator U4 is connected to the voltage to be measured, one inverted phase input end of the first accumulator U4 is connected to the output end of the first gain amplifier U3, and the positive phase input end of the first accumulator U4 is used for accumulating the output U' of the first multiplexer, the voltage to be measured, and the inverted phase output of the first gain amplifier U3 to obtain the first transient voltage Vt.
In some exemplary embodiments, the averaging unit comprises an integrator Z, as shown in fig. 7-1And a second accumulator U5, one input terminal of the second accumulator U5 is connected with the output terminal of the arithmetic operation unit, and the other input terminal of the second accumulator U5 is connected with the integrator Z-1An output of the second accumulator U5 is connected to an input of the quantization unit and to the integrator Z-1To the input terminal of (1).
In some exemplary embodiments, as shown in fig. 7, the quantization unit includes a comparator U6, a first inverter U7, and a second inverter U8; one input end of the comparator U6 is connected with one output end of the averaging unit, the other input end of the comparator is connected with the differential voltage reference (0), and the output end of the comparator U6 is connected with the input end of the first inverter U7; the output end of the first inverter U7 is connected with the input end of the second inverter U8. The output of the comparator U6 outputs the feedback signal, and the output of the second inverter U8 also outputs the feedback signal, i.e., a 1-bit stream signal.
In some exemplary embodiments, as shown in fig. 8, the voltage determination module includes a Low pass filter 801(Low pass filter), 802(Gain _ filter), and a third accumulator 803; the low-pass filter is set to obtain multi-bit filtering data for the feedback signal (Adc _1bit _ o) according to a preset cut-off frequency; the input end of the second gain amplifier is connected with the output end of the low-pass filter and is used for amplifying the filtering data according to a preset voltage detection gain; two positive input ends of the third accumulator are connected to the output end of the second gain amplifier and the input preset voltage detection offset0, and are used for accumulating the output of the second gain amplifier and the voltage detection offset0 to obtain a digitized value ADC _ out corresponding to the voltage to be measured.
The embodiment of the present disclosure further provides a voltage detection method, as shown in fig. 1, including:
step 11, determining a feedback signal Kadc corresponding to the voltage to be measured according to the voltage to be measured V (vsp, vsn), the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain coefficient kvbg, and averaging the feedback signal Kadc
Step 12, determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured;
wherein the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg satisfy the following bandgap reference voltage relationship:
the bandgap reference voltage Vbg ═ V (vbep, vben) + kvbg × (dvbp, dvbn). (2)
In some exemplary embodiments, the average value of the feedback signal corresponding to the voltage to be measured
In some exemplary embodiments, the determining the digitized value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured includes:
according to a preset cut-off frequency, low-pass filtering is carried out on a feedback signal corresponding to the voltage to be measured, and multi-bit filtering data are obtained; the multi-bit filtering data is an average value representation of the voltage to be measured;
and amplifying the filtering data according to a preset voltage detection gain, adding the amplified filtering data with a preset voltage detection offset, and determining a digital value of the voltage to be detected.
In some exemplary embodiments, the generating the first differential voltage according to the first current source includes:
generating the first differential voltage according to the first current source and the first transistor
Wherein ICIs the collector current of the first transistor, ISIs the first transistor reverse saturation current.
In some exemplary embodiments, said generating a second differential voltage according to a second current source comprises:
generating the second differential voltage according to the second current source, the second transistor and the third transistor
Where K is the Boltzmann constant, T is the absolute temperature, and q is the unit electron charge. I isS1，IS0The reverse saturation currents of the third transistor and the second transistor, respectively. I isE1And IE0Emitter currents of the third transistor and the second transistor, respectively.
In some exemplary embodiments, the second transistor and the third transistor have the same specification;
the second current source is M second current sources with the same size; according to a preset clock relationship, P branches of the M branches of currents flow through the second transistor, and the rest M-P branches of currents flow through the third transistor;
the generating a second differential voltage from a second current source includes:
determining the voltage difference generated by the M-P branch currents flowing through the third transistor as the positive end voltage of the second differential voltage according to the preset clock relationship; according to the preset clock relationship, determining the voltage difference generated when the P branch currents flow through the second transistor as the negative terminal voltage of the second differential voltage to obtain the second differential voltage
Wherein K is Boltzmann's constant, T is absolute temperature, and q is unit electron charge; (ii) a M is more than or equal to 2, P is more than or equal to 1, and M is more than P.
In some exemplary embodiments, the determining, according to the voltage to be measured, the first differential voltage, the second differential voltage, and a preset first gain coefficient, a feedback signal corresponding to the voltage to be measured includes:
determining a first transient voltage according to the voltage to be measured, the first differential voltage, the second differential voltage and the first gain coefficient;
and accumulating and summing the first transient voltage according to a clock signal, and comparing the summed result with a preset differential voltage reference to obtain the feedback signal.
In some exemplary embodiments, the clock signals are multi-phase non-overlapping clock signals;
the clock signals are divided into two groups, wherein 1-n phase clocks are one group, and each next phase clock in the group of clocks delays a first preset delay time than the rising edge of the previous phase clock; the n + 1-2 n phase clocks are a group, and each next phase clock in the group of clocks is delayed by a first preset delay time compared with the rising edge of the previous phase clock;
the rising edge of a first phase clock of the second group of clocks is delayed by a first preset delay time than the falling edge of the last phase clock of the first group of clocks; the rising edge of a first phase clock of the first set of clocks is delayed by a first preset delay time from the falling edge of the last phase clock of the second set of clocks.
In some exemplary embodiments, the differential voltage reference is 0.
In some exemplary embodiments, before determining the feedback signal corresponding to the voltage to be measured, the method further includes:
and judging whether the voltage to be measured is within a preset voltage range, and when the voltage to be measured is determined to exceed the preset voltage range, carrying out amplitude adjustment on the voltage to be measured according to a preset voltage amplitude gain to obtain the adjusted voltage to be measured.
In some exemplary embodiments, the generating the first differential voltage according to the first current source includes: generating the first differential voltage by a first differential circuit according to the first current source;
wherein the first differential circuit has a first transistor; the first current source provides current to the first transistor; the first current source is connected with an emitter of the first transistor to form a first output node, a base of the first transistor is connected with a collector of the first transistor and grounded to form a second output node, and the first differential voltage is output from the first output node and the second output node;
alternatively, the first differential circuit has a first transistor; the first current source provides current to the first transistor; the first current source is connected to a collector of the first transistor and a base of the first transistor to form a first output node, an emitter of the first transistor is grounded to form a second output node, and the first differential voltage is output from the first output node and the second output node.
In some exemplary embodiments, said generating a second differential voltage according to a second current source comprises: generating the second differential voltage by a second differential circuit according to the second current source;
wherein the second differential circuit has a second transistor, a third transistor, a clock driving unit, a first control switch, and a second control switch;
the second current source is M second current sources with the same size;
the clock driving unit is used for accessing a clock reference signal and generating a clock driving control signal according to the clock reference signal;
the M second current sources with the same size are connected with the first control switch and used for providing M currents;
a first output end of the first control switch is connected with an emitter of the second transistor and a first input end of the second control switch, a second output end of the first control switch is connected with an emitter of the third transistor and a second input end of the second control switch, the first control switch is used for respectively enabling P branch currents in the M branch currents to flow into the second transistor and enabling the rest (M-P) branch currents to flow into the third transistor under the control of the clock driving control signal, M is not less than 2, P is not less than 1, and M is greater than P;
the base electrode of the second transistor is connected with the collector electrode of the second transistor and grounded, the base electrode of the third transistor is connected with the collector electrode of the third transistor and grounded, and the output end of the second control switch is used for outputting the second differential voltage;
or, wherein the second differential circuit has a second transistor, a third transistor, a clock driving unit, a first control switch, and a second control switch;
the second current source is M second current sources with the same size;
the clock driving unit is used for accessing a clock reference signal and generating a clock driving control signal according to the clock reference signal;
the M second current sources with the same size are connected with the first control switch and used for providing M currents;
the first output end of the first control switch is connected with the collector and the base of the second transistor and the first input end of the second control switch, the second output end of the first control switch is connected with the collector and the base of the third transistor and the second input end of the second control switch, the first control switch is used for respectively enabling P branch currents in the M branch currents to flow into the second transistor under the control of the clock driving control signal, the rest (M-P) branch currents flow into the third transistor, M is not less than 2, P is not less than 1, and M is more than P;
the emitter of the second transistor is grounded, the emitter of the third transistor is grounded, and the output end of the second control switch is used for outputting the second differential voltage.
The embodiment of the present disclosure further provides a voltage sensing device, including:
a differential voltage generation module configured to: generating a first differential voltage according to a first current source and a second differential voltage according to a second current source;
a first feedback module configured to: determining a feedback signal Kadc according to the voltage V (vsp, vsn) to be measured, the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg, so that an average value Kadc _ va of the feedback signal Kadc satisfies the following feedback relationship:
V(vsp，vsn)-Kadc_va*V(vbep，vben)-Kadc_va*kvbg*V(dvbep，dvben)＝0； (1)
a voltage determination module configured to: determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured;
wherein the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg satisfy the following bandgap reference voltage relationship:
the bandgap reference voltage Vbg ═ V (vbep, vben) + kvbg × (dvbp, dvbn). (2)
In some exemplary embodiments, the voltage determination module is further configured to:
according to a preset cut-off frequency, low-pass filtering is carried out on a feedback signal corresponding to the voltage to be measured, and multi-bit filtering data are obtained; the multi-bit filtering data is an average value representation of the voltage to be measured;
and amplifying the filtering data according to a preset voltage detection gain, adding the amplified filtering data with a preset voltage detection offset, and determining a digital value of the voltage to be detected.
In the method provided by the embodiment of the disclosure, a feedback signal Kadc corresponding to a voltage to be measured is determined according to the voltage to be measured, the first differential voltage, the second differential voltage and a preset first gain coefficient, so that an average value Kadc _ va of the feedback signal Kadc meets a preset feedback relation; determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured; the first differential voltage, the second differential voltage, the preset first gain coefficient and the band gap reference voltage meet a preset band gap reference voltage relation. According to the scheme, the average value of the feedback signal representing the average value of the voltage to be measured is generated, and then the digital value of the voltage to be measured is determined.
According to the voltage detection scheme provided by the embodiment of the disclosure, the linear relation between the average value Kadc _ va of the feedback signal Kadc and the voltage to be detected is ensured through the preset feedback relation, and further, the determination of the digital value of the voltage to be detected according to the average value of the feedback signal can be realized. According to the detection scheme provided by the embodiment of the disclosure, voltage detection can be realized without a band gap reference circuit and an off-chip reference voltage source, the digital value of the voltage to be detected is determined, and the cost and the power consumption can be effectively reduced.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (14)
1. A voltage detection method, comprising:
generating a first differential voltage according to a first current source and a second differential voltage according to a second current source;
determining a feedback signal Kadc corresponding to the voltage to be measured according to the voltage to be measured V (vsp, vsn), the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain coefficient kvbg, and enabling the average value of the feedback signal Kadc to be equal to the average value
Determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured;
wherein the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg satisfy the following bandgap reference voltage relationship:
the bandgap reference voltage Vbg ═ V (vbep, vben) + kvbg × (dvbp, dvbn).
2. The method of claim 1,
average value of feedback signals corresponding to the voltage to be measured
3. The method of claim 2,
the determining the digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured includes:
according to a preset cut-off frequency, low-pass filtering is carried out on a feedback signal corresponding to the voltage to be measured, and multi-bit filtering data are obtained; the multi-bit filtering data is an average value representation of the voltage to be measured;
and amplifying the filtering data according to a preset voltage detection gain, adding the amplified filtering data with a preset voltage detection offset, and determining a digital value of the voltage to be detected.
4. The method according to claim 1, 2 or 3,
the generating a first differential voltage from a first current source includes:
generating the first differential voltage according to the first current source and the first transistor
Wherein ICIs the collector current of the first transistor, ISIs the first transistor reverse saturation current.
5. The method according to claim 1, 2 or 3,
the generating a second differential voltage from a second current source includes:
generating the second differential voltage according to the second current source, the second transistor and the third transistor
Wherein K is Boltzmann constantT is absolute temperature, and q is unit electron charge; i isS1，IS0Reverse saturation currents of the third transistor and the second transistor, respectively; i isE1And IE0Emitter currents of the third transistor and the second transistor, respectively.
6. The method of claim 5,
the second transistor and the third transistor have the same specification;
the second current source is M second current sources with the same size; according to a preset clock relationship, P branches of the M branches of currents flow through the second transistor, and the rest M-P branches of currents flow through the third transistor;
the generating a second differential voltage from a second current source includes:
determining the voltage difference generated by the M-P branch currents flowing through the third transistor as the positive end voltage of the second differential voltage according to the preset clock relationship; according to the preset clock relationship, determining the voltage difference generated when the P branch currents flow through the second transistor as the negative terminal voltage of the second differential voltage to obtain the second differential voltage
Wherein K is Boltzmann's constant, T is absolute temperature, and q is unit electron charge; (ii) a M is more than or equal to 2, P is more than or equal to 1, and M is more than P.
7. The method according to claim 1, 2 or 3,
the determining a feedback signal corresponding to the voltage to be measured according to the voltage to be measured, the first differential voltage, the second differential voltage and a preset first gain coefficient includes:
determining a first transient voltage according to the voltage to be measured, the first differential voltage, the second differential voltage and the first gain coefficient;
and accumulating and summing the first transient voltage according to a clock signal, and comparing the summed result with a preset differential voltage reference to obtain the feedback signal.
8. The method of claim 7,
the clock signal is a multi-phase non-overlapping clock signal;
the clock signals are divided into two groups, wherein 1-n phase clocks are one group, and each next phase clock in the group of clocks delays a first preset delay time than the rising edge of the previous phase clock; the n + 1-2 n phase clocks are a group, and each next phase clock in the group of clocks is delayed by a first preset delay time compared with the rising edge of the previous phase clock;
the rising edge of a first phase clock of the second group of clocks is delayed by a first preset delay time than the falling edge of the last phase clock of the first group of clocks; the rising edge of a first phase clock of the first set of clocks is delayed by a first preset delay time from the falling edge of the last phase clock of the second set of clocks.
9. The method of claim 7,
the differential voltage reference is 0.
10. The method according to claim 1, 2 or 3,
before determining the feedback signal corresponding to the voltage to be measured, the method further includes:
and judging whether the voltage to be measured is within a preset voltage range, and when the voltage to be measured is determined to exceed the preset voltage range, carrying out amplitude adjustment on the voltage to be measured according to a preset voltage amplitude gain to obtain the adjusted voltage to be measured.
11. The method according to claim 1, 2 or 3,
the generating a first differential voltage from a first current source includes: generating the first differential voltage by a first differential circuit according to the first current source;
wherein the first differential circuit has a first transistor; the first current source provides current to the first transistor; the first current source is connected with an emitter of the first transistor to form a first output node, a base of the first transistor is connected with a collector of the first transistor and grounded to form a second output node, and the first differential voltage is output from the first output node and the second output node;
alternatively, the first differential circuit has a first transistor; the first current source provides current to the first transistor; the first current source is connected to a collector of the first transistor and a base of the first transistor to form a first output node, an emitter of the first transistor is grounded to form a second output node, and the first differential voltage is output from the first output node and the second output node.
12. The method according to claim 1, 2 or 3,
the generating a second differential voltage from a second current source includes: generating the second differential voltage by a second differential circuit according to the second current source;
wherein the second differential circuit has a second transistor, a third transistor, a clock driving unit, a first control switch, and a second control switch;
the second current source is M second current sources with the same size;
the clock driving unit is used for accessing a clock reference signal and generating a clock driving control signal according to the clock reference signal;
the M second current sources with the same size are connected with the first control switch and used for providing M currents;
a first output end of the first control switch is connected with an emitter of the second transistor and a first input end of the second control switch, a second output end of the first control switch is connected with an emitter of the third transistor and a second input end of the second control switch, the first control switch is used for respectively enabling P branch currents in the M branch currents to flow into the second transistor and enabling the rest (M-P) branch currents to flow into the third transistor under the control of the clock driving control signal, M is not less than 2, P is not less than 1, and M is greater than P;
the base electrode of the second transistor is connected with the collector electrode of the second transistor and grounded, the base electrode of the third transistor is connected with the collector electrode of the third transistor and grounded, and the output end of the second control switch is used for outputting the second differential voltage;
or, wherein the second differential circuit has a second transistor, a third transistor, a clock driving unit, a first control switch, and a second control switch;
the second current source is M second current sources with the same size;
the clock driving unit is used for accessing a clock reference signal and generating a clock driving control signal according to the clock reference signal;
the M second current sources with the same size are connected with the first control switch and used for providing M currents;
the first output end of the first control switch is connected with the collector and the base of the second transistor and the first input end of the second control switch, the second output end of the first control switch is connected with the collector and the base of the third transistor and the second input end of the second control switch, the first control switch is used for respectively enabling P branch currents in the M branch currents to flow into the second transistor under the control of the clock driving control signal, the rest (M-P) branch currents flow into the third transistor, M is not less than 2, P is not less than 1, and M is more than P;
the emitter of the second transistor is grounded, the emitter of the third transistor is grounded, and the output end of the second control switch is used for outputting the second differential voltage.
13. A voltage sensing apparatus, comprising:
a differential voltage generation module configured to: generating a first differential voltage according to a first current source and a second differential voltage according to a second current source;
a first feedback module configured to: determining a feedback signal Kadc according to the voltage V (vsp, vsn) to be measured, the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg, so that an average value Kadc _ va of the feedback signal Kadc satisfies the following feedback relationship:
V(vsp,vsn)-Kadc_va*V(vbep,vben)-Kadc_va*kvbg*V(dvbep，dvben)＝0；
a voltage determination module configured to: determining a digital value of the voltage to be measured according to the average value of the feedback signal corresponding to the voltage to be measured;
wherein the first differential voltage V (vbep, vben), the second differential voltage V (dvbp, dvbn) and a preset first gain factor kvbg satisfy the following bandgap reference voltage relationship:
the bandgap reference voltage Vbg ═ V (vbep, vben) + kvbg × (dvbp, dvbn).
14. The voltage sensing apparatus of claim 13,
the voltage determination module is further configured to:
according to a preset cut-off frequency, low-pass filtering is carried out on a feedback signal corresponding to the voltage to be measured, and multi-bit filtering data are obtained; the multi-bit filtering data is an average value representation of the voltage to be measured;
and amplifying the filtering data according to a preset voltage detection gain, adding the amplified filtering data with a preset voltage detection offset, and determining a digital value of the voltage to be detected.
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