CN112671408B

CN112671408B - Temperature and voltage sensor, chip and electronic equipment

Info

Publication number: CN112671408B
Application number: CN202011596187.8A
Authority: CN
Inventors: 吴启明; 马鑫; 林晓志
Original assignee: Gowin Semiconductor Corp
Current assignee: Gowin Semiconductor Corp
Priority date: 2020-12-29
Filing date: 2020-12-29
Publication date: 2021-09-17
Anticipated expiration: 2040-12-29
Also published as: CN112671408A

Abstract

The invention provides a temperature voltage sensor, a chip and electronic equipment, wherein the temperature voltage sensor comprises an analog-to-digital conversion module and a reference voltage generation module which are integrated in the same chip, the reference voltage generation module can provide a plurality of reference voltages, and the analog-to-digital conversion module can receive a mode control signal for selecting a voltage sensor mode or a temperature sensor mode, and carry out corresponding operation processing on a voltage input signal and the plurality of reference voltages to obtain required temperature information or voltage information. According to the invention, a band gap reference circuit and an off-chip reference voltage source are not needed, a plurality of reference voltages can be provided for the analog-to-digital conversion module in the chip by directly utilizing the reference voltage generation module in the chip, and the mode configuration is carried out on the analog-to-digital conversion module through the mode control signal, so that the same sensor can realize two modes of a temperature sensor and a voltage sensor, the area of the chip can be saved, the power consumption and the cost are reduced, and the measurement precision is improved.

Description

Temperature and voltage sensor, chip and electronic equipment

Technical Field

The invention relates to the technical field of sensor design, in particular to a temperature and voltage sensor, a chip and electronic equipment.

Background

As chip manufacturing processes advance, chips are developed toward smaller sizes and lower power supply voltages. The thermal effect effects of the chip are gradually being brought up to the research routine. In order to avoid overheating the chip and thus adversely affect the performance of the chip, a temperature sensor is integrated inside the chip to monitor the temperature of the chip in real time.

At present, the following methods are mainly used for integrating a temperature sensor inside a chip:

one is to use a thermistor, which is relatively versatile, but has limited accuracy.

Secondly, a voltage reference is generated by a bandgap reference circuit, and a voltage representing temperature is quantized by an Analog-to-Digital Converter (ADC, or referred to as a/D Converter), such as a Junction voltage VBE between a base B and an emitter E of a Bipolar Junction Transistor (BJT), so as to achieve the purpose of temperature detection through a corresponding relationship between voltage and temperature. This approach has the following drawbacks: (1) the cost is increased due to the arrangement of the band-gap reference circuit and the like, more chip area is consumed, and larger power consumption is brought; (2) because the random manufacturing deviation of the bandgap reference circuit causes a large error of the temperature sensor and has low precision, for some high-precision applications, the chip needs to be further equipped with an off-chip reference voltage source, thereby increasing the cost additionally.

Furthermore, the above problems also exist in some applications that require the on-chip integration of a voltage sensor, because the common way to integrate a voltage sensor on-chip is to use a bandgap reference circuit or an off-chip reference voltage source as the reference voltage source of the ADC. This approach is similar to the second approach of integrating the temperature sensor on the chip, and has the disadvantages of low accuracy, high cost, and high power consumption.

Moreover, with the further popularization of the internet of things, people have higher and higher requirements on the sensor, and in daily application, the sensor is expected to have more acquisition parameters, small size, high precision, low power consumption, low cost, strong anti-interference capability and the like. The traditional sensor is not competent, and the integrated sensor perfectly combined with the integrated circuit process is produced at the moment and integrated on a chip, so that the integrated sensor has the advantages of multiple acquisition parameters, low cost, high precision, low power consumption and high anti-interference capability, and can well meet the application of the Internet of things.

Disclosure of Invention

The invention aims to provide a temperature and voltage sensor, a chip and electronic equipment, which can be compatible with the acquisition of temperature and voltage parameters and avoid the use of a band gap reference circuit and an off-chip reference voltage source so as to reduce the cost and the power consumption.

In order to solve the above technical problem, the present invention provides a temperature-voltage sensor, which includes an analog-to-digital conversion module and a reference voltage generation module integrated in the same chip, wherein the reference voltage generation module is configured to provide a plurality of reference voltages for the analog-to-digital conversion module; the analog-to-digital conversion module is used for receiving a mode control signal, a voltage input signal and the reference voltages, and performing corresponding operation processing on the reference voltages and the voltage input signal to obtain required temperature information or voltage information, wherein the mode control signal is used for selecting a voltage sensor mode or a temperature sensor mode.

Optionally, the temperature-voltage sensor further includes a voltage buffer module integrated in the chip, and an output end of the voltage buffer module is connected to a corresponding input end of the analog-to-digital conversion module, and is configured to receive a differential voltage input signal, and process the differential voltage input signal into a differential voltage input signal allowed by a voltage input range of the analog-to-digital conversion module, so as to serve as the voltage input signal and provide the voltage input signal to the analog-to-digital conversion module.

Optionally, the voltage buffer module comprises a first gain amplifier.

Optionally, the temperature-voltage sensor further includes a clock module integrated in the chip, the clock module is connected to the reference voltage generation module and the analog-to-digital conversion module, and the clock module is configured to receive a corresponding clock input signal, and generate a multi-phase non-overlapping clock signal required by the analog-to-digital conversion module and a clock reference signal required by the reference voltage generation module according to the clock input signal, respectively, so that the reference voltage generation module generates a corresponding reference voltage under the control of the clock reference signal, and the analog-to-digital conversion module outputs the result of the operation processing and a clock output signal corresponding to the result of the operation processing under the control of the multi-phase non-overlapping clock signal.

Optionally, the reference voltage generating module includes a first reference voltage generating circuit and a second reference voltage generating circuit capable of outputting the plurality of reference voltages, and the first reference voltage generating circuit has a first transistor and a first current source for supplying a current to the first transistor, and the first transistor is configured to generate two paths of differential reference voltages according to the current supplied by the first current source; the second reference voltage generating circuit is provided with a second transistor, a third transistor and a second current source used for providing current for the second transistor and the third transistor respectively, and the second transistor and the third transistor are used for generating two paths of differential reference voltages according to the current provided by the second current source.

Optionally, the first reference voltage generating circuit further includes a first capacitor, the first current source is connected to the emitter of the first transistor and one end of the first capacitor to form a first output node for outputting the corresponding differential reference voltage, and the base of the first transistor is connected to the collector of the first transistor and the other end of the first capacitor and grounded to form a second output node for outputting the corresponding differential reference voltage.

Optionally, the second reference voltage generating circuit has M second current sources with the same size, and the second reference voltage generating circuit further includes a clock driving unit, a first control switch and a second control switch, where:

the clock driving unit is used for accessing a clock reference signal and generating a clock driving control signal according to the clock reference signal;

the M second current sources with the same size are connected with the first control switch and used for providing M currents;

a first output end of the first control switch is connected with an emitter of the second transistor and a first input end of the second control switch, a second output end of the first control switch is connected with an emitter of the second transistor and a second input end of the second control switch, the first control switch is used for respectively enabling P branch currents in the M branch currents to flow into the second transistor and other (M-P) branch currents to flow into the third transistor under the control of the clock driving control signal, M is not less than 2, P is not less than 1, M is more than P, and M, P are integers;

the base electrode of the second transistor is connected with the collector electrode of the second transistor and grounded, the base electrode of the third transistor is connected with the collector electrode of the third transistor and grounded, and the output end of the second control switch is used for outputting the other two paths of differential reference voltages.

Optionally, the analog-to-digital conversion module includes:

an arithmetic operation unit for performing operation processing on the plurality of reference voltages and the voltage input signal under control of the mode control signal;

the integration unit is connected with the arithmetic operation unit and is used for carrying out integration operation on the operation processing result of the arithmetic operation unit;

and the quantization unit is connected with the integration unit and used for quantizing the output of the integration unit to obtain a 1-bit stream signal representing the voltage input signal.

Optionally, the quantization unit comprises a comparator, a first inverter and a second inverter; two input ends of the comparator are connected with two output ends of the integrating unit or one input end of the comparator is connected with one output end of the integrating unit, the other input end of the comparator is connected with a comparison reference signal, and the output end of the comparator is connected with the input end of the first phase inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter outputs the 1-bit stream signal.

Optionally, the arithmetic operation unit includes first to fifth multiplexers, a second gain amplifier, and a first accumulator; the first multiplexer is connected with the first reference voltage generating circuit and used for selectively outputting the two paths of differential reference voltages output by the first reference voltage generating circuit according to the control of the mode control signal; the second multiplexer is used for selectively outputting the voltage input signal and the 0V voltage signal according to the control of the mode control signal; the third multiplexer is connected with the first multiplexer and the output end of the comparator and used for selectively outputting the output of the first multiplexer and the 0V voltage signal according to the control of the output of the comparator; the fifth multiplexer is connected with the output end of the comparator and the output end of the first inverter and is used for selectively outputting the output of the comparator and the output of the first inverter; the fourth multiplexer is connected with the second reference voltage generating circuit and the fifth multiplexer and is used for selectively outputting the output of the second reference voltage generating circuit and the 0V voltage signal according to the control of the output of the fifth multiplexer; the second gain amplifier is connected with the fourth multiplexer and is used for performing gain amplification on the output of the fourth multiplexer; the first accumulator is connected with the output end of the second multiplexer, the output end of the third multiplexer and the output end of the second gain amplifier, and is used for accumulating the output of the second multiplexer, the output of the third multiplexer and the output of the second gain amplifier to obtain a corresponding operation processing result; alternatively, the first and second electrodes may be,

the arithmetic operation unit comprises two parallel operation branches, and each operation branch comprises a first multiplexer, a second multiplexer, a fifth multiplexer, a second gain amplifier and a first accumulator; the first multiplexer is connected with the first reference voltage generating circuit and used for selectively outputting the two paths of differential reference voltages output by the first reference voltage generating circuit according to the control of the mode control signal; the second multiplexer is used for selectively outputting one path of differential input signals and 0V voltage signals in the voltage input signals according to the control of the mode control signal; the third multiplexer is connected with the first multiplexer and the output end of the comparator and used for selectively outputting the output of the first multiplexer and the 0V voltage signal according to the control of the output of the comparator; the fifth multiplexer is connected with the output end of the comparator and the output end of the first inverter and is used for selectively outputting the output of the comparator and the output of the first inverter; the fourth multiplexer is connected with the second reference voltage generating circuit and the fifth multiplexer and is used for selectively outputting one path of differential reference voltage and 0V voltage signal output by the second reference voltage generating circuit according to the control of the output of the fifth multiplexer; the second gain amplifier is connected with the fourth multiplexer and is used for performing gain amplification on the output of the fourth multiplexer; the first accumulator is connected with the output end of the second multiplexer, the output end of the third multiplexer and the output end of the second gain amplifier, and is used for accumulating the output of the second multiplexer, the output of the third multiplexer and the output of the second gain amplifier to obtain a path of operation processing result signal.

Optionally, the clock module is further configured to generate an offset control signal for averaging an offset error of the integration unit according to the clock input signal.

Optionally, the integration unit includes a first offset control switch, an operational amplifier, a second offset control switch, a first integration capacitor and a second integration capacitor, two input terminals of the first offset control switch are respectively connected to two differential output terminals of the arithmetic operation unit, two output terminals of the first offset control switch are respectively connected to positive and negative input terminals of the operational amplifier, two output terminals of the second offset control switch are respectively connected to positive and negative output terminals of the operational amplifier and two input terminals of the quantization unit, the first integration capacitor is connected between one input terminal of the first offset control switch and one output terminal of the second offset control switch, and the second integration capacitor is between the other input terminal of the first offset control switch and the other output terminal of the second offset control switch, the control ends of the first offset control switch and the second offset control switch are connected with the clock module so as to access the offset control signal.

Optionally, the integrating unit includes an integrator and a second accumulator, one input end of the second accumulator is connected to the output end of the arithmetic operation unit, the other input end of the second accumulator is connected to the output end of the second accumulator, and the output end of the second accumulator is connected to the input end of the quantization unit and the input end of the integrator.

Optionally, the quantization unit further outputs a clock output signal corresponding to the 1-bit stream signal while outputting the 1-bit stream signal; the temperature and voltage sensor also comprises a filtering output module integrated in the chip, and the filtering output module is used for converting the clock output signal and the 1bit stream signal into the temperature information or the voltage information to be output under the control of the mode control signal.

Optionally, the filtering output module includes a low-pass filter, a third gain amplifier, a bias multiplexer, and a third accumulator, where the low-pass filter is connected to the third gain amplifier, and both the third gain amplifier and the bias multiplexer are connected to the third accumulator; the low-pass filter is used for performing low-pass filtering processing on the clock output signal and the 1bit stream signal under the control of the mode control signal and processing the signals into multi-bit signals; the third gain amplifier is used for selecting a corresponding gain value under the control of the mode control signal and carrying out gain amplification on the multi-bit signal; the offset multiplexer is used for selecting a corresponding offset value under the control of the mode control signal; the third accumulator is configured to accumulate an output of the third gain amplifier and an output of the offset multiplexer to obtain the temperature information or the voltage information.

Based on the same inventive concept, the invention also provides a chip, and the temperature and voltage sensor is integrated in the chip.

Based on the same inventive concept, the invention also provides electronic equipment which is provided with the chip.

Compared with the prior art, the technical scheme of the invention has one of the following technical effects:

1. the band-gap reference circuit and the off-chip reference voltage source are not needed, the reference voltage generating module in the chip can be directly utilized to provide a plurality of reference voltages for the analog-to-digital conversion module in the chip, the analog-to-digital conversion module is configured in a mode through a mode control signal, and the analog-to-digital conversion module can carry out temperature information operation or voltage information operation on the plurality of reference voltages and corresponding voltage input signals, so that the same sensor can realize two modes of a temperature sensor and a voltage sensor, namely, the multi-mode can be supported, and the acquisition and measurement of multiple parameters can be supported.

2. The use of the band-gap reference circuit is avoided, so that the chip area can be saved, the power consumption can be reduced, the measurement error of the sensor caused by the random deviation of the band-gap reference circuit is avoided, and the measurement precision is improved.

3. The cost can be reduced since the use of an off-chip reference voltage source is avoided.

Drawings

Fig. 1 is a schematic system structure diagram of a temperature-voltage sensor according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a voltage buffer module of a temperature-voltage sensor according to an embodiment of the invention.

FIG. 3 is a timing diagram of a multi-phase non-overlapping clock signal generated by a clock module of a temperature-voltage sensor according to an embodiment of the invention.

Fig. 4 is a schematic circuit diagram of a first reference voltage generating circuit of a reference voltage generating module of a temperature-voltage sensor according to an embodiment of the invention.

Fig. 5 is a schematic circuit diagram of a second reference voltage generating circuit of the reference voltage generating module of the temperature-voltage sensor according to an embodiment of the invention.

Fig. 6 is a schematic circuit diagram of an analog-to-digital conversion module of a temperature-voltage sensor according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of a linear curve of an operation result KAdc _ va of the analog-to-digital conversion module of the temperature-voltage sensor according to an embodiment of the invention and a temperature T to be measured.

Fig. 8 is a schematic diagram of a linear curve of the operation result KAdc _ va of the analog-to-digital conversion module of the temperature-voltage sensor according to the embodiment of the invention and the voltage V to be measured.

Fig. 9 is a schematic circuit diagram of a filter output module of a temperature-voltage sensor according to an embodiment of the present invention.

Fig. 10 is a schematic system structure diagram of a temperature-voltage sensor according to another embodiment of the present invention.

Fig. 11 is a schematic circuit diagram of an analog-to-digital conversion module of a temperature-voltage sensor according to another embodiment of the present invention.

Detailed Description

The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Referring to fig. 1, an embodiment of the invention provides a temperature-voltage sensor, which includes a voltage buffer module 11, a clock module 12, a reference voltage generation module 13, an analog-to-digital conversion (ADC) module 14, and a filtering output module 15 integrated in a same chip.

In this embodiment, the signals to be detected are two differential Voltage input signals, Voltage _ sensp and Voltage _ sensn, and the Voltage buffer module 11 is configured to receive the two differential Voltage input signals, Voltage _ sensp and Voltage _ sensn, and process the two differential Voltage input signals, Voltage _ sensp and Voltage _ sensn, into differential Voltage input signals vsp and vsn allowed by a Voltage input range (or referred to as a Voltage amplitude) of the analog-to-digital conversion module 14, so as to serve as Voltage input signals required by the analog-to-digital conversion module 14 and provide the Voltage input signals to the analog-to-digital conversion module 14. I.e. the differential voltage input signals vsp and vsn are differential voltage input signals suitable for the voltage input range of the analog to digital conversion module 14. Optionally, referring to fig. 2, the Voltage buffer module 11 includes a first gain amplifier 110, which gains and amplifies the differential Voltage input signals Voltage _ sensp and Voltage _ senn to the input range of the analog-to-digital conversion module 14 to obtain differential Voltage input signals vsp and vsn, which can be collectively referred to as the Voltage input signals V (vsp, vsn).

The clock module 12 is configured to receive a corresponding clock input signal ADC _ clk _ i, and generate a multiphase non-overlapping clock signal ADC _ clk required by the analog-to-digital conversion module 14 and a clock reference signal Ck _ vref required by the reference voltage generation module 13 according to the clock input signal ADC _ clk _ i, so as to meet requirements of the analog-to-digital conversion module 14 on clock multiphase and meet requirements of the reference voltage generation module 13 on the clock reference signal. Wherein the multiphase non-overlapping clock signals are as shown in figure 3. In each phase of non-overlapping clock signals Adc _ clk <1>, Adc _ clk <2>, … …, Adc _ clk < n >, the interval time between rising edges or falling edges of non-overlapping clock signals of adjacent phases is td (td >0), while in each phase of non-overlapping clock signals Adc _ clk < n +1>, Adc _ clk < n +2> … … Adc _ clk <2> n >, the interval time between rising edges or falling edges of non-overlapping clock signals of adjacent phases is td (td > 0). The time interval between the falling edge of the non-overlapping clock signal Adc _ clk < n > and the rising edge of the non-overlapping clock signal Adc _ clk < n +1> is also td. The time interval between the falling edge of the non-overlapping clock signal Adc _ clk <2 x n > and the rising edge of the non-overlapping clock signal Adc _ clk <1> is also td. According to the requirement of the analog-to-digital conversion module 14 for multiple phases of the clock, the clock module 12 can generate four-phase, six-phase, … …, 2 × n-phase non-overlapping clock signals, where n is greater than or equal to 1.

Referring to fig. 1, fig. 4 and fig. 5, the reference voltage generating module 13 generates a plurality of reference voltages vbep, vben, dvbp and dvben under the control of the clock reference signal Ck _ vref, and provides the reference voltages vbep, vben, dvben to the analog-to-digital converting module 14. In this embodiment, the reference voltage generating module 13 includes a first reference voltage generating circuit 13a and a second reference voltage generating circuit 13b capable of outputting the plurality of reference voltages.

Specifically, referring to fig. 4, the first reference voltage generating circuit 13a includes a first current source Ibias0, a first transistor Q0 and a first capacitor C0, the first current source Ibias0 is connected to the emitter of the first transistor Q0 and one end of the first capacitor C0 to form a first output node NA, the base of the first transistor Q0 is connected to the collector of the first transistor Q0 and the other end of the first capacitor C0 and to ground to form a second output node N_B. The first current source Ibias0 is used to provide current to the first transistor Q0, and the current provided by the first current source Ibias0 passes through the base-emitter junction (i.e. BE junction) of the first transistor Q0 to generate two differential reference voltages vbep, vben, and the voltage difference between the two differential reference voltages vbep, vben is the base-emitter junction voltage vbe of Q0, and because of the voltage difference between the two differential reference voltages vbep, vbenA capacitor C0 connected across the first output node N_AAnd a second output node N_BTherefore, the voltage difference vbe between the reference voltages vbep and vben can be stabilized.

Referring to fig. 1 and 5, the second reference voltage generating circuit 13b has a second transistor Q1, a third transistor Q2, and a second current source for respectively providing currents to the second transistor Q1 and the third transistor Q2, the second transistor Q1 and the third transistor Q2 are used for generating two different base-emitter junction voltages Vbe0 and Vbe1 according to the current provided by the second current source, i.e. two different differential reference voltages dvbep and dvben, and the differential reference voltages dvbep and dvben can be represented by the following formulas:

further, the two differential reference voltages dvbep and dvben can be collectively denoted as V (dvbep, dvben), and can be expressed as the following equation:

where K is the Boltzmann constant, T is the absolute temperature, and q is the unit electron charge. I is_s1、I_s0Which are reverse saturation currents of the second transistor Q1 and the third transistor Q2, respectively. I is_E1And I_E0Emitter currents of the second transistor Q1 and the third transistor Q2, respectively.

In general I_s1、I_s0In a certain proportional relationship, I_E1And I_E0Proportional, but for manufacturing reasons, there may be deviations and mismatches between the second transistor Q1 and the third transistor Q2 and between the current sources to which the transistors Q1, Q2 are connected. In the present embodiment, the current is selectively passed through the second transistor Q1 by turnsAnd the current sources of the two transistors of the third transistor Q2, and the sources of the Vbe are changed in turn, namely the Vbe0 and the Vbe1 are selected in turn, and then the reference voltages are averaged, so that the aim of eliminating deviation and mismatch between BJTs and between the current sources is fulfilled.

As an example, referring to fig. 4, the second reference voltage generating circuit 13b includes a clock driving unit 131, M equal-sized second current sources I0< M-1:0>, a first control switch 132, a second control switch 133, a second transistor Q1, and a third transistor Q2. A first output terminal of the first control switch 132 is connected to an emitter of the second transistor Q1 and a first input terminal of the second control switch 133, a second output terminal of the first control switch 132 is connected to an emitter of the second transistor Q1 and a second input terminal of the second control switch 133, a base of the second transistor Q1 is connected to a collector of the second transistor Q1 and grounded, a base of the third transistor Q2 is connected to a collector of the third transistor Q2 and grounded, and an output terminal of the second control switch 133 is configured to output differential reference voltages dvben and dvbep. Wherein M is an integer.

The clock driving unit 131 is configured to access the clock reference signal Ck _ vref generated by the clock module 12, and generate a first clock driving control signal Ctl < m-1:0> and a second clock driving control signal polar according to the clock reference signal Ck _ vref. The M second current sources I0< M-1:0> with the same size are all connected to the first control switch 132, and are configured to provide M currents, where M is M; the first control switch 132 is driven by a first clock driving control signal Ctl < M-1:0> to enable P of the M currents to enter a second transistor Q1 and the rest (M-P) currents to enter a third transistor Q2, wherein M is larger than or equal to 2, P is larger than or equal to 1, M is larger than P, and M, P are integers; the second control switch 133 outputs the Vbe voltage of the second transistor Q1 and the Vbe voltage of the third transistor Q2 as differential reference voltages dvben and dvbep, respectively, driven by the second clock driving control signal polar.

For example, when P is 1, at the 1 st time, the 1 st current of the M currents enters the second transistor Q1, and the 2 nd to M currents enter the third transistor Q2; at the 2 nd moment, the 2 nd branch current enters the second transistor Q1, and the 1 st and 3 rd to M branch currents enter the third transistor Q2; by analogy, at the Mth moment, the Mth branch current enters the second transistor Q1, and the 1 st to M-1 st branch currents enter the third transistor Q2. At the above 1 st to mth time points, the Vbe voltage output of the second transistor Q1 is the differential reference voltage dvben, and the Vbe voltage output of the third transistor Q2 is the differential reference voltage dvbep. Then, at the moment M +1, the 1 st branch current enters the third transistor Q2, and the 2 nd to M th branch currents enter the second transistor Q1; at the moment M +2, the current of the 2 nd branch enters a third transistor Q2, and the currents of the 1 st branch and the 3 rd branch and the M th branch enter a second transistor Q1; by analogy, at the 2 × M time, the mth branch current enters the third transistor Q2, and the 1 st to M-1 st branches current enter the second transistor Q1. At the above-mentioned M +1 to 2 × M time, the Vbe voltage output of the third transistor Q2 is the differential reference voltage dvben, and the Vbe voltage output of the second transistor Q1 is the differential reference voltage dvbep. In this implementation, the second transistor Q1 and the third transistor Q2 have the same size and the M-branch current sources have the same size, without considering manufacturing variations. Thus V (dvbep, dvben) can be expressed as the following equation:

if manufacturing variations are taken into account, then the average over 2 × M moments can be expressed as follows:

thereby obtaining:

Δ _ k represents the mismatch ratio at the k-th configuration. This mismatch ratio follows a gaussian distribution. Thus, it is possible to provide

Therefore, it is possible to obtain:

thus, the effect of mismatch on the reference voltage can be reduced in this way.

It should be noted that, the first transistor Q0, the second transistor Q1, and the third transistor Q2 may all be bipolar junction transistors BJT, triodes, or MOS transistors, and when the first transistor Q0, the second transistor Q1, and the third transistor Q2 are MOS transistors, the base of the above transistors is the gate of the MOS transistor, the emitter of the transistor is the source of the MOS transistor, and the collector of the transistor is the drain of the MOS transistor.

Referring to fig. 1 and 6, the analog-to-digital conversion module 14 is configured to receive a mode control signal Adc _ mode, differential voltage input signals vsp and vsn, and respective differential reference voltages vben, vbp, dvben and dvbep, perform a temperature information operation or a voltage information operation on the plurality of reference voltages vben, vbp, dvben and the voltage input signal V (vsp, vsn) under the control of the mode control signal Adc _ mode and the multiphase non-overlapping clock signal Adc _ clk, and output a result of the operation to obtain a 1-bit stream Adc _1bit _ o representing the voltage input signal V (vsp, vsn), and simultaneously send out a clock signal Adc _ clk _ o associated with (i.e., corresponding to) the Adc _1bit _ o, so that the filter output module 15 can output corresponding temperature information or voltage information.

In this embodiment, the analog-to-digital conversion module 14 includes an arithmetic operation unit 141, an integration unit 142, and a quantization unit 143.

The arithmetic operation unit 141 is configured to perform operation processing on each of the reference voltages V (vben, vbep), V (dvvben, dvbp) output by the reference voltage generation module and the voltage input signal V (vben, vbep) under control of a mode control signal Adc _ mode, where the mode control signal Adc _ mode is used to select a voltage sensor mode or a temperature sensor mode, and the arithmetic operation unit 141 can implement different operation processing under control of the mode control signal Adc _ mode. The integration unit 142 is connected to the arithmetic operation unit 141, and is configured to perform an integration operation on the operation processing result of the arithmetic operation unit 141. The quantization unit 143 is connected to the integration unit 142, and configured to quantize the output of the integration unit 142 to obtain a 1-bit stream signal Adc _1bit _ o representing the voltage input signal. In addition, the quantization unit 143 outputs the clock output signal Adc _ clk _ o corresponding to the 1-bit stream signal Adc _1bit _ o while outputting the 1-bit stream signal Adc _1bit _ o.

As an example, referring to FIG. 6, the arithmetic operation unit 141 includes first to fifth multiplexers U1-U5, a second gain amplifier U6 and a first accumulator U7, and the integration unit 142 includes an integrator Z^-1And a second accumulator U8, the quantization unit 143 including a comparator U9, first to fourth inverters U10 to U13.

In this example, referring to fig. 1 to fig. 6, specifically, two input terminals of the first multiplexer U1 are connected to two output terminals of the first reference voltage generating circuit 13a, and the first multiplexer U1 is configured to selectively output the two differential reference voltages vben and vbep output by the first reference voltage generating circuit 13a according to the control of the mode control signal Adc _ mode. Two input ends of the second multiplexer U2 are connected to two output ends of the voltage buffer module 11, and are configured to selectively output the differential voltage input signals vsp, vsn and the 0V voltage signal output by the voltage buffer module 11 according to the control of the mode control signal Adc _ mode. One input end of a third multiplexer U3 is connected with the output end of the first multiplexer U1, the other input end is connected with a 0V voltage signal, a control end is connected with the output end of a comparator U9, and the third multiplexer U3 is used for selectively outputting the output of the first multiplexer U1 and the 0V voltage signal under the control of the output of the comparator U9. Two input ends of a fifth multiplexer U5 are respectively connected to the output end of the comparator U9 and the output end of the first inverter U10, a control end is connected to a mode control signal Adc _ mode, and the fifth multiplexer U5 is configured to selectively output the output of the comparator U9 and the output of the first inverter U10. One input end of the fourth multiplexer U4 is connected to two output ends of the second reference voltage generating circuit 13b, the other input end is connected to the 0V voltage signal, the control end is connected to the output end of the fifth multiplexer U5, and the fourth multiplexer U4 is configured to selectively output the output of the second reference voltage generating circuit 13b and the 0V voltage signal according to the control of the output of the fifth multiplexer U5. The input end of the second gain amplifier U6 is connected to the fourth multiplexer U4, the output end is connected to one input end of the first accumulator U7, and the second gain amplifier U6 is used for gain amplification of the output of the fourth multiplexer U4. The other input end of the first accumulator U7 is connected to the output end of the second multiplexer U2, and the other input end thereof is connected to the output end of the third multiplexer U3, and the first accumulator U7 is configured to accumulate the output of the second multiplexer U2, the output of the third multiplexer U3, and the output of the second gain amplifier U6 to obtain a corresponding operation result.

The second accumulator U8 has one input connected to the output of the first accumulator U7 and another input connected to the integrator Z^-1The output of the second accumulator U8 is connected to the integrator Z^-1And the positive input (+) of the comparator U9. Integrator Z^-1Used for integrating the output result of the first accumulator U7 and feeding back the result to the second accumulator U8, and the second accumulator U8 is used for integrating the output of the first accumulator U7 and the integrator Z^-1The output of (a) is accumulated. The accumulation calculation of the first accumulator U7 and the second accumulator U8 includes addition, subtraction or a combination of addition and subtraction. Integrator Z^-1The integrator may be an analog integrator or a digital integrator, and may be implemented by any suitable analog circuit design or digital circuit design known to those skilled in the art, which can perform the integration operation and feedback of the output result of the first accumulator U7.

A positive input terminal (+) of the comparator U9 is connected to the output terminal of the integration unit 142, a negative input terminal (-) of the comparator U9 is connected to a comparison reference signal a0, the comparison reference signal a0 may be a 0-value signal, or other level signal or pulse signal, etc., an output terminal of the comparator U9 is connected to an input terminal of the first inverter U10 and a control terminal of the third multiplexer U3, a control terminal of the comparator U9 is connected to the output terminal of the clock module 12, and the comparator U9 is configured to compare the magnitude between the output of the integration unit 142 and the comparison reference signal a0 under the control of the multiphase non-overlapping clock signals to output an operation result (i.e., a signal) KAdc.

The output end of the first inverter U10 is connected to the input end of the second inverter U11, the first inverter U10 is used for inverting the signal KAdc to output the signal KAdc _ b, and the output end of the second inverter U11 is used for inverting the signal KAdc _ b to output the signal Adc _1bit _ o, so that it can be seen that the 1bit stream signal Adc _1bit _ o is KAdc. An input terminal of the third inverter U12 is connected to an output terminal of the clock module 12, an output terminal of the third inverter U12 is connected to an input terminal of the fourth inverter U13, the third inverter U12 is configured to invert the output of the multi-phase non-overlapping clock signal Adc _ clk, and the fourth inverter U13 is configured to invert the output of the third inverter U12 and output the inverted output as a clock output signal Adc _ clk _ o corresponding to the 1-bit stream signal Adc _1bit _ o.

In the temperature sensor mode, the analog-to-digital conversion module 14 may implement the following arithmetic expression:

where KAdc _ va represents the average value of Adc _1bit _ o, Kvbg is a gain factor, and makes the following:

Vbg＝V(vbep,vben)+kvbg*V(dvbep,dvben)

where Vbg is the bandgap reference voltage of the equivalent bandgap reference circuit, so that:

kvbg × V (dvbep, dvben) is a voltage quantity proportional to the temperature T, and vbg is a bandgap voltage, so that a corresponding temperature value can be obtained according to KAdc _ va. As shown in FIG. 7, KAdc _ va is a value that is linear with temperature T, one temperature T corresponding to one KAdc _ va value.

In the voltage sensor mode, the analog-to-digital conversion module 14 may implement the following arithmetic expression:

Vbg＝V(vbep,vben)+kvbg*V(dvbep,dvben)

v (vsp, vsn) is the voltage to be measured, and vbg is the bandgap voltage, so that the corresponding relationship between voltage and KAdc _ va can be obtained from KAdc _ va. As shown in FIG. 8, KAdc _ va is a value that is linear with the voltage V to be measured, one voltage V corresponding to one KAdc _ va value.

As can be seen from the above, the arithmetic operation unit 141 of the analog-to-digital conversion module 14 actually performs operation processing on the plurality of reference voltages provided by the reference voltage generation module 13 to generate a high-precision constant reference voltage source suitable for the temperature sensor mode or the voltage sensor mode, thereby avoiding the existing scheme of using the bandgap reference circuit or the off-chip reference voltage source as the reference voltage source of the analog-to-digital conversion module, further saving the chip area and the power consumption consumed by the setting of the bandgap reference circuit, avoiding the problem of large measurement error of the sensor caused by the random manufacturing deviation of the bandgap reference circuit, and avoiding the additional cost increased by the need of additionally providing an off-chip reference voltage source.

Based on the linear relationship between the temperature sensor mode and the voltage sensor mode, the filter output module 15 is used to convert the output of the analog-to-digital conversion module 14 into the finally required measured temperature information (i.e. temperature value) or voltage information (voltage value).

In this embodiment, referring to fig. 9, the filtering output module 15 includes a low pass filter 151, a third gain amplifier 152, an offset multiplexer 153, and a third accumulator 154. One input end of the low-pass filter 151 is connected to the 1-bit stream signal Adc _1bit _ o output by the analog-to-digital conversion module 14, the other input end is connected to the clock output signal Adc _ clk _ o output by the analog-to-digital conversion module 14, and the control end is connected to the mode control signal Adc _ mode, where the low-pass filter 151 is configured to perform low-pass filtering processing on the clock output signal Adc _ clk _ o and the 1-bit stream signal Adc _1bit _ o under the control of the mode control signal Adc _ mode, and process the signals into a multi-bit signal filter _ o. An input end of the third gain amplifier 152 is connected to an output end of the low pass filter 151, an output end of the third gain amplifier 152 is connected to an input end of a third accumulator 154, a control end of the third gain amplifier 152 is connected to the mode control signal Adc _ mode, the third gain amplifier 152 is configured to select a corresponding gain value under control of the mode control signal Adc _ mode, and perform gain amplification on the multi-bit signal filter _ o, specifically, in the temperature sensor mode, the selected gain value can convert the multi-bit signal filter _ o into a corresponding temperature signal according to a linear relationship between KAdc _ va and a temperature T to be measured, and in the voltage sensor mode, the selected gain value can convert the multi-bit signal filter _ o into a corresponding voltage signal according to a linear relationship between KAdc _ va and a voltage V to be measured. An input terminal of the offset multiplexer 153 is connected to a corresponding offset value signal, a control terminal is connected to a mode control signal Adc _ mode, an output terminal of the offset multiplexer 153 is connected to another input terminal of the third accumulator 154, and the offset multiplexer 153 is used for selecting an offset value offset0 or offset1 suitable for a temperature sensor mode or suitable for a voltage sensor mode under the control of the mode control signal Adc _ mode. The third accumulator 154 is used for performing an accumulation calculation on the output of the third gain amplifier 152 and the output of the offset multiplexer 153 to obtain more accurate temperature information or voltage information Adc _ out.

In the solution of this embodiment, the voltage buffer module 11, the clock module 12, the reference voltage generation module 13, the analog-to-digital conversion module 14, and the filter output module 15 are all integrated in the same chip, and a bandgap reference circuit and an off-chip reference voltage source are not needed, and the analog-to-digital conversion module 14 may perform an operation on a plurality of reference voltages provided by the reference voltage generation module 13 to generate a high-precision constant reference voltage source suitable for a temperature sensor mode or a voltage sensor mode, and implement mode configuration by using a mode control signal Adc _ mode, thereby finally implementing compatibility between the temperature sensor and the voltage sensor.

It should be noted that, although the temperature-voltage sensor in the above-mentioned embodiment includes the voltage buffer module 11, the clock module 12, the reference voltage generation module 13, the analog-to-digital conversion module (ADC)14, and the filtering output module 15, in other embodiments of the present invention, the arrangement of the voltage buffer module 11, the clock module 12 and the filtering output module 15 can be omitted according to the requirement of practical application, for example, an electronic device has integrated therein a microprocessor chip and a temperature-voltage sensor chip of the present invention, and the microprocessor chip can have the functions of the voltage buffer module 11, the clock module 12 and the filtering output module 15, therefore, the voltage buffer module 11, the clock module 12 and the filter output module 15 can be omitted from the sensor chip, and the functions realized by the voltage buffer module 11, the clock module 12 and the filter output module 15 can be realized by the microprocessor chip.

In addition, it should be noted that, in the above embodiments, the specific circuit designs of the voltage buffer module 11, the clock module 12, the reference voltage generating module 13, the analog-to-digital conversion module 14 and the filtering output module 15 are only used as examples, and the technical solution of the present invention is not limited to the above-mentioned circuit designs, and those skilled in the art can select a suitable circuit design to perform corresponding replacement according to needs. For example, when the integrating unit in the analog-to-digital conversion module 14 is implemented by an analog integrator, the circuit design of the clock module 12 may be enabled to generate the offset control signal chop for averaging the offset error of the analog integrator while generating the multiphase non-overlapping clock signal Adc _ clk required by the analog-to-digital conversion module 14 and the clock reference signal Ck _ vref required by the reference voltage generating module 13.

Specifically, referring to fig. 10 and 11, another embodiment of the present invention provides a temperature-voltage sensor, which includes a voltage buffer module 11, a clock module 12, a reference voltage generation module 13, an analog-to-digital conversion module (ADC)14, and a filter output module 15 integrated in the same chip. The analog-to-digital conversion module (ADC)14 has an arithmetic operation unit 141, an integration unit 142, and a quantization unit 143, and the circuit designs of the voltage buffer module 11, the reference voltage generation module 13, the filter output module 15, and the quantization unit 143 may be completely the same as those in the above embodiments, and are not described herein again.

In this embodiment, the clock module 12 can generate a path of offset control signal chop according to the clock input signal ADC _ clk _ i, and the chop signal is a control signal for averaging the offset error of the integrating unit 142. The input and output of the arithmetic operation unit 141 and the integration unit 142 of the analog-to-digital conversion module (ADC)14 are implemented in a fully differential manner. As shown in fig. 10, the arithmetic operation unit 141 has two operation branches to output two differential operation result signals, and each operation branch has first to fifth multiplexers, a second gain amplifier and a first accumulator.

Specifically, in the first path of operation branch, two input ends of a first multiplexer U1 'are connected to two output ends of the first reference voltage generating circuit 13a, and the first multiplexer U1' is configured to selectively output the two paths of differential reference voltages vben and vbep output by the first reference voltage generating circuit 13a according to the control of the mode control signal Adc _ mode. An input end of the second multiplexer U21 is connected to an output end of the voltage buffer module 11, and is configured to selectively output the differential voltage input signal vsp and the 0V voltage signal output by the voltage buffer module 11 according to the control of the mode control signal Adc _ mode. One input end of a third multiplexer U31 is connected to the output end of the first multiplexer U1 ', the other input end is connected to a 0V voltage signal, a control end is connected to the output end of the comparator U9 of the quantization unit 143, and the third multiplexer U31 is configured to selectively output the output of the first multiplexer U1' and the 0V voltage signal under the control of the output of the comparator U9. Two input ends of the fifth multiplexer U51 are respectively connected to the output end of the comparator U9 of the quantization unit 143 and the output end of the first inverter U10, and a control end is connected to the mode control signal Adc _ mode, and the fifth multiplexer U51 is configured to selectively output the output of the comparator U9 and the output of the first inverter U10. One input end of the fourth multiplexer U41 is connected to one output end of the second reference voltage generating circuit 13b, the other input end is connected to the 0V voltage signal, the control end is connected to the output end of the fifth multiplexer U51, and the fourth multiplexer U41 is configured to selectively output the differential reference voltage dvbep and the 0V voltage signal output by the second reference voltage generating circuit 13b according to the control of the output of the fifth multiplexer U51. The input end of the second gain amplifier U61 is connected to the fourth multiplexer U41, the output end is connected to one input end of the first accumulator U71, and the second gain amplifier U61 is used for gain amplification of the output of the fourth multiplexer U41. The other input end of the first accumulator U71 is connected to the output end of the second multiplexer U21, and the other input end thereof is connected to the output end of the third multiplexer U31, and the first accumulator U71 is configured to accumulate the output of the second multiplexer U21, the output of the third multiplexer U31, and the output of the second gain amplifier U61 to obtain a differential operation processing result signal.

In the second path of operation branch, two input ends of a first multiplexer U1 ″ are connected to two output ends of the first reference voltage generating circuit 13a, and the first multiplexer U1 ″ is configured to selectively output the two paths of differential reference voltages vben and vbep output by the first reference voltage generating circuit 13a according to the control of the mode control signal Adc _ mode. One input end of the second multiplexer U22 is connected to the other output end of the voltage buffer module 11, and is configured to selectively output the differential voltage input signal vsn and the 0V voltage signal output by the voltage buffer module 11 according to the control of the mode control signal Adc _ mode. One input end of a third multiplexer U32 is connected to the output end of the first multiplexer U1 ", the other input end is connected to a 0V voltage signal, a control end is connected to the output end of the comparator U9 of the quantization unit 143, and the third multiplexer U32 is configured to selectively output the output of the first multiplexer U1" and the 0V voltage signal under the control of the output of the comparator U9. Two input ends of the fifth multiplexer U52 are respectively connected to the output end of the comparator U9 of the quantization unit 143 and the output end of the first inverter U10, and a control end is connected to the mode control signal Adc _ mode, and the fifth multiplexer U51 is configured to selectively output the output of the comparator U9 and the output of the first inverter U10. One input end of the fourth multiplexer U42 is connected to the other output end of the second reference voltage generating circuit 13b, the other input end is connected to the 0V voltage signal, the control end is connected to the output end of the fifth multiplexer U51, and the fourth multiplexer U42 is configured to selectively output the differential reference voltage dvben and the 0V voltage signal output by the second reference voltage generating circuit 13b according to the control of the output of the fifth multiplexer U52. The input end of the second gain amplifier U62 is connected to the fourth multiplexer U42, the output end is connected to one input end of the first accumulator U72, and the second gain amplifier U62 is used for gain amplification of the output of the fourth multiplexer U42. The other input end of the first accumulator U72 is connected to the output end of the second multiplexer U22, and the other input end is connected to the output end of the third multiplexer U32, and the first accumulator U72 is configured to accumulate the output of the second multiplexer U22, the output of the third multiplexer U32, and the output of the second gain amplifier U62 to obtain another differential operation processing result signal.

The integrating unit 142 comprises a first detuning control switch U82, an operational amplifier U81, a second detuning control switch U83, a first integrating capacitor C1 and a second integrating capacitor C2, wherein two input terminals of the first detuning control switch U82 are respectively connected with two differential output terminals of the arithmetic operation unit 141, two output terminals of the first detuning control switch U82 are respectively connected with positive and negative input terminals of the operational amplifier U81, two output terminals of the second detuning control switch U83 are respectively connected with positive and negative output terminals of the operational amplifier U81 and two input terminals of the quantization unit 143, the first integrating capacitor C1 is connected between one input terminal of the first detuning control switch U82 and one output terminal of the second detuning control switch U82, and the second integrating capacitor C2 is connected between the other input terminal of the first detuning control switch U82 and the other output terminal of the second detuning control switch U83, the control ends of the first offset control switch U82 and the second offset control switch U83 are both connected to the clock module 12 to access the offset control signal chop. The offset voltage is a fixed value because the operational amplifier U81 has an offset voltage that is typically fixed in relation to process manufacturing. With the first offset control switch U82 and the second offset control switch U83 as shown in fig. 11, the differential operation result signal of the positive and negative input terminals of the operational amplifier U81 can be selected to be connected to the arithmetic operation unit 141 in the forward and reverse directions and the quantization unit 143 of the positive and negative output terminals of the operational amplifier U81 can be selected to be connected in the forward and reverse directions at different times when the chop signal is "1" and "0". Assume that an offset voltage voffset _ op exists in the operational amplifier U81, and the offset voltage contributes to the charge of the integrating unit 142 at the forward access time as follows: w1 ═ Citg × voffset _ op, the contribution at the reverse access instant is: w0 ═ Citg × voffset _ op, Citg is a constant coefficient. Long-time charge integration does not accumulate after the first offset control switch U82 and the second offset control switch U83 are controlled to be switched by the chop signal, and a boundary value w1 or w0 exists, so that the accuracy can be improved.

Note that, the first offset control switch U82 and the second offset control switch U83 are provided to increase the processing accuracy of the integration unit 142, but the first offset control switch U82 and the second offset control switch U83 may be omitted if accuracy loss is allowed.

Based on the same inventive concept, please refer to fig. 1 to 11, an embodiment of the present invention further provides a chip, wherein the temperature and voltage sensor of the present invention is integrated in the chip.

Based on the same inventive concept, please refer to fig. 1 to 11, an embodiment of the invention further provides an electronic device having the chip of the invention.

In summary, according to the technical solution of the present invention, a bandgap reference circuit and an off-chip reference voltage source are not required, a reference voltage generation module in a chip can be directly used to provide a plurality of reference voltages for an analog-to-digital conversion module in the chip, and the analog-to-digital conversion module is configured in a mode through a mode control signal, so that the analog-to-digital conversion module can perform temperature information operation or voltage information operation on the plurality of reference voltages and corresponding voltage input signals under the control of the mode control signal, thereby enabling the same sensor to implement two modes of a temperature sensor and a voltage sensor. And because the use of a band gap reference circuit and an off-chip reference voltage source is avoided, the chip area can be saved, the power consumption and the cost are reduced, and the measurement precision is improved.

In addition, it should be noted that the terms "first", "second", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for representing a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.

It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

It is to be further understood that the present invention is not limited to the particular methodology, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.

Claims

1. The temperature and voltage sensor is characterized by comprising an analog-to-digital conversion module and a reference voltage generation module which are integrated in the same chip, wherein the reference voltage generation module is used for providing a plurality of reference voltages for the analog-to-digital conversion module; the analog-to-digital conversion module is used for receiving a mode control signal, a voltage input signal and the reference voltages, and performing corresponding operation processing on the reference voltages and the voltage input signal to obtain required temperature information or voltage information, wherein the mode control signal is used for selecting a voltage sensor mode or a temperature sensor mode; the temperature and voltage sensor further comprises a clock module integrated in the chip, the clock module is connected with the reference voltage generation module and the analog-to-digital conversion module, and the clock module is used for receiving corresponding clock input signals, respectively generating multiphase non-overlapping clock signals required by the analog-to-digital conversion module and clock reference signals required by the reference voltage generation module according to the clock input signals, so that the reference voltage generation module generates corresponding reference voltages under the control of the clock reference signals, and the analog-to-digital conversion module outputs the result of the operation processing and clock output signals corresponding to the result of the operation processing under the control of the multiphase non-overlapping clock signals.

2. The temperature-voltage sensor of claim 1, further comprising a voltage buffer module integrated within the chip, an output of the voltage buffer module being connected to a corresponding input of the analog-to-digital conversion module for receiving a differential voltage input signal and processing the differential voltage input signal into a differential voltage input signal allowed by a voltage input range of the analog-to-digital conversion module for providing as the voltage input signal to the analog-to-digital conversion module.

3. The temperature-voltage sensor of claim 2, wherein the voltage buffer module comprises a first gain amplifier.

4. The temperature-voltage sensor of claim 1, wherein the reference voltage generation module comprises a first reference voltage generation circuit and a second reference voltage generation circuit capable of outputting the plurality of reference voltages, and the first reference voltage generation circuit has a first transistor and a first current source for providing current to the first transistor, the first transistor is configured to generate two differential reference voltages according to the current provided by the first current source; the second reference voltage generating circuit is provided with a second transistor, a third transistor and a second current source used for providing current for the second transistor and the third transistor respectively, and the second transistor and the third transistor are used for generating two paths of differential reference voltages according to the current provided by the second current source.

5. The temperature-voltage sensor of claim 4, wherein the first reference voltage generating circuit further comprises a first capacitor, the first current source is connected to the emitter of the first transistor and one end of the first capacitor to form a first output node for outputting the corresponding differential reference voltage, the base of the first transistor is connected to the collector of the first transistor and the other end of the first capacitor and to ground to form a second output node for outputting the corresponding differential reference voltage.

6. The temperature-voltage sensor of claim 4, wherein the second reference voltage generating circuit has M second current sources of the same size, the second reference voltage generating circuit further comprising a clock driving unit, a first control switch, and a second control switch, wherein:

the clock driving unit is used for accessing the clock reference signal and generating a clock driving control signal according to the clock reference signal;

7. The temperature-voltage sensor of claim 1, wherein the analog-to-digital conversion module comprises:

8. The temperature-voltage sensor according to claim 7, wherein the quantization unit includes a comparator, a first inverter, and a second inverter; two input ends of the comparator are connected with two output ends of the integrating unit or one input end of the comparator is connected with one output end of the integrating unit, the other input end of the comparator is connected with a comparison reference signal, and the output end of the comparator is connected with the input end of the first phase inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter outputs the 1-bit stream signal.

9. The temperature-voltage sensor according to claim 8, wherein the arithmetic operation unit includes first to fifth multiplexers, a second gain amplifier, and a first accumulator; the first multiplexer is connected with the first reference voltage generating circuit and used for selectively outputting the two paths of differential reference voltages output by the first reference voltage generating circuit according to the control of the mode control signal; the second multiplexer is used for selectively outputting the voltage input signal and the 0V voltage signal according to the control of the mode control signal; the third multiplexer is connected with the first multiplexer and the output end of the comparator and used for selectively outputting the output of the first multiplexer and the 0V voltage signal according to the control of the output of the comparator; the fifth multiplexer is connected with the output end of the comparator and the output end of the first inverter and is used for selectively outputting the output of the comparator and the output of the first inverter; the fourth multiplexer is connected with the second reference voltage generating circuit and the fifth multiplexer and is used for selectively outputting the output of the second reference voltage generating circuit and the 0V voltage signal according to the control of the output of the fifth multiplexer; the second gain amplifier is connected with the fourth multiplexer and is used for performing gain amplification on the output of the fourth multiplexer; the first accumulator is connected with the output end of the second multiplexer, the output end of the third multiplexer and the output end of the second gain amplifier, and is used for accumulating the output of the second multiplexer, the output of the third multiplexer and the output of the second gain amplifier to obtain an operation processing result signal; alternatively, the first and second electrodes may be,

10. The temperature-voltage sensor of claim 8, wherein the clock module is further configured to generate an offset control signal for averaging an offset error of the integration unit based on the clock input signal.

11. The temperature-voltage sensor according to any one of claims 7 to 10, wherein the integrating unit includes an integrator and a second accumulator, one input terminal of the second accumulator is connected to the output terminal of the arithmetic operation unit, the other input terminal of the second accumulator is connected to the output terminal of the second accumulator, and the output terminal of the second accumulator is connected to the input terminal of the quantization unit and the input terminal of the integrator.

12. The temperature-voltage sensor according to claim 10, wherein the integration unit includes a first offset control switch, an operational amplifier, a second offset control switch, a first integration capacitor and a second integration capacitor, two input terminals of the first offset control switch are respectively connected to two differential output terminals of the arithmetic operation unit, two output terminals of the first offset control switch are respectively connected to positive and negative input terminals of the operational amplifier, two output terminals of the second offset control switch are respectively connected to positive and negative output terminals of the operational amplifier and two input terminals of the quantization unit, the first integration capacitor is connected between one input terminal of the first offset control switch and one output terminal of the second offset control switch, and the second integration capacitor is connected between the other input terminal of the first offset control switch and the other output terminal of the second offset control switch, the control ends of the first offset control switch and the second offset control switch are connected with the clock module so as to access the offset control signal.

13. The temperature-voltage sensor according to claim 7, wherein the quantization unit further outputs a clock output signal corresponding to the 1-bit stream signal at the same time as the 1-bit stream signal is output; the temperature and voltage sensor also comprises a filtering output module integrated in the chip, and the filtering output module is used for converting the clock output signal and the 1bit stream signal into the temperature information or the voltage information to be output under the control of the mode control signal.

14. The temperature-voltage sensor of claim 13, wherein the filter output module comprises a low pass filter, a third gain amplifier, a bias multiplexer, and a third accumulator, the low pass filter coupled to the third gain amplifier, the third gain amplifier and the bias multiplexer both coupled to the third accumulator; the low-pass filter is used for performing low-pass filtering processing on the clock output signal and the 1bit stream signal under the control of the mode control signal and processing the signals into multi-bit signals; the third gain amplifier is used for selecting a corresponding gain value under the control of the mode control signal and carrying out gain amplification on the multi-bit signal; the offset multiplexer is used for selecting a corresponding offset value under the control of the mode control signal; the third accumulator is configured to accumulate an output of the third gain amplifier and an output of the offset multiplexer to obtain the temperature information or the voltage information.

15. A chip, wherein the temperature-voltage sensor according to any one of claims 1 to 14 is integrated inside the chip.

16. An electronic device, characterized in that it has a chip as claimed in claim 15.