CN112769426A

CN112769426A - Noise suppression high-voltage level shift circuit based on time delay self-locking

Info

Publication number: CN112769426A
Application number: CN202110194269.8A
Authority: CN
Inventors: 刘天奇; 杨广文; 蔡畅; 陈更生; 甘霖
Original assignee: National Supercomputing Center In Wuxi
Current assignee: National Supercomputing Center In Wuxi
Priority date: 2021-02-20
Filing date: 2021-02-20
Publication date: 2021-05-07

Abstract

The invention provides a self-locking noise suppression circuit based on noise signal delay superposition, which can effectively suppress the propagation path of a noise signal by reasonably setting the locking pulse width of the noise signal without influencing the propagation of a normal working signal; and the circuit structure and the used modules are simple, the occupied area is small, and the reliability and the application value are higher.

Description

Noise suppression high-voltage level shift circuit based on time delay self-locking

Technical Field

The invention relates to a noise suppression high-voltage level shift circuit, in particular to a noise suppression high-voltage level shift circuit based on time delay self-locking.

Background

The high-voltage level shift circuit is mainly used for turning on a high-side MOSFET or IGBT power transistor and is a key circuit for converting a low-voltage logic signal into a high-voltage signal. In order to correctly turn on and off the high-side power transistor, the gate voltage V needs to be set_gsThe level range is shifted between the high voltage supply VB and the floating ground VS to ensure that the gate-source voltage difference is greater than the turn-on threshold voltage of the power transistor. For theIn a conventional narrow pulse triggered level shift circuit (fig. 1), the floating ground VS floats from 0V to a high voltage, which in turn generates dV/dt noise in the circuit. The large dV/dt noise can produce displacement currents through the drain parasitic capacitances of the two LDMOS power transistors, which can cause voltage drops across the series resistors R1 and R2, thereby producing false trigger signals at the a and B nodes. Fig. 2 is a typical noise signal propagation diagram, and for an ideal common mode noise signal generated at nodes a and B, the noise amplitude can reach the flip-flop through the filter circuit as long as the noise amplitude is large enough. The common mode noise signal reaches the RS flip-flop at the same time, which will cause the flip-flop to be in an uncertain operating state, thereby causing an output error. For noise signals containing significant differential mode components, the filter circuit can generally filter noise with relatively small pulse width, but the other path of noise can often directly cause the state of the trigger to change after passing through the filter circuit, so that the output state is wrong.

The reliability of the high-voltage level shift circuit is seriously threatened by the existence of dV/dt noise, and the power transistor can be directly turned on up and down due to false triggering, so that the device can be burnt seriously. In order to suppress the influence of noise signals on the circuit, researchers have proposed various circuit structures, such as a bypass capacitor common mode noise suppression circuit, a noise interlock circuit formed by a gate-source short-circuited LDMOS power transistor and a PMOS, or a noise suppression circuit formed by a plurality of differential amplifiers. For a bypass capacitor common mode noise suppression circuit, a high-voltage capacitor process is generally needed, the technical threshold of the circuit is high, and the circuit is difficult to implement. For a noise interlocking circuit formed by a grid-source short-circuit LDMOS power transistor and a PMOS, redundant LDMOS transistors occupy a large layout area, and the product cost is greatly increased. In addition, the noise suppression circuit using a plurality of differential amplifiers also faces the problems of matching and high voltage stability of the circuit, and has certain risks in specific applications.

Disclosure of Invention

The invention provides a noise suppression high-voltage level shift circuit based on time delay self-locking, which solves the problems in the prior art, can effectively suppress the propagation path of a noise signal, and does not influence the propagation of a normal working signal.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

the invention provides a noise suppression high-voltage level shift circuit based on time delay self-locking, which comprises an input port, a level shift circuit, a voltage clamping circuit, a filter circuit, a time delay self-locking circuit, an RS trigger, a drive circuit, an output port and a high-voltage bias port; the input ports include a first input port and a second input port; the level shift circuit comprises a first LDMOS transistor and a second LDMOS transistor; the voltage clamping circuit comprises a first clamping circuit and a second clamping circuit; the first input port is connected with the grid electrode of the first LDMOS transistor; the source electrode of the first LDMOS transistor is grounded, and the drain electrode of the first LDMOS transistor is connected with the high-voltage bias port through the first clamping circuit; the second input port is connected with the grid electrode of the second LDMOS transistor; the source electrode of the second LDMOS transistor is grounded, and the drain electrode of the second LDMOS transistor is connected with the high-voltage bias port through the second clamping circuit; the filter circuit comprises a first filter circuit and a second filter circuit; the drain electrode of the first LDMOS transistor is connected with the input end of the first filter circuit; the drain electrode of the second LDMOS transistor is connected with the input end of the second filter circuit; the delay self-locking circuit comprises a first input end, a second input end, a first output end and a second output end; the output end of the first filter circuit is connected with the first input end; the output end of the second filter circuit is connected with the second input end; the first output end is connected with the position end of the RS trigger; the second output end is connected with the reset end of the RS trigger; the output end of the RS trigger is connected with the input end of the driving circuit; the driving circuit is connected with the output port.

According to the noise suppression high-voltage level shift circuit based on the time delay self-locking, preferably, the first voltage clamping circuit comprises a first resistor and a plurality of first Zener diodes; all the first Zener diodes are connected in series in the same direction and are connected with the first resistor in parallel; the connection point of the first resistor and the anode of the first Zener diode forms the input end of the first voltage clamping circuit; the connection point of the first resistor and the cathode of the first Zener diode forms the output end of the first voltage clamping circuit; the drain electrode of the first LDMOS transistor is connected with the input end of the first voltage clamping circuit; the high-voltage bias port is connected with the output end of the first voltage clamping circuit; the second voltage clamping circuit comprises a second resistor and a plurality of second Zener diodes; all the second Zener diodes are connected in series in the same direction and are connected with the second resistor in parallel; the connection point of the second resistor and the anode of the second Zener diode forms the input end of the second voltage clamping circuit; the connection point of the second resistor and the cathode of the second Zener diode forms the output end of the second voltage clamping circuit; the drain electrode of the second LDMOS transistor is connected with the input end of the second voltage clamping circuit; the high voltage bias port is connected with the output end of the second voltage clamping circuit.

The invention provides a noise suppression high-voltage level shift circuit based on time delay self-locking, which preferably further comprises a high-voltage floating ground port; the delay self-locking circuit comprises a first tri-state gate, a second tri-state gate, a third resistor, a fourth resistor, a first inverter, a second inverter, an OR gate, a delay circuit and an AND gate; the connection input end of the OR gate is respectively connected with the drain electrode of the first LDMOS transistor and the drain electrode of the second LDMOS transistor; the output end of the OR gate is connected with the input end of the delay circuit; two input ends of the AND gate are respectively connected with the output end of the OR gate and the output end of the delay circuit; the output end of the AND gate is connected with the gating port of the first tri-state gate and the gating port of the second tri-state gate; the input end of the first tri-state gate is a first input end; the input end of the second tri-state gate is a second input end; the output end of the first tri-state gate is connected with the input end of the first inverter; the output end of the second tri-state gate is connected with the input end of the second inverter; the output end of the first phase inverter is a first output end; the output end of the second inverter is a second output end; the output end of the first tri-state gate is connected with the high-voltage floating ground port through a third resistor; and the output end of the second tri-state gate is connected with the high-voltage floating ground port through a fourth resistor.

According to the noise suppression high-voltage level shift circuit based on the time delay self-locking, preferably, the first tri-state gate and the second tri-state gate are both composed of the same type of tri-state gate; the tri-state gate comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a gating port, an input port and an output port; the source electrode of the first PMOS transistor is connected with the high-voltage bias port; the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor; the drain electrode of the second PMOS transistor is connected with the drain electrode of the first NMOS transistor; the source electrode of the first NMOS transistor is connected with the drain electrode of the second NMOS transistor; the source electrode of the second NMOS transistor is connected with the high-voltage floating ground port; the input port is connected with the grids of the first PMOS transistor and the second NMOS transistor; the gating port is connected with the grid electrode of the second PMOS transistor through an inverter; the gating port is connected with the source electrode of the first NMOS transistor; the output port is connected to a drain of the second PMOS transistor.

In the noise suppression high-voltage level shift circuit based on time delay self-locking provided by the invention, preferably, all power ends of the first filter circuit, the second filter circuit, the or gate, the and gate, the time delay circuit, the first inverter, the second inverter and the driving circuit are connected with the high-voltage bias port; all the bottom ends of the first filter circuit, the second filter circuit, the OR gate, the AND gate, the delay circuit, the first inverter, the second inverter and the drive circuit are connected with the high-voltage floating ground port.

The invention has the following advantages:

Drawings

The invention and its features, aspects and advantages will become more apparent from reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIG. 1 is a schematic diagram of a conventional high-side level shifting circuit;

FIG. 2 is a waveform diagram of noise signal propagation in a conventional high-side level-shifting circuit;

fig. 3 is a noise suppression high-side level shift circuit based on delay self-locking according to embodiment 1 of the present invention;

FIG. 4 shows a tri-state gate structure according to embodiment 1 of the present invention;

FIG. 5 is a waveform diagram illustrating a normal operating state of the high-side level shift circuit according to embodiment 1 of the present invention;

fig. 6 is a waveform diagram of a noise suppression state of the high voltage level shift circuit according to embodiment 1 of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application.

Example 1:

as shown in fig. 3, a noise suppression high-voltage level shift circuit based on delay self-locking is characterized by comprising an input port 1, a level shift circuit 2, a voltage clamp circuit 3, a filter circuit 4, a delay self-locking circuit 5, an RS flip-flop 6, a driving circuit 7, an output port 8, a high-voltage bias port 9 and a high-voltage floating ground port 0; the input port 1 includes a first input port 11 and a second input port 12; the level shift circuit 2 includes a first LDMOS transistor 21, a second LDMOS transistor 22; the voltage clamp circuit 3 includes a first clamp circuit 31 and a second clamp circuit 32; the first input port 11 is connected to the gate of the first LDMOS transistor 21; the source of the first LDMOS transistor 21 is grounded, and the drain of the first LDMOS transistor 21 is connected to the high voltage bias port 9 through the first clamp circuit 31; the second input port 12 is connected to the gate of the second LDMOS transistor 22; the source of the second LDMOS transistor 22 is grounded, and the drain of the second LDMOS transistor 22 is connected to the high voltage bias port 9 through a second clamp circuit 32; the filter circuit 4 includes a first filter circuit 41 and a second filter circuit 42; the drain of the first LDMOS transistor 21 is connected to the input terminal of the first filter circuit 41; the drain of the second LDMOS transistor 22 is connected to the input terminal of the second filter circuit 42; the delay self-locking circuit 5 comprises a first input end, a second input end, a first output end and a second output end; the output end of the first filter circuit 41 is connected to the first input end; the output terminal of the second filter circuit 42 is connected to the second input terminal; the first output end is connected with the position end of the RS trigger 6; the second output end is connected with the reset end of the RS trigger 6; the output end of the RS trigger 6 is connected with the input end of the drive circuit 7; the drive circuit 7 is connected to the output port 8.

The voltage clamp circuit 3 mainly provides proper levels for the output signals of the nodes a and B in fig. 3 so as to correctly turn on the subsequent high-side circuit, and the first voltage clamp circuit 31 includes a first resistor 311 and a plurality of first zener diodes 312; all the first zener diodes 321 are connected in series in the same direction and are connected in parallel with the first resistor 311; the junction of the first resistor 311 and the anode of the first zener diode 321 forms the input terminal of the first voltage clamp circuit 31; the junction of the first resistor 311 and the cathode of the first zener diode 312 forms the output terminal of the first voltage clamp circuit 31; the drain of the first LDMOS transistor 21 is connected to the input terminal of the first voltage clamp circuit 31; the high-voltage bias port 9 is connected with the output end of the first voltage clamping circuit 31; second voltage-clamping circuit 32 includes a second resistor 321 and a number of second zener diodes 322; all the second zener diodes 322 are connected in series in the same direction and are connected in parallel with the second resistor 321; the junction of the second resistor 321 and the anode of the second zener diode 322 forms the input of the second voltage clamp 32; the junction of the second resistor 321 and the cathode of the second zener diode 322 forms the output terminal of the second voltage clamping circuit 32; the drain of the second LDMOS transistor 21 is connected to the input terminal of the second voltage clamp circuit 32; the high voltage bias port 9 is connected to the output of the second voltage clamp 32.

The delay self-locking circuit is mainly used for performing shunt delay, superposition integration, logic locking and the like on noise signals generated by nodes a and B in fig. 3, as shown in fig. 4, the delay self-locking circuit 5 in this embodiment includes a first tri-state gate 501, a second tri-state gate 502, a third resistor 503, a fourth resistor 504, a first inverter 505, a second inverter 506, an or gate 507, a delay circuit 508 and an and gate 509; the connection input end of the or gate 507 is connected with the drain of the first LDMOS transistor 21 and the drain of the second LDMOS transistor 22, respectively; the output end of the or gate 507 is connected with the input end of the delay circuit 508; two input ends of the and gate 509 are respectively connected with an output end of the or gate 507 and an output end of the delay circuit 508; the output end of the AND gate 509 is connected with the gating port of the first tri-state gate 501 and the gating port of the second tri-state gate 502; the input end of the first tri-state gate 501 is a first input end; the input of the second tri-state gate 502 is a second input; the output of the first tri-state gate 501 is connected to the input of the first inverter 505; the output of the second tri-state gate 502 is connected to the input of the second inverter 506; the output terminal of the first inverter 505 is a first output terminal; the output of the second inverter 506 is a second output; the output end of the first tri-state gate 501 is connected to the high-voltage floating ground port 0 through a third resistor 503; the output of the second tri-state gate 502 is connected to the high voltage floating ground port 0 through a fourth resistor 504.

The first tri-state gate 501 and the second tri-state gate 502 in this embodiment are both composed of the same type of tri-state gate; the tri-state gate comprises a first PMOS transistor 01, a second PMOS transistor 02, a first NMOS transistor 03, a second NMOS transistor 04, a gating port 05, an input port 06 and an output port 07; the source of the first PMOS transistor 01 is connected to the high voltage bias port 9; the drain electrode of the first PMOS transistor 01 is connected with the source electrode of the second PMOS transistor 02; the drain of the second PMOS transistor 02 is connected to the drain of the first NMOS transistor 03; the source of the first NMOS transistor 03 is connected to the drain of the second NMOS transistor 04; the source electrode of the second NMOS transistor 04 is connected with a high-voltage floating ground port 0; the input port 06 is connected with the gates of the first PMOS transistor 01 and the second NMOS transistor 02; the gate port 05 is connected to the gate of the second PMOS transistor 02 through an inverter 08; the gating port 05 is connected with the source electrode of the first NMOS transistor 03; the output port 07 is connected to the drain of the second PMOS transistor 02.

In addition, in the present embodiment, all power supply terminals of the first filter circuit 41, the second filter circuit 42, the or gate 507, the delay circuit 508, the and gate 509, the first inverter 505, the second inverter 506, and the driving circuit 7 are connected to the high voltage bias port 9; all the bottom ends of the first filter circuit 41, the second filter circuit 42, the or gate 507, the delay circuit 508, the and gate 509, the first inverter 505, the second inverter 506 and the drive circuit 7 are connected to the high-voltage floating ground port 0.

As shown in fig. 5 and 6, when the delay self-locking based noise suppression high-voltage level shift circuit provided in the embodiment of the invention operates, in a power driving process, the controller first generates a PWM periodic square wave signal according to a control logic, converts the PWM periodic square wave signal into two paths of narrow pulse signals (generally, middle and low voltage signals, such as VSS-VDD in fig. 5) through the narrow pulse generating circuit, respectively inputs the two paths of narrow pulse signals through the first input port 11 and the second input port 12, and is used for periodically turning on the first LDMOS transistor 21 and the second LDMOS transistor 22, the two paths of middle and low voltage narrow pulse signals input through the first input port 11 and the second input port 12 are respectively converted into two paths of high-voltage negative pulse signals at the nodes a and B, and the converted level range is VS-VB.

Normally, as shown in fig. 5, the negative pulse signals of the nodes a and B are not in phase, but are separated by a certain period, the distance is the width of the PWM square wave, so that the nodes a and B are only in one of three combination states of low level/high level, high level/high level, and high level/low level; at this time, the signals of the nodes a and B are input through the or gate 507, the output of the or gate 507 is always high, and therefore the nodes C, D and E are always high; the first tri-state gate 501 and the second tri-state gate 502 are active high, so both tri-state gates are always on. The time delay self-locking circuit 5 is in a complete open circuit state, the negative pulse signals of the nodes A and B sequentially pass through the filter circuit 4, the two three-state gates and the two inverters, finally waveform reconstruction is carried out through the RS trigger 6, and finally the negative pulse signals are amplified through the driving circuit 7 and then output through the output port 8.

When the COM ground in fig. 3 is floating under the high voltage VS ground, a shift current is generated at the drains of the first LDMOS transistor 21 and the second LDMOS transistor 22, and a voltage drop is generated at the first resistor 311 and the second resistor 312, and noise signals are generated at the nodes a and B, as shown in fig. 6. When nodes a and B generate ideal common mode signals simultaneously, the or gate 597 in the self-latching delay circuit 5 will output a low level signal at node C, assuming that the output signal width is W1; w1 is phase-shifted by Δ T (Δ T < W1) by the delay circuit 508, a negative pulse of W2 is generated at node D, and W2 is slightly different from W1 under the influence of the delay circuit 508; w1 and W2 enter an AND gate 509 to be integrated and superposed, and finally a larger negative pulse width W3 is obtained, wherein W3 is equal to the sum of delta T and W2; in the negative pulse width of W3, the low level of node E locks the first tri-state gate 501 and the second tri-state gate 502, the outputs of the first tri-state gate 501 and the second tri-state gate 502 are in the high impedance state, the third resistor 503 and the fourth resistor 504 respectively pull down the inputs of the first inverter 505 and the second inverter 506 to the low level, and finally the output state of the output port 8 is maintained.

By properly setting the filtering capabilities of the first and

second filtering circuits

41 and 42, the filtered noise signal can be within the pulse width W3 of the node E. As shown in fig. 6, the pulse width of the common mode noise signal of the filtered nodes F and G is S1, S1 is smaller than W3, and is completely contained in phase by W3; since the first tri-state gate 501 and the second tri-state gate 502 are already locked, the common mode noise signals of the nodes F and G cannot be transmitted to the subsequent circuit, i.e. the noise suppression is realized.

For noise signals containing significant differential mode components, as shown in fig. 6, the noise signals at nodes a and B may have significant differences in width and amplitude, so that only their common mode portions may trigger the delay self-locking circuit 5 through the or gate 507. In a real circuit, the noise differential mode components of the nodes a and B are generally small, and the common mode part of the noise differential mode components can still generate a wide enough locking signal after passing through a delay self-locking circuit, as shown in L3 in fig. 6; as long as the value of the time delay circuit delta T is reasonably set, the noises N1 and N2 with different pulse widths can still be successfully filtered.

In conclusion, the noise suppression high-voltage level shift circuit based on the time delay self-locking has extremely strong anti-noise interference capability, can effectively filter most noise signals before the RS trigger, and improves the reliability of the circuit.

The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or any other related technical fields, are included in the scope of the present invention.

Claims

1. A noise suppression high-voltage level shift circuit based on time delay self-locking is characterized by comprising an input port, a level shift circuit, a voltage clamping circuit, a filter circuit, a time delay self-locking circuit, an RS trigger, a drive circuit, an output port and a high-voltage bias port; the input ports include a first input port and a second input port; the level shift circuit comprises a first LDMOS transistor and a second LDMOS transistor; the voltage clamping circuit comprises a first clamping circuit and a second clamping circuit; the first input port is connected with the grid electrode of the first LDMOS transistor; the source electrode of the first LDMOS transistor is grounded, and the drain electrode of the first LDMOS transistor is connected with the high-voltage bias port through the first clamping circuit; the second input port is connected with the grid electrode of the second LDMOS transistor; the source electrode of the second LDMOS transistor is grounded, and the drain electrode of the second LDMOS transistor is connected with the high-voltage bias port through the second clamping circuit; the filter circuit comprises a first filter circuit and a second filter circuit; the drain electrode of the first LDMOS transistor is connected with the input end of the first filter circuit; the drain electrode of the second LDMOS transistor is connected with the input end of the second filter circuit; the delay self-locking circuit comprises a first input end, a second input end, a first output end and a second output end; the output end of the first filter circuit is connected with the first input end; the output end of the second filter circuit is connected with the second input end; the first output end is connected with the position end of the RS trigger; the second output end is connected with the reset end of the RS trigger; the output end of the RS trigger is connected with the input end of the driving circuit; the driving circuit is connected with the output port.

2. The delay self-locking based noise-suppressing high voltage level shifting circuit of claim 1, wherein the first voltage clamp circuit comprises a first resistor and a number of first zener diodes; all the first Zener diodes are connected in series in the same direction and are connected with the first resistor in parallel; the connection point of the first resistor and the anode of the first Zener diode forms the input end of the first voltage clamping circuit; the connection point of the first resistor and the cathode of the first Zener diode forms the output end of the first voltage clamping circuit; the drain electrode of the first LDMOS transistor is connected with the input end of the first voltage clamping circuit; the high-voltage bias port is connected with the output end of the first voltage clamping circuit; the second voltage clamping circuit comprises a second resistor and a plurality of second Zener diodes; all the second Zener diodes are connected in series in the same direction and are connected with the second resistor in parallel; the connection point of the second resistor and the anode of the second Zener diode forms the input end of the second voltage clamping circuit; the connection point of the second resistor and the cathode of the second Zener diode forms the output end of the second voltage clamping circuit; the drain electrode of the second LDMOS transistor is connected with the input end of the second voltage clamping circuit; the high voltage bias port is connected with the output end of the second voltage clamping circuit.

3. The delay self-locking based noise-suppressing high voltage level shifting circuit of claim 1, further comprising a high voltage floating ground port; the delay self-locking circuit comprises a first tri-state gate, a second tri-state gate, a third resistor, a fourth resistor, a first inverter, a second inverter, an OR gate, a delay circuit and an AND gate; the connection input end of the OR gate is respectively connected with the drain electrode of the first LDMOS transistor and the drain electrode of the second LDMOS transistor; the output end of the OR gate is connected with the input end of the delay circuit; two input ends of the AND gate are respectively connected with the output end of the OR gate and the output end of the delay circuit; the output end of the AND gate is connected with the gating port of the first tri-state gate and the gating port of the second tri-state gate; the input end of the first tri-state gate is a first input end; the input end of the second tri-state gate is a second input end; the output end of the first tri-state gate is connected with the input end of the first inverter; the output end of the second tri-state gate is connected with the input end of the second inverter; the output end of the first phase inverter is a first output end; the output end of the second inverter is a second output end; the output end of the first tri-state gate is connected with the high-voltage floating ground port through a third resistor; and the output end of the second tri-state gate is connected with the high-voltage floating ground port through a fourth resistor.

4. The delay self-locking based noise-rejection high voltage level shifting circuit of claim 3, wherein said first tri-state gate and said second tri-state gate are each comprised of the same type of tri-state gate; the tri-state gate comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a gating port, an input port and an output port; the source electrode of the first PMOS transistor is connected with the high-voltage bias port; the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor; the drain electrode of the second PMOS transistor is connected with the drain electrode of the first NMOS transistor; the source electrode of the first NMOS transistor is connected with the drain electrode of the second NMOS transistor; the source electrode of the second NMOS transistor is connected with the high-voltage floating ground port; the input port is connected with the grids of the first PMOS transistor and the second NMOS transistor; the gating port is connected with the grid electrode of the second PMOS transistor through an inverter; the gating port is connected with the source electrode of the first NMOS transistor; the output port is connected to a drain of the second PMOS transistor.

5. The delay self-locking based noise suppression high voltage level shifting circuit according to claim 3, wherein all power terminals of the first filter circuit, the second filter circuit, the OR gate, the AND gate, the delay circuit, the first inverter, the second inverter and the driving circuit are connected to the high voltage bias port; all the bottom ends of the first filter circuit, the second filter circuit, the OR gate, the AND gate, the delay circuit, the first inverter, the second inverter and the drive circuit are connected with the high-voltage floating ground port.