CN111049515A

CN111049515A - High voltage level shifting circuit and method for enhanced reliability

Info

Publication number: CN111049515A
Application number: CN201911365107.5A
Authority: CN
Inventors: 冯翰雪; 李冬超
Original assignee: 3Peak Inc
Current assignee: 3Peak Inc
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2020-04-21
Anticipated expiration: 2039-12-26
Also published as: CN111049515B

Abstract

A high voltage level shifting circuit and method of enhanced reliability that level shifts a low voltage domain input signal to a high voltage domain output signal includes a coupling circuit configured to respond to rising and/or falling edges of the high voltage domain signal and to maintain a high voltage domain output signal state. The invention utilizes the RC coupling circuit to generate pulse signals at the rising edge and the falling edge of HV _ VSS/HV _ VDD, keeps the state of a latch at a high-voltage end, avoids the latch from false overturning and solves the problem of false overturning caused by very large change slope of HV _ VSS/HV _ VDD in the high-voltage circuit.

Description

High voltage level shifting circuit and method for enhanced reliability

Technical Field

The invention relates to a level shift circuit, in particular to a high-voltage level shift circuit and a method for enhancing reliability.

Background

Level shift circuits are widely used, for example, in DC/DC, motor drivers, load switches, etc., the level shift circuits can control the turn-on and turn-off of high-side power transistors.

Referring to fig. 1 and 2, when the conventional level shift circuit is applied to a DC/DC motor driving circuit, especially under high voltage condition, there is a reliability problem, that is, the latch state will be flipped by mistake, and the high-low logic state of the output signal OUT is inconsistent with the input signal ON. The sources of this problem are:

1. in the DC/DC motor driving circuit, the voltage difference between HV _ VDD and HV _ VSS is fixed, but HV _ VSS can be switched rapidly between around 0V and a high voltage, and the slope during switching can be as high as 5V/ns.

2. In the high-voltage circuit, the PM3/PM4/NM 3-NM 6 must use high-voltage MOS, and the parasitic capacitance of the drain and the source is obvious, that is, the ON _ HV/OFF _ HV node has larger parasitic capacitance, such as Cpar1/Cpar2 shown in FIG. 1.

3. During the high-low transition of the input signal, Cpar1/Cpar2 needs to be charged quickly to ensure the output logic is correct, and the following is exemplified by the rising edge of input ON, as shown in fig. 3 (a):

the input signal ON goes high, ON _ HV goes low equal to HV _ VSS voltage, OFF _ HV goes high equal to HV _ VDD; NM1/PM2 is on, NM2/PM1 is off.

HV _ VSS/HV _ VDD then appears as a fast rising edge. During the rising edge, ON _ HV/OFF _ HV also needs to follow the fast rise of HV _ VSS/HV _ VDD. For the ON-HV and OFF-HV nodes, Cpar1 and Cpar2 can be charged quickly and the ON-HV and OFF-HV nodes are pushed up to the same potential, since the parasitic diodes of NM1 and NM2 have stronger current capability.

Just after HV _ VSS/HV _ VDD stops rising, neither PM3 nor PM4 can conduct. The four devices of the latch are in the same operating state and are in an "out-of-lock" state, and the latch may be locked again when any one of the nodes ON _ HV and OFF _ HV is disturbed. And whether the output result is correct or not depends on which node is disturbed.

4. Similarly, as shown in FIG. 3 (b), the input ON signal goes low, OUT will appear in the opposite state, and then HV _ VSS/HV _ VDD will appear as a fast falling edge, requiring fast discharge of Cpar1 and Cpar 2. Since the parasitic diodes of PM2 have a stronger current capability due to PM1, it is possible to quickly discharge Cpar1 and Cpar2 and pull down the ON _ HV and OFF _ HV nodes to the same potential. The subsequent occurrence of "out-of-lock" and a disturbance causing latch lock in the wrong state is the same principle as the ON signal going high.

5. Similarly, if the parasitic inductance of the PCB, bonding wire, etc. is too large, HV _ VSS/HV _ VDD generates high frequency oscillations in which high speed rising/falling edges can also cause the level shifting circuit to generate erroneous outputs.

How to provide a reliable high-voltage level shift circuit is a problem which needs to be solved urgently.

Disclosure of Invention

An embodiment of the present invention provides a high voltage level shift circuit and method for enhancing reliability, which can avoid error in output signal state especially under high voltage and high slew rate. The method comprises the following steps:

there is provided a high voltage level shifting circuit of enhanced reliability level shifting a low voltage domain input signal to a high voltage domain output signal, the high voltage level shifting circuit comprising a coupling circuit configured to respond to rising and/or falling edges of the high voltage domain signal and to maintain a high voltage domain output signal state.

In one embodiment, the coupling circuit is an RC coupling circuit.

In one embodiment, the coupling circuit drives and pulls up the high-voltage domain output signal in response to a rising edge of the high-voltage domain power supply terminal from a negative pulse of the coupled-out signal.

In one embodiment, the coupling circuit drives and pulls down the high-voltage domain output signal in response to a falling edge of the high-voltage domain power supply terminal from a positive pulse of the coupled-out signal.

In one embodiment, the coupling circuit is configured to respond to a rising edge and/or a falling edge of the ground of the high voltage domain and pull down a voltage at the high voltage domain output signal terminal.

In one embodiment, the high voltage level shifting circuit further comprises a latch comprising a pair of cross-coupled inverters.

In one embodiment, the high voltage level shifting circuit further comprises an output inverter having an input associated with the output of the latch,

the coupling circuit is configured to respond to a rising edge and/or a falling edge of a ground of the high voltage domain and pull down an input terminal node voltage of the output inverter.

In one embodiment, the high voltage level shift circuit further includes a first MOS transistor, a source of the first MOS transistor is grounded, and a drain of the first MOS transistor is associated with the high voltage domain output signal terminal;

the coupling circuit responds to the rising edge of the high-voltage domain ground and couples out RISE signal pulse, and the RISE signal pulse drives the grid electrode of the first MOS tube through a logic OR gate.

In one embodiment, the level shift circuit further includes a second MOS transistor, a source of the second MOS transistor is grounded, and a drain of the second MOS transistor is associated with the high-voltage domain output signal terminal;

the coupling circuit comprises a second capacitor and a second resistor;

the level shift circuit further comprises a third resistor and a second MOS tube, wherein the source electrode of the second MOS tube is associated with a power supply voltage VDD, the drain electrode of the second MOS tube is grounded through the third resistor, the second resistor is connected between the source electrode and the grid electrode of the second MOS tube, a second capacitor is connected between the grid electrode of the second MOS tube and the ground of a high-voltage domain, the coupling circuit responds to the falling edge of the ground of the high-voltage domain and couples out a FALL signal pulse, and the FALL signal pulse drives the grid electrode of the second MOS tube through a logic OR gate.

Also provided is a method of preventing a high voltage level shifting circuit from outputting an erroneous signal, the high voltage level shifting circuit level-shifting a low voltage domain input signal into a high voltage domain output signal, the high voltage level shifting circuit comprising a coupling circuit configured to respond to a rising edge and/or a falling edge of the high voltage domain signal and to maintain a high voltage domain output signal state.

Compared with the prior art, the invention utilizes the RC coupling circuit to generate pulse signals at the rising edge and the falling edge of HV _ VSS/HV _ VDD, keeps the state of a high-voltage end latch, avoids the latch from mistakenly turning over, and solves the problem of mistakenly turning over caused by very large change slope of HV _ VSS/HV _ VDD in the high-voltage circuit.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a conventional level shifting circuit topology;

FIG. 2 is a timing diagram of a conventional level shift circuit in normal operation;

fig. 3 is a timing chart of the conventional level shift circuit at the time of high-low transition of an input signal (in which (a) an input ON signal rises and (b) an input ON signal falls);

FIG. 4 is a topology diagram of a level shifting circuit according to a first embodiment of the present application;

FIG. 5 is a timing diagram illustrating the normal operation of the level shift circuit according to the first embodiment of the present application;

FIG. 6 is a topology diagram of a level shifting circuit according to a second embodiment of the present application;

fig. 7 is a timing chart of the level shift circuit in the second embodiment of the present application in a normal operation.

Detailed Description

The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.

Also, it should be understood that, although the terms first, second, etc. may be used herein to describe various elements or structures, these described elements should not be limited by these terms. These terms are only used to distinguish these descriptive objects from one another. For example, the first NMOS transistor may be referred to as a second NMOS transistor, and similarly, the second NMOS transistor may also be referred to as a first NMOS transistor, without departing from the scope of the present application.

Also, the same reference numbers or symbols may be used in different embodiments, but this does not represent a structural or functional relationship, but merely for convenience of description.

According to the embodiment of the invention, two coupling circuits for respectively detecting the rising edge and the falling edge of the HV _ VSS are added on the traditional level shift circuit, and the logic signal generated by the coupling circuit can force the latch of the high-voltage end to be in a correct state, so that the interference on the rising edge and the falling edge of the HV _ VSS is avoided.

Example 1

The topology and timing diagram of the level shifting circuit 100 are shown in fig. 4 and 5. The level shifting circuit 100 comprises a latch 110, the latch 110 comprising a second inverter 112 cross-coupled with a first inverter 111. The first inverter 111 includes a PMOS transistor PM1 with its source associated to a high power domain power supply node providing a high supply voltage HV _ VDD. The first inverter 111 also includes an NMOS transistor NM1, whose source is associated to the ground node HV _ VSS of the latch 110, and whose drain is coupled to the drain of the PMOS transistor PM 1.

Similarly, the second inverter 112 includes a PMOS transistor PM2 having its source associated with a high-power-domain power supply node that provides a high supply voltage HV _ VDD. The second inverter 112 also includes an NMOS transistor NM2, whose source is associated to the ground node HV _ VSS of the latch 110, and whose drain is coupled to the drain of the PMOS transistor PM 2.

The gates of the transistors PM1 and NM1 are coupled to the drains of the transistors PM2 and NM 2. Similarly, the gates of transistors PM2 and NM2 are coupled to the drains of transistors PM1 and NM 1.

The level shift circuit 100 further includes a high voltage PMOS transistor PM3, a PMOS transistor PM4, an NMOS transistor NM4, and an NMOS transistor NM 5.

The low voltage input signal ON drives the gate of the NMOS transistor NM4, the drain of the NMOS transistor NM4 is tied to the drain of the PMOS transistor PM3, and the source thereof is tied to ground.

The low voltage input signal ON is inverted by the third inverter 113 powered by the low voltage domain power supply voltage VDD to form a third inverter output signal OFF driving the gate of the NMOS transistor NM5, the drain of which NMOS transistor NM5 is associated to the drain of the PMOS transistor PM4 and the source thereof is associated to ground.

The source of the high voltage PMOS transistor PM3 is associated to the drains of the transistors PM1 and NM1 in the cross-coupled first inverter 111. The gate of high voltage PMOS transistor PM3 is associated with ground node HV _ VSS of latch 110.

The source of the high voltage PMOS transistor PM4 is associated to the drains of transistors PM2 and NM2 in the cross-coupled second inverter 112. The gate of high voltage PMOS transistor PM4 is associated with ground node HV _ VSS of latch 110.

The drains of the transistors PM1 and NM1 are also coupled to an input of a fourth inverter 114, the fourth inverter 114 outputting a level shifted output signal OUT for the level shifting circuit 100. The fourth inverter 114 is powered by the high-voltage domain supply voltage HV _ VDD.

The drains of the transistors PM2 and NM2 are also coupled to the input of a fifth inverter 115, the fifth inverter 115 outputting a level shifted output signal OUTB for the level shifting circuit 100. The fifth inverter 115 is powered by the high-voltage domain supply voltage HV _ VDD.

In order to shorten the delay time of inputting the ON signal to outputting the OUT signal, the level shift circuit 100 is further provided with a high voltage NMOS transistor NM3 and a high voltage NMOS transistor NM 6. The source of the NMOS transistor NM3 is tied to ground, and the drain of the NMOS transistor NM3 is coupled to the input terminal of the fourth inverter 114. The source of the NMOS transistor NM6 is tied to ground, and the drain of the NMOS transistor NM6 is coupled to the input terminal of the fifth inverter 115. Narrow PULSE low-voltage input signals ON _ PULSE and OFF _ PULSE are generated at the rising edge and the falling edge of the ON signal respectively, NM3 and NM6 are driven respectively, ON _ HV (the signal at the input end of the fourth inverter 114) and OFF _ HV (the signal at the input end of the fifth inverter 115) are directly pulled down, and the output signal OUT is accelerated to be inverted.

In other embodiments,

inverters

114 and 115 may also be replaced with buffers or other logic gates.

In this embodiment, the level shift circuit 100 functions to convert the logic signal ON between 0V/VDD voltages to the logic signal OUT between HV _ VSS/HV _ VDD voltages.

In order to keep the latch of the high voltage terminal in a correct state and avoid interference at the rising edge and the falling edge of HV _ VSS, in the present embodiment, the level shift circuit 100 further includes

coupling circuits

116 and 117 configured to respond to the rising edge and/or the falling edge of the high voltage domain signal and keep the high voltage domain output signal state.

In this embodiment, the coupling circuit may be configured to respond to a rising edge and/or a falling edge of the high-voltage domain signal power terminal HV _ VDD, and may also be configured to respond to a rising edge and/or a falling edge of the high-voltage domain signal ground terminal HV _ VSS.

In this embodiment, the ground HV _ VSS of the high voltage domain is the ground of the high voltage domain circuit, but it may be floating, for example, the voltage value may be 0V or may be raised to 40V. Then, the power source HV _ VDD of the high voltage domain is always higher than HV _ VSS by 5V, so the voltage value of HV _ VDD also changes along with HV _ VSS.

In one embodiment, the coupling circuit 116 is an RC coupling circuit, and includes a first resistor R1 and a first capacitor C1 connected in series between the ground HV _ VSS of the high voltage domain and the ground terminal. The C1/R1 detects the HV _ VSS rising edge, which is coupled out of the RISE signal pulse, which drives NM3 through a logic OR gate, pulling down the ON _ HV node, ensuring that ON _ HV is close to HV _ VSS voltage, and that latch also remains in this state after the HV _ VSS rising edge is over.

In one embodiment, the coupling circuit 117 includes a second capacitor C2 and a second resistor R2, the level shift circuit further includes a third resistor R3 and a second MOS transistor PM5, a source of the second MOS transistor PM5 is coupled to the power voltage VDD, a drain of the second MOS transistor PM5 is grounded through the third resistor R3, the second resistor R2 is connected between the source and the gate of the second MOS transistor PM5, and the second capacitor C2 is connected between the gate of the second MOS transistor PM5 and the ground HV _ VSS in the high voltage domain. C2/R2 detects the HV _ VSS falling edge. The falling edge of HV _ VSS couples out a pulse of the FALL signal, which drives NM6 through a logic OR gate, pulling down the OFF _ HV node, ensuring that OFF _ HV is close to the HV _ VSS voltage and that latch remains in this state after the falling edge of HV _ VSS is complete.

In this embodiment, the time constants of C1/R1 and C2/R2 are designed to match the slope of the rising/falling edge of HV _ VSS, and the RISE/FALL node needs voltage clamping to prevent over-voltage damage. This is not described in detail.

The coupling of example 1 is particularly applicable to: the ON high level corresponds to HV _ VSS rising to a high voltage, and the ON low level corresponds to HV _ VSS falling to a low voltage. Such as DC/DC, top tube control in motor drive circuits.

Example 2

The latch core in this embodiment is the same as that in embodiment 1, and is not described again. In order to force the latch at the high-voltage side to be in the correct state and avoid the interference at the rising edge and the falling edge of HV _ VSS, embodiment 2 provides another implementation manner, that is, the latch can be kept in the original state at the rising edge and the falling edge of HV _ VSS regardless of the ON high-low level.

As shown in connection with fig. 6, the level shift circuit 200 includes

coupling circuits

211 and 212.

The coupling circuit 211 includes a capacitor C1 and a resistor R1, and the capacitor C1 and the resistor R1 are connected in series between HV _ VDD and ground. There are 4 MOS transistors between HV _ VDD and HV _ VSS, including PM5, PM7, NM7 and NM10, where the source of PM5 is connected to HV _ VDD, the drain of PM5 is connected to the source of PM7, the drain of PM7 is connected to the drain of NM7, the source of NM7 is connected to the drain of NM10, the source of NM10 is connected to HV _ VSS, and the gates of PM5 and NM10 are connected to the gates of PM1 and PM 2.

Similarly, the coupling circuit 212 includes a capacitor C2 and a resistor R2, the capacitor C2 and the resistor R2 being connected in series between VIN and HV _ VSS. There are 4 MOS transistors between HV _ VDD and HV _ VSS, including PM6, PM8, NM8 and NM9, where the source of PM6 is connected to HV _ VDD, the drain of PM6 is connected to the source of PM8, the drain of PM8 is connected to the drain of NM8, the source of NM8 is connected to the drain of NM9, the source of NM9 is connected to HV _ VSS, and the gates of PM6 and NM9 are connected to the gates of PM1 and PM 2.

Taking the working condition of HV _ VSS rising and falling edges corresponding to ON high and low levels as an example, the working principle is as shown in fig. 7:

the ON rising edge generates a HV _ VDD rising edge, ON _ HV low, OFF _ HV high. The C1/R1 detects the HV _ VDD rising edge, which couples out the negative pulse of the FALL signal, turning PM7 on. At this time, ON _ HV is low, and PM5 is turned ON. This produces a current of I _ UP2, further pulling UP the OFF _ HV node, ensuring that OFF _ HV is close to the HV _ VDD voltage and that latch also maintains this state after the HV _ VDD rising edge ends.

The ON falling edge generates HV _ VSS falling edge, OFF _ HV low level, ON _ HV high level. The C2/R2 detects the HV _ VSS falling edge and couples out the positive pulse of the RISE signal, turning NM7 on. At this time, ON _ HV is high to turn ON NM10, thereby generating I _ DN2 current, further pulling down the OFF _ HV node, ensuring that OFF _ HV is close to HV _ VSS voltage and latch is maintained after the HV _ VSS falling edge is over.

For the working condition that the ON high level and the ON low level correspond to the descending and ascending edges of HV _ VSS, when the HV _ VSS ascends, the PM6/PM8 generates the pull-up of the ON _ HV node; ON the falling edge of HV _ VSS, the pull-down ON the ON _ HV node is generated by NM8/NM 9; the latch state can be kept free from the interference of the rising edge and the falling edge of HV _ VSS. This is not described in detail.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. An enhanced reliability high voltage level shifting circuit level shifts a low voltage domain input signal to a high voltage domain output signal, the high voltage level shifting circuit comprising a coupling circuit configured to respond to a rising edge and/or a falling edge of the high voltage domain signal and to maintain a high voltage domain output signal state.

2. The enhanced reliability high voltage level shifting circuit of claim 1, wherein the coupling circuit is an RC coupling circuit.

3. The enhanced reliability high voltage level shifting circuit of claim 1 or 2, wherein the coupling circuit drives and pulls up the high voltage domain output signal in response to a rising edge of the high voltage domain power supply terminal, a negative pulse of the coupled-out signal.

4. The enhanced reliability high voltage level shifting circuit of claim 1 or 2, wherein the coupling circuit drives and pulls down the high voltage domain output signal in response to a falling edge of the high voltage domain power supply terminal from a positive pulse of the coupled out signal.

5. The enhanced reliability high voltage level shifting circuit of claim 1 or 2, wherein the coupling circuit is configured to respond to a rising and/or falling edge of ground of the high voltage domain and pull down a high voltage domain output signal terminal voltage.

6. The enhanced reliability high voltage level shifting circuit of claim 1 or 2, further comprising a latch comprising a pair of cross-coupled inverters.

7. The enhanced reliability high voltage level shifting circuit of claim 6, further comprising an output inverter having an input associated with an output of said latch,

8. The enhanced reliability high voltage level shift circuit according to claim 1 or 2, further comprising a first MOS transistor having a source connected to ground and a drain connected to said high voltage domain output signal terminal;

9. The enhanced reliability high voltage level shift circuit according to claim 1 or 2, wherein the level shift circuit further comprises a second MOS transistor, the source of the second MOS transistor is grounded, and the drain of the second MOS transistor is associated with the high voltage domain output signal terminal;

the coupling circuit comprises a second capacitor and a second resistor;

10. A method of preventing a high voltage level shifting circuit from outputting an erroneous signal, wherein the high voltage level shifting circuit level shifts a low voltage domain input signal into a high voltage domain output signal, the high voltage level shifting circuit comprising a coupling circuit configured to respond to a rising edge and/or a falling edge of the high voltage domain signal and to maintain a high voltage domain output signal state.