CN112765080B - Information processing method and equipment - Google Patents
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- CN112765080B CN112765080B CN202110086865.4A CN202110086865A CN112765080B CN 112765080 B CN112765080 B CN 112765080B CN 202110086865 A CN202110086865 A CN 202110086865A CN 112765080 B CN112765080 B CN 112765080B
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- 230000010365 information processing Effects 0.000 title claims abstract description 16
- 238000003672 processing method Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims description 11
- 238000012544 monitoring process Methods 0.000 claims description 8
- 238000012360 testing method Methods 0.000 claims description 6
- 238000004891 communication Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The invention discloses an information processing method and equipment, which are applied to a device to be tested configured with a functional module, and comprise the following steps: based on a first instruction, periodically switching an operation mode of an IP core in the functional module; if the IP core is in a first operation mode, feeding back first parameter information representing the state of the functional module; and if the IP core is in the second operation mode, feeding back second parameter information representing the state of the device to be tested. Therefore, by setting the first operation mode and the second operation mode for the IP cores of the functional module and periodically switching according to the first instruction, the detected state is fed back in different operation modes.
Description
Technical Field
The present invention relates to the field of server technologies, and in particular, to an information processing method and apparatus.
Background
The current mode of acquiring the state information of the peripheral devices of the accelerator card by the power management module at the server side is to add an IIC IP core resource to each peripheral device to access the peripheral devices by the FPGA chip, and the mode has the defect of increasing operation resources.
Disclosure of Invention
The embodiment of the invention provides an information processing method and information processing equipment, which have the technical effect that the peripheral state of an FPGA chip can still be obtained under the condition that IP core resources are not increased.
In one aspect, the present invention provides an information processing method applied to a device to be tested configured with a functional module, the method including: based on a first instruction, periodically switching an operation mode of an IP core in the functional module; if the IP core is in a first operation mode, feeding back first parameter information representing the state of the functional module; and if the IP core is in the second operation mode, feeding back second parameter information representing the state of the device to be tested.
In an embodiment, the periodically switching the operation mode of the IP core in the functional module includes: the operation mode is initially the first operation mode; and switching the operation mode into the second operation mode every preset time period, and after feeding back the second parameter information, switching the operation mode into the first operation mode again.
In an embodiment, if the IP core is in the first operation mode, the method further includes: monitoring the first parameter information in real time, and storing the first parameter information into an information base; correspondingly, the feeding back the first parameter information includes: extracting first parameter information in the information base, and feeding back the first parameter information.
In an embodiment, the feeding back the first parameter information includes: and receiving and responding to a second instruction to feed back the first parameter information.
In an embodiment, the second parameter information includes a temperature parameter and a voltage parameter.
Another aspect of the present invention provides an information processing apparatus including a device under test configured with a functional module, a first device, and a second device; the first device is in communication connection with the functional module and is used for sending a first instruction to the functional module so as to periodically switch the operation mode of the IP core in the functional module; the first device is further configured to feed back first parameter information that characterizes a state of the functional module when the IP core is in a first operation mode; and the second device is used for feeding back second parameter information representing the state of the device to be tested when the IP core is in a second operation mode.
In an embodiment, the first device is specifically configured to: and sending a first instruction to the functional module at intervals of a preset time length to instruct the IP core to switch the operation mode to the second operation mode, and after the first device feeds back the second parameter information, switching the operation mode to the first operation mode.
In an embodiment, the first device is specifically configured to: monitoring the first parameter information in real time, and storing the first parameter information into a register; correspondingly, when the first device feeds back the first parameter information, the first device is specifically configured to: extracting first parameter information in the register and feeding back the first parameter information.
In an embodiment, the first device is specifically configured to, when feeding back the first parameter information: and receiving and responding to a second instruction sent by the third device to acquire the first parameter information and feeding back the first parameter information to the third device.
In an embodiment, the first device is a micro control unit MCU, the second device includes a temperature sensor and a current sensor, the third device is a power management device BMC, and the functional module is an FPGA chip.
In the embodiment of the invention, the first operation mode and the second operation mode are set for the IP core of the functional module, and the operation mode feedback is switched periodically.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 is a schematic diagram of an implementation flow of an information processing method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a flow chart for implementing each operation mode in an information processing method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an information processing apparatus according to an embodiment of the present invention;
Fig. 4 is a specific feedback flowchart of an information processing method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions according to the embodiments of the present invention will be clearly described in the following with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, an aspect of the present invention provides an information processing method applied to a device under test configured with a functional module, the method including:
Step 101, based on a first instruction, periodically switching the operation mode of the IP core in the functional module;
Step 102, if the IP core is in a first operation mode, feeding back first parameter information representing the state of the functional module;
and step 103, if the IP core is in the second operation mode, feeding back second parameter information representing the state of the device to be tested.
In this embodiment, the functional module is hardware of a configurable IP core, such as an FPGA chip (Field Programmable GATE ARRAY ), a CPLD chip (Complex Programmable Logic Device, complex programmable logic device), and the like, and in this embodiment, the FPGA chip is preferred. The device to be tested comprises an accelerator card, a display card, a sound card and the like, and the accelerator card is preferred to be the device to be tested in the embodiment.
As shown in fig. 2 and 3, in step 101, the first instruction may be a periodic clock signal or a pulse signal, and may be sent by internal hardware (such as a MCU) mounted on the device under test, or may be sent by an external device (such as a CPU) connected to the device under test, where in this embodiment, the first instruction is preferably sent by the MCU. The triggering mode of the first instruction is mainly triggered according to a local clock or an external clock, and comprises a high-level signal and a low-level signal. The functional module can configure the first operation mode and the second operation mode through a software program in advance, and after the functional module acquires the first instruction, the operation mode of the IP core is switched through the preset software program according to the clock high-low level signal.
In step 102 and step 103, the operation modes include a first operation mode and a second operation mode, where the first operation mode corresponds to a high level of the clock signal and the second operation mode corresponds to a low level of the clock signal, and when the clock signal is at the high level, the operation mode of the IP core is switched to the first operation mode, and when the clock signal is at the low level, the operation mode of the IP core is switched to the second operation mode. Of course, the reverse is also possible, i.e. the first operation mode corresponds to a low level of the clock signal and the second operation mode corresponds to a high level of the clock signal.
And when the operation mode of the IP core is in the first operation mode, acquiring first parameter information representing the state of the functional module and feeding back the first parameter information. Specifically, the first parameter information includes parameters such as temperature and voltage inside the functional module, where the parameters inside the functional module cannot be directly obtained by using peripheral devices (such as a temperature sensor and a voltage sensor), so when the IP core is in the first operation mode, the feedback mode of the first parameter information may be that the processor (such as an MCU) queries the device to be tested according to a preset access address of the device to be tested, obtains the first parameter information, and writes the first parameter information into a configured register and then feeds back the first parameter information.
And when the operation mode of the IP core is in the second operation mode, acquiring second parameter information for feeding back the state of the device to be tested and feeding back the second parameter information. Specifically, the second parameter information includes parameters such as temperature, voltage and current of the device to be tested, and the parameters of the device to be tested can be directly measured through external devices such as a temperature sensor, a current sensor and an EEPROM register connected with the I2C interface of the functional module, so that when the IP core is in the second operation mode, the feedback mode of the second parameter information can query each peripheral device through a preset access address of each peripheral device, acquire state information monitored by each peripheral device, and feed back the acquired state information.
The feedback object is determined according to the requirement, for example, the power management module BMC at the server side needs to acquire and manage the state of the acceleration card waiting for the device to be tested, and then the first parameter information and the second parameter information are fed back to the power management module.
Therefore, by setting the first operation mode and the second operation mode for the IP cores of the functional module and periodically switching according to the first instruction, the detected state is fed back in different operation modes.
In an embodiment, periodically switching the operation mode of the IP core in the functional module includes:
the operation mode is initially a first operation mode;
And switching the operation mode into a second operation mode every a preset time period, and switching the operation mode into the first operation mode again after feeding back the second parameter information.
In this embodiment, since the parameters inside the functional module have a larger influence on the entire functional module, the operation mode is initially the first operation mode to monitor the state inside the functional module for a long time, that is, the duration of the first operation mode is longer in a period of a preset duration. The preset duration may be a period duration of the clock signal, or a duration of the system additionally set to the functional module, and in this embodiment, the preset duration is preferably a period duration of the clock signal, and if the first operation mode corresponds to a high level of the clock signal, the duration of the clock signal in the high level is longer, and the duration of the clock signal in the low level is shorter. When the operation mode is in the first operation mode, if the clock signal generates high-low potential change, the function module responds to the potential change to switch the operation mode from the first operation mode to the second operation mode, and after the function module feeds back the second parameter information, the operation mode is switched to the first operation mode again in a short time due to the short duration of the low level.
Further, when the operation mode is switched to the second operation mode, the processor can actively read the status information obtained by monitoring each peripheral device, and send the status information to the power management module BMC through the SMBUS bus of the PCIE interface on the device to be tested (i.e. the low-speed data channel in the drawing), and of course, the status information can also be sent to the power management module BMC through the high-speed data channel on the PCIE interface.
In summary, as shown in fig. 3 and fig. 4, taking a functional module as an FPGA as an example, the overall implementation process of the steps is as follows:
Firstly, setting an IP core of an FPGA as a first operation mode to acquire parameters in the FPGA, and presetting an access address of a device to be tested through software so that a micro control unit can inquire the device to be tested according to the access address of the device to be tested.
And secondly, the micro control unit periodically sends a clock signal to the FPGA, and the high level corresponds to a first operation mode and the low level corresponds to a second operation mode. If the clock signal is at a high level at this time, the current operation mode is the first operation mode, and when the device to be tested receives a data reading request sent by the power management module BMC at the server side, the control unit queries the device to be tested according to the access address of the device to be tested, acquires parameters in the FPGA, and feeds back the parameters to the power management module BMC by writing the parameters into a register. When the clock signal is at a low level, the current operation mode is switched to the second operation mode, access addresses of all peripheral devices (such as a temperature sensor and a current sensor) are preset through software, the server side or the micro control unit inquires all the peripheral devices through the peripheral device access addresses and obtains all the peripheral states, and the obtained peripheral states are actively sent to the power management module BMC through the SMBUS.
Because the time that the clock signal is at the low level is short, after the transmission is completed in the second operation mode, the clock signal is switched to the first operation mode soon, and the read request of the power management module BMC is continuously waited in the first operation mode.
In one embodiment, if the IP core is in the first operation mode, the method further includes:
monitoring first parameter information in real time, and storing the first parameter information into an information base;
correspondingly, feeding back the first parameter information includes:
Extracting first parameter information in the information base and feeding back the first parameter information.
In this embodiment, if the IP core is in the first operation mode, the first parameter information inside the functional module is stored in the information base in real time, and the access request of the power management module BMC is received in real time, and after receiving the second instruction sent by the power management module BMC to obtain the first parameter information, the microcontroller or the processor will read and feed back the latest first parameter information in the information base.
Another aspect of the embodiment of the present invention provides an information processing apparatus, including a device to be tested configured with a functional module, a first device, and a second device;
the first device is in communication connection with the functional module and is used for sending a first instruction to the functional module so as to periodically switch the operation mode of the IP core in the functional module;
the first device is further used for feeding back first parameter information representing the state of the functional module when the IP core is in a first operation mode;
The second device is used for feeding back second parameter information representing the state of the device to be tested when the IP core is in a second operation mode.
In this embodiment, as shown in fig. 2, the functional module may be an FPGA chip (Field Programmable GATE ARRAY ), a CPLD chip (Complex Programmable Logic Device, complex programmable logic device), or the like, and preferably the functional module is an FPGA chip. The device to be tested comprises an accelerator card, a display card, a sound card and the like, and the accelerator card is preferred as the device to be tested. The first device may be a micro control unit MCU, a central processing unit CPU, preferably the first device is a micro control unit MCU. The second device includes a temperature sensor, a current sensor, an EEPROM register, and the like.
When the micro control unit MCU is used, the micro control unit MCU sends a first instruction to the FPGA chip, the first instruction can be a periodic clock signal or a pulse signal so as to periodically switch the operation modes of the IP core in the functional module, the operation modes comprise a first operation mode and a second operation mode, when the micro control unit MCU is applied, the first operation mode can be enabled to correspond to the high level of the clock signal, the second operation mode can be enabled to correspond to the low level of the clock signal, when the clock signal is at the high level, the operation mode of the IP core is switched to the first operation mode, and when the clock signal is at the low level, the operation mode of the IP core is switched to the second operation mode. Specifically, the triggering mode of the first instruction is mainly triggered according to a local clock or an external clock, and the triggering mode comprises a high-level signal and a low-level signal. The functional module can configure the first operation mode and the second operation mode through a software program in advance, and after the functional module acquires the first instruction, the operation mode of the IP core is switched through the preset software program according to the clock high-low level signal.
The first parameter information comprises parameters such as temperature, voltage and the like in the functional module, and the parameters in the functional module cannot be directly acquired by using peripheral equipment (such as a temperature sensor, a voltage sensor and the like), so that when the IP core is in a first operation mode, the device to be detected is inquired and the first parameter information is acquired by the MCU according to a preset access address of the device to be detected, and the first parameter information is written into a configured register and fed back to a third device; the second parameter information comprises parameters such as temperature, voltage and current of the device to be tested, and the parameters of the device to be tested can be directly measured by a second device such as a temperature sensor, a current sensor and an EEPROM which are connected with the I2C interface of the functional module, so that when the IP core is in a second operation mode, the second device is used for inquiring each peripheral device through a preset access address of each peripheral device, acquiring state information monitored by each peripheral device, and acquiring and feeding back the second parameter information such as voltage and current to a third device. The third device is preferably a power management module BMC at the server side according to the requirement, and the power management module BMC needs to acquire and manage the state of the acceleration card waiting device.
Therefore, by setting the first operation mode and the second operation mode for the IP cores of the functional module and periodically switching according to the first instruction, the detected state is fed back in different operation modes.
In one embodiment, the first device is specifically configured to:
And sending a first instruction to the functional module at intervals of a preset time length to instruct the IP core to switch the operation mode to the second operation mode, and switching the operation mode to the first operation mode after the first device feeds back the second parameter information.
In this embodiment, since the parameters inside the FPGA chip have a greater influence on the whole FPGA chip, the operation mode is initially the first operation mode to monitor the state inside the FPGA chip in real time, that is, in a period of a preset duration, the duration in the first operation mode is longer. The preset duration may be a period duration of the clock signal, or a duration of the system additionally set to the functional module, and in this embodiment, the preset duration is preferably a period duration of the clock signal, and if the first operation mode corresponds to a high level of the clock signal, the duration of the clock signal in the high level is longer, and the duration of the clock signal in the low level is shorter. When the operation mode is in the first operation mode, if the clock signal generates high-low potential change, the function module responds to the potential change to switch the operation mode from the first operation mode to the second operation mode, and after the function module feeds back the second parameter information, the operation mode switches the vertical horse to the first operation mode again because the duration of the low level is shorter.
Further, when the operation mode is switched to the second operation mode, the processor can actively read the status information obtained by monitoring each peripheral device, and send the status information to the power management module BMC through the SMBUS bus of the PCIE interface on the device to be tested (i.e. the low-speed data channel in the drawing), and of course, the status information can also be sent to the power management module BMC through the high-speed data channel on the PCIE interface.
In one embodiment, the first device is specifically configured to:
monitoring first parameter information in real time, and storing the first parameter information into a register;
Correspondingly, when the first device feeds back the first parameter information, the first device is specifically configured to:
First parameter information in the register is extracted, and the first parameter information is fed back.
In this embodiment, if the IP core is in the first operation mode, the first parameter information in the FPGA chip is stored in the register in real time, and the access request of the power management module BMC is received in real time, and after receiving the second instruction sent by the power management module BMC to obtain the first parameter information, the MCU will read and feed back the latest first parameter information in the register.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely illustrative embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present invention, and the invention should be covered. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. An information processing method applied to a device under test configured with a functional module, the method comprising:
Based on a first instruction, periodically switching an operation mode of an IP core in the functional module, wherein the operation mode of the IP core comprises a first operation mode and a second operation mode which are configured in advance;
If the IP core is in a first operation mode, feeding back first parameter information representing the state of the functional module;
And if the IP core is in the second operation mode, feeding back second parameter information representing the state of the device to be tested.
2. The method of claim 1, the periodically switching the operation mode of the IP core in the functional module, comprising:
The operation mode is initially the first operation mode;
And switching the operation mode into the second operation mode every preset time period, and after feeding back the second parameter information, switching the operation mode into the first operation mode again.
3. The method of claim 1, if the IP core is in a first mode of operation, the method further comprising:
monitoring the first parameter information in real time, and storing the first parameter information into an information base;
correspondingly, the feeding back the first parameter information includes:
extracting first parameter information in the information base, and feeding back the first parameter information.
4. A method according to claim 1 or 3, said feeding back first parameter information comprising:
And receiving and responding to a second instruction to feed back the first parameter information.
5. The method of claim 1, the second parameter information comprising a temperature parameter and a voltage parameter.
6. An information processing apparatus includes a device under test configured with a functional module, a first device, and a second device;
the first device is in communication connection with the functional module and is used for sending a first instruction to the functional module so as to periodically switch the operation mode of the IP core in the functional module, wherein the operation mode of the IP core comprises a first operation mode and a second operation mode which are configured in advance;
The first device is further configured to feed back first parameter information that characterizes a state of the functional module when the IP core is in a first operation mode;
and the second device is used for feeding back second parameter information representing the state of the device to be tested when the IP core is in a second operation mode.
7. The apparatus of claim 6, the first means being specifically for:
and sending a first instruction to the functional module at intervals of a preset time length to instruct the IP core to switch the operation mode to the second operation mode, and after the first device feeds back the second parameter information, switching the operation mode to the first operation mode.
8. The apparatus of claim 6, the first means being specifically for:
monitoring the first parameter information in real time, and storing the first parameter information into a register;
correspondingly, when the first device feeds back the first parameter information, the first device is specifically configured to:
Extracting first parameter information in the register and feeding back the first parameter information.
9. The apparatus according to claim 6 or 8, wherein the first device is configured to, when feeding back the first parameter information:
And receiving and responding to a second instruction sent by the third device to acquire the first parameter information and feeding back the first parameter information to the third device.
10. The apparatus of claim 9, the first device being a micro control unit MCU, the second device comprising a temperature sensor, a current sensor, the third device being a power management device BMC, the functional module being an FPGA chip.
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| CN107506279A (en) * | 2017-08-18 | 2017-12-22 | 江苏微锐超算科技有限公司 | The Properties Control method and device of FPGA device |
| CN207115097U (en) * | 2017-07-19 | 2018-03-16 | 郑州云海信息技术有限公司 | A kind of FPGA isomeries accelerator card |
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| CN103970701B (en) * | 2014-05-28 | 2017-08-25 | 吉林大学 | The IP core of real time data synchronization collection based on field programmable gate array |
| CN105760053A (en) * | 2016-02-18 | 2016-07-13 | 联想(北京)有限公司 | Information processing method and electronic equipment |
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| CN207115097U (en) * | 2017-07-19 | 2018-03-16 | 郑州云海信息技术有限公司 | A kind of FPGA isomeries accelerator card |
| CN107506279A (en) * | 2017-08-18 | 2017-12-22 | 江苏微锐超算科技有限公司 | The Properties Control method and device of FPGA device |
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