CN112764308A - Method for improving OPC correction precision - Google Patents
Method for improving OPC correction precision Download PDFInfo
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- CN112764308A CN112764308A CN201911075154.6A CN201911075154A CN112764308A CN 112764308 A CN112764308 A CN 112764308A CN 201911075154 A CN201911075154 A CN 201911075154A CN 112764308 A CN112764308 A CN 112764308A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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Abstract
The invention provides a method for improving OPC correction precision, which modifies the distribution of sub-resolution auxiliary graphs by taking edge positioning errors between layout graphs and corrected graphs as the basis, adds or removes the sub-resolution auxiliary graphs, improves the OPC correction precision, improves a process window and meets the process requirements.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for improving OPC correction precision.
Background
According to Moore's law, the characteristic size of a chip is continuously reduced to reach a process node of 0.13 μm or below, and the used photoetching wavelength (193nm) is far larger than the Critical Dimension (CD), so that the optical proximity effect caused by diffraction, interference and the like becomes the critical prisoner influencing the photoetching process. To compensate for the effect of this effect, we directly modify the designed pattern and then do the lithography process. This iterative process of correction is called Optical Proximity Correction (OPC). The optical proximity effect correction solves the problem of deformation of the photoetching pattern, such as the phenomenon of line end shortening edge after photoetching, to the greatest extent possible.
In general, the spatial frequency and the aerial image of a pattern can be effectively improved by inserting a Sub Resolution Assist pattern (SRAF) around or inside the pattern, thereby improving the OPC accuracy.
With the continuous reduction of the characteristic dimension of the line width, the mask error factor of an exposed graph is also obviously increased, and correspondingly, the small fluctuation of the graph dimension of the mask can cause the huge fluctuation of the line width of the graph on a wafer, so that higher requirements are put forward for a process window, a certain yield is ensured, and the precision of the existing OPC correction cannot meet the requirements.
Disclosure of Invention
The invention aims to provide a method for improving OPC correction precision, which can improve OPC correction precision, improve a process window and meet process requirements.
In order to solve the above problems, the present invention provides a method for improving OPC correction accuracy, which comprises the following steps: (a) providing a layout graph; (b) adding a sub-resolution auxiliary graph at the periphery or inside of the layout graph; (c) correcting the layout graph by utilizing an OPC correction model to obtain a corrected graph; (d) obtaining the edge positioning error of the layout graph and the corrected graph; (e) comparing the absolute value of the edge positioning error with a preset value, when the absolute value of the edge positioning error is larger than or equal to the preset value, if the edge positioning error is a negative value, removing the sub-resolution auxiliary graph at the periphery of the layout graph of the area corresponding to the edge positioning error, or adding the sub-resolution auxiliary graph inside the layout graph of the area corresponding to the edge positioning error, and executing the step (f); if the edge positioning error is a positive value, adding a sub-resolution auxiliary graph at the periphery of the layout graph of the area corresponding to the edge positioning error, or removing the sub-resolution auxiliary graph inside the layout graph of the area corresponding to the edge positioning error, and executing the step (f); when the absolute value of the edge positioning error is smaller than the preset value, ending OPC correction; (f) and (d) correcting the corrected graph by utilizing an OPC correction model to obtain a new corrected graph, and executing the step (d).
Further, the edge positioning error is a difference between an edge of the layout graph and an edge of the corrected graph.
Further, the preset value is X% of the dimension of the layout graph, and the range of X is 5-10.
Further, the OPC correction model in step (c) and the OPC correction model in step (f) are the same model.
Further, before the step (d), the following steps are included: (c1) and (d) arranging a plurality of spaced marking lines on the layout graph, and in the step (d), taking the intersection points of the marking lines, the layout graph and the corrected graph as sampling points of the edge positioning error.
Further, in the same direction, the pitch of the marking lines is 1nm to 10 nm.
Further, the illustrated marker lines are equally spaced.
Further, a plurality of the marker lines are formed in a lattice shape.
Further, the mark line is perpendicular to the sub-resolution auxiliary pattern of the region.
Further, in the step (e), adding the sub-resolution auxiliary pattern includes: sub-resolution auxiliary patterns located on both sides of the region are connected.
The method has the advantages that the distribution of the sub-resolution auxiliary graph is modified by taking the edge positioning error between the layout graph and the corrected graph as the basis, and the sub-resolution auxiliary graph is added or removed, so that the OPC correction precision is improved, the process window is improved, and the process requirements are met.
Drawings
FIG. 1 is a flowchart illustrating the steps of a first embodiment of a method for improving OPC correction accuracy according to the present invention;
FIGS. 2A-2E are schematic diagrams illustrating a first embodiment of a method for improving OPC correction accuracy according to the present invention;
FIG. 3 is a schematic diagram of setting sampling points for the method of improving OPC correction accuracy according to the present invention;
FIG. 4 is a flowchart illustrating the steps of a second embodiment of the method for improving OPC correction accuracy according to the present invention;
fig. 5A to 5E are schematic diagrams illustrating a method for improving OPC correction accuracy according to a second embodiment of the present invention.
Detailed Description
The following describes a specific embodiment of the method for improving OPC correction accuracy according to the present invention in detail with reference to the accompanying drawings.
Fig. 1 is a flowchart illustrating steps of a first embodiment of a method for improving OPC correction accuracy according to the present invention, and referring to fig. 1, the method for improving OPC correction accuracy includes the following steps: step S10, providing a layout graph; step S11, adding sub-resolution auxiliary graphs at the periphery of the layout graph; step S12, correcting the layout graph by utilizing an OPC correction model to obtain a corrected graph; step S13, obtaining the edge positioning error of the layout graph and the corrected graph; step S14, comparing the absolute value of the edge positioning error with a preset value, when the absolute value of the edge positioning error is larger than or equal to the preset value, if the edge positioning error is a negative value, removing the sub-resolution auxiliary graph at the periphery of the layout graph of the area corresponding to the edge positioning error, and executing the step S15; if the edge positioning error is a positive value, adding a sub-resolution auxiliary graph at the periphery of the layout graph in the area corresponding to the edge positioning error, and executing the step S15; when the absolute value of the edge positioning error is smaller than the preset value, ending OPC correction; step S15, the corrected pattern is corrected by the OPC correction model to obtain a new corrected pattern, and step S13 is executed. The concrete description is as follows.
Referring to step S10 and fig. 2A, a layout graph 200 is provided. The layout pattern 200 is a pattern that is actually expected to be formed on a silicon wafer.
Referring to step S11 and fig. 2B, a sub-resolution auxiliary pattern is added on the periphery of the layout pattern 200. In this step, the sub-resolution auxiliary pattern is added to the periphery of the layout pattern 200 according to the addition rule of the sub-resolution auxiliary pattern, which is a known rule and is not described again. In fig. 2B, three sub-resolution auxiliary patterns 210, 220, and 230 are added to the periphery of the layout pattern 200. The sub-resolution auxiliary patterns 210 and 220 correspond to line sides of the layout pattern 200, and the sub-resolution auxiliary pattern 230 corresponds to a line end of the layout pattern 200.
Referring to step S12 and fig. 2C, the layout graph 200 is corrected by using an OPC correction model to obtain a corrected graph 240. The OPC correction model may be a known model.
Referring to step S13 and fig. 2C, an edge positioning error E of the layout pattern 200 and the corrected pattern 240 is obtained. Wherein, the Edge Placement Error (EPE) is a difference between an Edge of the layout graph 200 and an Edge of the corrected graph 240. Specifically, in this step, the value of the edge positioning error is obtained.
With the change of the shapes of the layout pattern 200 and the corrected pattern 240, the edge positioning errors of the layout pattern 200 and the corrected pattern 240 are also changed continuously, and in this step, a plurality of edge positioning errors E need to be collected.
Furthermore, sampling points can be set according to a certain rule to collect the edge positioning error E. One method of setting the sampling points is exemplified below.
Referring to fig. 3, after steps S10, S11 and S12 are performed, a plurality of spaced mark lines 301 are arranged on the layout pattern 300, the mark lines 301, the layout pattern 300 and the corrected pattern 340 have intersection points, and a distance between the two intersection points is the edge positioning error E. In step S13, a plurality of edge positioning errors E are obtained by using the intersection points of the marker line 301, the layout pattern 300, and the corrected pattern 340 as sampling points of the edge positioning errors. Several intersections are schematically indicated in fig. 3 with black solid dots.
The arrangement of the marker lines 301 is related to sub-resolution auxiliary patterns distributed at the periphery of the layout pattern 300. As shown in fig. 3, sub-resolution auxiliary patterns 310 extending along the X direction and sub-resolution auxiliary patterns 320 extending along the Y direction are distributed on the periphery of the layout pattern 300, the mark lines 301 include mark lines extending along the X direction and mark lines extending along the Y direction, and the mark lines 301 form a grid structure. The sub-resolution auxiliary pattern 310 extending along the X direction corresponds to the mark line 301 extending along the Y direction, the sub-resolution auxiliary pattern 320 extending along the Y direction corresponds to the mark line 301 extending along the X direction, that is, the intersection point of the mark line 301 extending along the Y direction, the layout pattern 300 and the corrected pattern 340 is used as a sampling point of the edge positioning error, and the edge positioning error obtained at the sampling point can be used as a basis for subsequently judging whether to add or remove the sub-resolution auxiliary pattern in the X direction; the intersection point of the mark line 301 extending along the X direction, the layout pattern 300 and the corrected pattern 340 is used as a sampling point of the edge positioning error, and the edge positioning error obtained at the sampling point can be used as a basis for subsequently judging whether to add or remove the sub-resolution auxiliary pattern in the Y direction.
Wherein the marking line 301 is perpendicular to the sub-resolution auxiliary pattern of the region. Specifically, as shown in fig. 3, the sub-resolution auxiliary patterns 320 extending in the Y direction are perpendicular to the mark lines 301 extending in the X direction, and the sub-resolution auxiliary patterns 310 extending in the X direction are perpendicular to the mark lines 301 extending in the Y direction.
Preferably, the pitch of the mark lines 301 is 1nm to 10nm in the same direction. For example, the mark lines 301 extending in the Y direction are parallel to each other in the X direction and are arranged at a pitch of 1nm to 10nm, and the mark lines 301 extending in the X direction are parallel to each other in the Y direction and are arranged at a pitch of 1nm to 10 nm. Preferably, the marker lines 301 are arranged at equal intervals, so that the sampling points can be uniformly distributed, and the sampling regularity is improved. It can be understood that the smaller the pitch of the illustrated marker lines 301, the denser the distribution of the sampling points is, and the more accurate the obtained edge positioning error is, and if the pitch of the marker lines 301 is too large, the sparseness of the distribution of the sampling points is caused, and the obtained edge positioning error is inaccurate.
The above is only one embodiment of the method for setting the sampling point, and the present invention may also sample other known methods for sampling, which are not described herein again.
When the edge of the corrected graph 240 exceeds the edge of the layout graph 200, the edge positioning error E is a negative value, as shown by a line end position (an area indicated by an arrow a) in fig. 2C (i.e., an area corresponding to the sub-resolution auxiliary graph 230); when the edge of the corrected pattern 240 is within the edge of the layout pattern 200, the edge positioning error is a positive value, as shown by the line-side position (the region indicated by the arrow B) in fig. 2C (i.e., the region corresponding to the spaced position of the sub-resolution auxiliary patterns 210 and 220).
Referring to step S14 and fig. 2D, the absolute value of the edge positioning error E is compared with a predetermined value. The preset value is X% of the size of the layout graph 200, and the range of X is 5-10%. That is, the preset value may be a value within a range of 5% to 10% of the size of the layout graph 200. In this embodiment, the preset value is 5% of the size of the layout graph 200, which can further improve the OPC correction accuracy. In other specific embodiments of the present invention, the preset values are 6%, 7%, 8%, 9%, 10%, and the like of the size of the layout graph 200.
When the absolute value of the edge positioning error E is greater than or equal to the preset value, there are two cases:
the edge positioning error E is a negative value, that is, the edge of the corrected graph 240 exceeds the edge of the layout graph 200, as shown by an arrow a in fig. 2D. In this case, the edge of the corrected pattern 240 needs to be narrowed down to fit the edge of the layout pattern 200. If the edge positioning error E is a negative value, removing the sub-resolution auxiliary graph at the periphery of the layout graph 200 in the area corresponding to the edge positioning error E. As shown in fig. 2D, a portion of the sub-resolution auxiliary pattern 230 corresponding to the region indicated by the arrow a is removed, and both ends of the sub-resolution auxiliary pattern 230 are remained, and the removed region is schematically illustrated by a dotted line in fig. 2D.
The edge positioning error E is a positive value, that is, the edge of the corrected graph 240 is within the edge of the layout graph 200, as shown by an arrow B in fig. 2D. In this case, it is necessary to extend the edge of the corrected pattern 240 so as to coincide with the edge of the layout pattern 200. And if the edge positioning error E is a positive value, adding a sub-resolution auxiliary graph at the periphery of the layout graph 200 in the area corresponding to the edge positioning error E. As shown in fig. 2D, a sub-resolution auxiliary pattern 250 is added at a position corresponding to the region indicated by the arrow B, i.e., the region between the sub-resolution auxiliary patterns 210 and 220, and the sub-resolution auxiliary pattern 250 is shown by hatching. Preferably, the sub-resolution auxiliary patterns 210 and 220 may be directly connected, and then the sub-resolution auxiliary patterns may be added at positions corresponding to the regions indicated by the arrows B.
When the absolute value of the edge positioning error E is smaller than the preset value, it indicates that the layout pattern 200 is substantially consistent with the corrected pattern 240, and the sub-resolution auxiliary pattern does not need to be added or removed in the region. And when all the areas of the layout graph and the corrected graph 240 are basically matched, namely the absolute value of the edge positioning error E of all the areas of the layout graph and the corrected graph 240 is smaller than the preset value, ending the OPC correction to form a formal layout graph.
In step S14, after the sub-resolution auxiliary pattern is adjusted, in order to verify whether a correct pattern can be obtained after the adjustment, step S15 is executed: referring to fig. 2E, the corrected graph 240 is corrected by using an OPC correction model to obtain a new corrected graph 260, and the steps S13 and S14 are performed on the new corrected graph until the absolute value of the edge positioning error E of all the areas of the layout graph and the corrected graph 240 is smaller than the preset value, and then the OPC correction is finished to form a formal layout graph.
The OPC correction models in steps S12 and S15 are the same model, which can ensure the consistency of the correction criteria.
The method for improving the OPC correction precision modifies the distribution of the sub-resolution auxiliary graph by taking the edge positioning error between the layout graph and the corrected graph as a basis, adds or removes the sub-resolution auxiliary graph, improves the OPC correction precision, improves a process window and meets the process requirements.
In the first embodiment of the present invention, the edge positioning error between the layout pattern and the corrected pattern is used as a basis to modify the distribution of the sub-resolution auxiliary patterns at the periphery of the layout pattern, which can make the size of the main pattern meet the requirement, while in some areas of the layout pattern, the sub-resolution auxiliary patterns need to be arranged inside the main pattern, for example, in some areas of the layout pattern, in order to ensure that the size of the space between two main patterns meets the requirement, the sub-resolution auxiliary patterns need to be arranged inside the main pattern, so the edge positioning error between the layout pattern and the corrected pattern is used as a basis to modify the distribution of the sub-resolution auxiliary patterns inside the layout pattern, so that the size of the space between two main patterns meets the requirement. In view of the above, the present invention provides a second embodiment.
The second embodiment is different from the first embodiment in that the modification direction of the sub-resolution auxiliary pattern is different according to the edge positioning error of the layout pattern and the corrected pattern. Specifically, fig. 4 is a flowchart illustrating steps of a second embodiment of the method for improving OPC correction accuracy according to the present invention, please refer to fig. 4, wherein the method for improving OPC correction accuracy comprises the following steps: step S40, providing a layout graph; step S41, adding a sub-resolution auxiliary graph inside the layout graph; step S42, correcting the layout graph by utilizing an OPC correction model to obtain a corrected graph; step S43, obtaining the edge positioning error of the layout graph and the corrected graph; step S44, comparing the absolute value of the edge positioning error with a preset value, when the absolute value of the edge positioning error is larger than or equal to the preset value, if the edge positioning error is a negative value, adding a sub-resolution auxiliary graph inside the layout graph of the area corresponding to the edge positioning error, and executing step S45; if the edge positioning error is a positive value, removing the sub-resolution auxiliary graph inside the layout graph of the area corresponding to the edge positioning error, and executing the step S45; when the absolute value of the edge positioning error is smaller than the preset value, ending OPC correction; step S45, the corrected pattern is corrected by the OPC correction model to obtain a new corrected pattern, and step S43 is executed.
Referring to step S40 and fig. 5A, a layout pattern 400 is provided. The layout pattern 400 is a pattern that is actually expected to be formed on a silicon wafer.
Referring to step S41 and fig. 5B, a sub-resolution auxiliary pattern 410 is added inside the layout pattern 400. In this step, the sub-resolution auxiliary pattern is added inside the layout pattern 400 according to the addition rule of the sub-resolution auxiliary pattern, which is a known rule and is not described again.
Referring to step S42 and fig. 5C, the layout graph 400 is corrected by using an OPC correction model to obtain a corrected graph 440. The OPC correction model may be a known model.
Referring to step S43 and fig. 5C, an edge positioning error E of the layout pattern 400 and the corrected pattern 440 is obtained. Step S43 of the present embodiment is the same as step S13 of the first embodiment, and is not repeated here.
When the edge of the corrected graph 440 exceeds the edge of the layout graph 400, the edge positioning error E is a negative value; when the edge of the corrected pattern 440 is within the edge of the layout pattern 400, the edge placement error is positive, as shown in fig. 5C for the line end position (the area indicated by the arrow a). In fig. 5C, the situation that the edge of the corrected pattern 440 exceeds the edge of the layout pattern 400 is not shown.
Referring to step S44 and fig. 5D, the absolute value of the edge positioning error E is compared with a predetermined value. The value of the preset value is the same as that of the first embodiment, and is not described again.
When the absolute value of the edge positioning error E is greater than or equal to the preset value, there are two cases:
the edge positioning error E is a positive value, that is, the edge of the corrected graph 440 is within the edge of the layout graph 400, as shown by the area indicated by the arrow B in fig. 5D. In this case, it is necessary to extend the edge of the corrected pattern 440 so as to coincide with the edge of the layout pattern 400. If the edge positioning error E is a positive value, the sub-resolution auxiliary graph 410 inside the layout graph 400 in the region corresponding to the edge positioning error E is removed. As shown in fig. 5D, the sub-resolution auxiliary pattern 410 is completely or partially removed at a position corresponding to the area indicated by the arrow a. In the present embodiment, the sub-resolution auxiliary pattern is partially removed, and the removed portion is illustrated by a dotted line.
The edge positioning error E is a negative value, that is, the edge of the corrected graph 440 exceeds the edge of the layout graph 400, which is not shown in the drawing. In this case, the edge of the corrected pattern 440 needs to be narrowed to fit the edge of the layout pattern 400. If the edge positioning error E is a negative value, adding a sub-resolution auxiliary graph inside the layout graph 400 of the area corresponding to the edge positioning error E.
When the absolute value of the edge positioning error E is smaller than the preset value, it indicates that the layout pattern 400 is substantially consistent with the corrected pattern 440, and the sub-resolution auxiliary pattern does not need to be added or removed in the region. And when the layout graph is basically consistent with all the areas of the corrected graph 440, namely the absolute value of the edge positioning error E of all the areas of the layout graph and the corrected graph 440 is smaller than the preset value, ending the OPC correction to form a formal layout graph.
In step S44, after the sub-resolution auxiliary pattern is adjusted, in order to verify whether a correct pattern can be obtained after the adjustment, step S45 is executed: referring to fig. 5E, the corrected graph 440 is corrected by using an OPC correction model to obtain a new corrected graph 460, and step S43 and step S44 are performed on the new corrected graph 460 until the absolute value of the edge positioning error E of all areas of the layout graph and the corrected graph is smaller than the preset value, and then the OPC correction is finished to form a formal layout graph.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for improving OPC correction precision is characterized by comprising the following steps:
(a) providing a layout graph;
(b) adding a sub-resolution auxiliary graph at the periphery or inside of the layout graph;
(c) correcting the layout graph by utilizing an OPC correction model to obtain a corrected graph;
(d) obtaining the edge positioning error of the layout graph and the corrected graph;
(e) comparing the absolute value of the edge positioning error with a preset value, when the absolute value of the edge positioning error is larger than or equal to the preset value, if the edge positioning error is a negative value, removing the sub-resolution auxiliary graph at the periphery of the layout graph of the area corresponding to the edge positioning error, or adding the sub-resolution auxiliary graph inside the layout graph of the area corresponding to the edge positioning error, and executing the step (f); if the edge positioning error is a positive value, adding a sub-resolution auxiliary graph at the periphery of the layout graph of the area corresponding to the edge positioning error, or removing the sub-resolution auxiliary graph inside the layout graph of the area corresponding to the edge positioning error, and executing the step (f); when the absolute value of the edge positioning error is smaller than the preset value, ending OPC correction;
(f) and (d) correcting the corrected graph by utilizing an OPC correction model to obtain a new corrected graph, and executing the step (d).
2. The method according to claim 1, wherein the edge positioning error is a difference between an edge of the layout pattern and an edge of the corrected pattern.
3. The method for improving OPC correction accuracy according to claim 1, wherein the preset value is X% of the dimension of the layout graph, and the range of X is 5-10.
4. The method for improving OPC correction accuracy of claim 1, wherein the OPC correction model in step (c) and the OPC correction model in step (f) are the same model.
5. The method for improving OPC correction accuracy as claimed in claim 1, further comprising the following steps before step (d): (c1) and (d) arranging a plurality of spaced marking lines on the layout graph, and in the step (d), taking the intersection points of the marking lines, the layout graph and the corrected graph as sampling points of the edge positioning error.
6. The method for improving OPC correction accuracy according to claim 5, wherein the pitch of the mark lines is 1nm to 10nm in the same direction.
7. The method for improving OPC correction accuracy as claimed in claim 6, wherein said mark lines are set at equal intervals.
8. The method of claim 5, wherein a plurality of said marks are formed in a grid pattern.
9. The method of claim 5, wherein the mark line is perpendicular to the sub-resolution auxiliary pattern in the area.
10. The method for improving OPC correction accuracy of claim 1, wherein the adding of the sub-resolution auxiliary pattern in the step (e) comprises: sub-resolution auxiliary patterns located on both sides of the region are connected.
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| CN114415466A (en) * | 2022-03-29 | 2022-04-29 | 合肥晶合集成电路股份有限公司 | Method and system for correcting layout graph |
| CN115933305A (en) * | 2023-01-29 | 2023-04-07 | 合肥晶合集成电路股份有限公司 | Method, device, equipment and medium for correcting photomask graph |
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