CN112751495A - Multi-level frequency converter chopping brake control method and device - Google Patents
Multi-level frequency converter chopping brake control method and device Download PDFInfo
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- CN112751495A CN112751495A CN202011643831.2A CN202011643831A CN112751495A CN 112751495 A CN112751495 A CN 112751495A CN 202011643831 A CN202011643831 A CN 202011643831A CN 112751495 A CN112751495 A CN 112751495A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electric Propulsion And Braking For Vehicles (AREA)
Abstract
The invention discloses a chopping brake control method for a multilevel frequency converter, which comprises the following steps: acquiring voltage values at two ends of each sub-bus and a full bus voltage feedback value in the multi-level frequency converter, calculating a voltage equalization coefficient of each sub-bus according to the voltage values at the two ends of each sub-bus, carrying out amplitude limiting on the voltage equalization coefficient of each sub-bus, carrying out proportional integral adjustment calculation on the full bus voltage, and limiting an output result of the proportional integral adjustment of the full bus voltage; modifying and amplitude limiting the full bus chopping modulation wave according to the amplitude-limited voltage equalization coefficient of each sub-bus, and obtaining the chopping modulation wave of each sub-bus; and comparing the chopped wave modulation waves of the respective sub-buses with a carrier to generate a PWM signal. The method solves the problem that a chopper brake circuit cannot be applied due to the withstand voltage of a power semiconductor device in a high-voltage application occasion, and simultaneously realizes the dynamic balance of a plurality of sub-bus voltages in the discharging process.
Description
Technical Field
The invention relates to the field of frequency converter control, in particular to a method and a device for controlling chopping braking of a multi-level frequency converter.
Background
With the continuous increase of the capacity of the frequency converter, the voltage grade of the frequency converter is continuously improved, and the mode of improving the output voltage through the multi-level topology structure is considered to be the optimal strategy for improving the output voltage at present. The difficulty with this approach is that the individual sub-bus voltages must be dynamically balanced or otherwise cause torque ripple in the motor.
In the prior art, chopping discharge is performed on a full direct current bus of a frequency converter, and the technical means adopts a mode that a power semiconductor device is connected in series for chopping to realize discharge on a high direct current voltage bus. The prior art also discloses a method for discharging a plurality of sub-buses of a frequency converter. The method can cause the voltage of each sub-bus to be unbalanced, cause adverse effects on the control performance of the frequency converter, and cause the torque vibration or overcurrent faults of the motor when the control performance is serious.
How to realize chopping discharge of the high-voltage multi-level frequency converter and keep dynamic balance of voltages of all the sub-buses in the discharge process is a key factor for safe and reliable operation of a speed regulating system of the high-voltage high-power multi-level frequency converter.
Disclosure of Invention
The invention aims to provide a chopping brake control method and a chopping brake control device of a multilevel frequency converter, which are simple to control and high in practicability, so that the problems in the background art are solved.
In order to achieve the purpose, the invention provides the following technical scheme: a chopping brake control method for a multilevel frequency converter comprises the following steps:
acquiring voltage values at two ends of each sub-bus and a full-bus voltage feedback value in the multi-level frequency converter;
calculating voltage equalization coefficients of the sub-buses according to voltage values at two ends of the sub-buses, and carrying out amplitude limiting on the voltage equalization coefficients of the sub-buses;
carrying out proportional integral adjustment calculation on the full bus voltage, and limiting the output result of the proportional integral adjustment of the full bus voltage;
the output result of the defined full bus voltage proportional integral adjustment is used as a full bus chopping modulation wave;
modifying and amplitude limiting the full bus chopping modulation wave according to the amplitude-limited voltage equalization coefficient of each sub-bus, and obtaining the chopping modulation wave of each sub-bus;
and comparing the chopped wave modulation waves of the respective sub-buses with a carrier to generate a PWM signal.
Preferably, the method includes the steps of calculating voltage equalization coefficients of the respective sub-buses according to voltage values at two ends of the respective sub-buses, and limiting the voltage equalization coefficients of the respective sub-buses, and includes:
calculating an expected equilibrium voltage value of the current working state;
calculating the balance coefficient of each sub-bus voltage;
the equalization coefficient of each sub-bus voltage is clipped so that the coefficient value is always limited to a value between plus or minus 1.
Preferably, the method for calculating the expected equilibrium voltage value includes: accumulating the voltage values of the sub-buses, and dividing the accumulated value by the number of the sub-buses to obtain an expected equilibrium voltage value Udcave。
Preferably, the equalization coefficient is obtained by the following formula, wherein Udc(N) is N-1 direct current input voltage values of the N-level frequency converter, and N is the level number of the multi-level frequency converter;
preferably, the proportional-integral adjustment calculation is performed on the full bus voltage, and an output result of the proportional-integral adjustment on the full bus voltage is limited, and the specific method includes:
calculating the sum of all the voltage values of the sub-buses;
when the full bus voltage feedback value is higher than the chopping brake trigger voltage value, starting full bus voltage proportional integral regulation; the chopping brake trigger voltage value is set to be 1.1 times of the no-load full-direct-current input voltage;
carrying out proportional integral adjustment calculation on the full bus voltage;
and limiting the output result of the proportional integral adjustment of the full bus voltage.
Preferably, the calculation method for the proportional-integral adjustment of the full bus voltage comprises the following steps: comparing the expected full bus voltage value with a full bus voltage feedback value, and performing proportional-integral adjustment operation on the compared deviation;
the proportional-integral regulation control equation is as follows, wherein Kp is a proportional link coefficient, Ki is an integral link coefficient, e (t) is a difference value between an expected full voltage value and a full bus voltage feedback value, and u (t) is a calculation result of proportional-integral regulation:
the expected full bus voltage value is an expected value which is set manually according to rated parameters of the frequency converter, and the expected full bus voltage value is set as a no-load full bus voltage value.
Preferably, the output result of the proportional-integral adjustment of the full bus voltage is defined, and the specific method includes: limiting the output result to zero when the output result is less than zero; when the output result is greater than the upper limit value, the output result is equal to the upper limit value; the upper limit value is the minimum value of the maximum power consumption of the chopper braking circuit in a short time and the maximum working current of the chopper circuit.
Preferably, the full bus chopping modulation wave is corrected and amplitude-limited according to the voltage equalization coefficient of each limited sub-bus, and the chopping modulation wave of each sub-bus is obtained, and the specific method comprises the following steps:
synthesizing the full bus chopping modulation wave and the voltage equalization coefficient of each sub-bus, and calculating the chopping modulation wave of each sub-bus; the formula for calculating the chopped wave modulation wave of each branch line is as follows:
Umn＝Uc×(1+fn)n∈(1～N-1)
wherein Uc is the calculated full bus chopping modulation wave, fn is the voltage balance coefficient of each sub-bus calculated in step S1, and UmnFor a chopped wave modulation wave of each sub-bus, N belongs to (1-N-1) N and is the level number of the multi-level frequency converter;
carrying out amplitude limiting processing on each branch bus modulation wave, and limiting to zero when each branch bus chopping modulation wave is less than zero; when each of the chopper-modulated waves of the denominator lines is larger than the upper limit value allowed by the chopper brake circuit, the limit is equal to the upper limit value.
The invention also provides a chopping brake control device of the multilevel frequency converter, which is characterized in that: the device comprises a chopping brake main loop unit and a chopping brake control unit,
the chopping brake main loop unit comprises a capacitor unit, a diode, an IGBT and a resistor, wherein,
the capacitor unit consists of 1 capacitor or a plurality of capacitors connected in series and in parallel;
the anode of the diode is connected with the collector of the IGBT in series and then connected with the two ends of the capacitor in parallel;
or the cathode of the diode is connected with the emitter of the IGBT in series and then connected with the two ends of the capacitor in parallel;
the diode is connected with a plurality of resistors in parallel;
the chopping brake control unit is used for controlling the controllable semiconductor device in the chopping brake main loop unit in a PWM pulse mode; when the controllable semiconductor device is switched on, the capacitor discharges the resistor through the controllable semiconductor device, and when the controllable semiconductor device is switched off, the resistor and the connecting cable follow current through the uncontrollable semiconductor device.
Preferably, the chopping brake control unit comprises a voltage acquisition module, an equalization coefficient calculation module, a full bus chopping modulation wave calculation module, a bus bar chopping modulation wave calculation module and a PWM pulse generation module, wherein,
the voltage acquisition module is used for acquiring voltage values of the sub-buses;
the equalization coefficient calculation module is used for calculating the imbalance coefficient among the sub-buses and carrying out amplitude limiting on the equalization coefficient of the voltage of each sub-bus;
the full bus chopping modulation wave calculation module is used for performing proportional integral adjustment calculation on the full bus voltage and limiting the output result of the proportional integral adjustment of the full bus voltage;
the branch bus chopping modulation wave calculation module is used for correcting and amplitude limiting the output result of the limited full bus voltage proportional integral adjustment according to the amplitude-limited branch bus voltage equalization coefficient to obtain the chopping modulation wave of each branch bus;
and the PWM pulse generation module is used for comparing the chopped wave modulation wave of each sub-bus with a carrier to generate a PWM signal.
Has the advantages that:
the invention effectively solves the problem that a chopping brake circuit cannot be applied due to the withstand voltage of a power semiconductor device in a high-voltage application occasion by chopping the voltages of a plurality of sub-buses of the multi-level frequency converter to control the discharge and simultaneously considering the unbalance control of the voltages of the sub-buses in the discharge process of the multi-level frequency converter, and simultaneously realizes the dynamic balance of the voltages of the plurality of sub-buses in the discharge process.
Description of the drawings:
in order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
Fig. 1 is a flowchart of a chopping brake control method for a multilevel frequency converter according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating a calculation process of voltage equalization coefficients of each sub-bus according to an embodiment of the present invention;
FIG. 3 is a flowchart of a full bus voltage proportional integral adjustment provided in accordance with an embodiment of the present invention;
fig. 4 is a flowchart illustrating a chopper modulated wave correction process according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a chopper brake unit with an upper portion connected by a resistor according to the present invention;
FIG. 6 is a circuit diagram of a chopper brake unit with a lower portion connected to a resistor according to the present invention;
FIG. 7 is a schematic diagram of a circuit connection relationship of a main loop unit in a multi-level converter according to another embodiment of the present invention;
fig. 8 is a schematic composition diagram of a multilevel converter chopping brake control unit according to another embodiment of the present invention.
Detailed Description
In order to further understand and understand the present invention, the technical solutions of the present invention are further described below with reference to the accompanying drawings and the detailed description.
The embodiment of the invention provides a chopping brake control method for a multilevel frequency converter, which can independently discharge each sub-bus of a multilevel and simultaneously realize voltage balance control of each sub-bus in the discharging process. Fig. 1 is a flowchart of a control method for chopper braking of a multilevel converter according to an embodiment of the present invention, where the method includes the following steps:
step S0: and acquiring voltage values at two ends of each sub-bus and a full bus voltage feedback value in the multi-level frequency converter.
Step S1: and calculating the voltage equalization coefficient of each sub-bus according to the voltage values at the two ends of each sub-bus, and carrying out amplitude limiting on the voltage equalization coefficient of each sub-bus.
Step S2: and carrying out proportional integral adjustment calculation on the full bus voltage, and limiting an output result of the proportional integral adjustment on the full bus voltage.
Step S3: and proportionally integrating and adjusting the defined full bus voltage to obtain an output result as a full bus chopping modulation wave.
Step S4: and modifying and amplitude limiting the full bus chopping modulation wave according to the voltage equalization coefficient of each sub-bus for amplitude limiting, and acquiring the chopping modulation wave of each sub-bus.
Step S5: and comparing the chopped wave modulation waves of the respective sub-buses with a carrier to generate a PWM signal.
Fig. 2 is a flowchart of calculating voltage equalization coefficients of respective sub-buses according to another embodiment of the present invention, where the method includes the following steps:
step S10: and calculating the expected equilibrium voltage value of the current working state.
Step S11: and calculating the balance coefficient of each sub-bus voltage.
Step S12: clipping is performed on each voltage equalization coefficient, defining the coefficient value to be between plus or minus 1.
Further, the method for calculating the expected equilibrium voltage value comprises the following steps: accumulating the voltage values of the sub-buses, and dividing the accumulated value by the number of the sub-buses to obtain an expected equilibrium voltage value Udcave。
Further, the equalization coefficient is obtained by the following formula, wherein N is the number of levels of the multi-level frequency converter.
Fig. 3 is a flowchart of calculating proportional-integral adjustment of the full bus voltage according to another embodiment of the present invention, where the method includes the following steps:
step S20: and calculating the accumulated sum of all the voltage values of the sub-buses.
Step S21: and when the full bus voltage feedback value is higher than the chopping brake trigger voltage value, starting the full bus voltage proportional integral regulation.
In this embodiment, the chopping brake trigger voltage value is set to be 1.1 times of the no-load full-dc input voltage.
Step S22: and (4) carrying out proportional integral adjustment calculation on the full bus voltage.
Step S23: and limiting the output result of the proportional integral adjustment of the full bus voltage.
Further, the calculation method for proportional integral adjustment of the full bus voltage is as follows: and comparing the expected full bus voltage value with the full bus voltage feedback value, and performing proportional-integral adjustment operation on the compared deviation. The proportional integral regulation control equation is as follows, wherein Kp is a proportional link coefficient, Ki is an integral link coefficient, e (t) is a difference value between an expected full voltage value and a full bus voltage feedback value, and u (t) is a calculation result of proportional integral regulation.
The expected full bus voltage value is an expected value which is manually set according to rated parameters of the frequency converter. In this embodiment, the desired full bus voltage value is set to the unloaded full bus voltage value.
Further, the output result of the proportional integral adjustment of the full bus voltage is limited, and the specific implementation is limited as follows: limiting the output result to zero when the output result is less than zero; and when the output result is greater than the upper limit value, the output result is equal to the upper limit value. In this embodiment, the upper limit value is a minimum value of a maximum value of power consumption of the chopper brake circuit during a short time and a maximum operating current of the chopper circuit.
Fig. 4 is a flowchart of a chopper-modulated wave correction method according to another embodiment of the present invention, where the method includes the following steps:
step S40: and integrating the full bus chopping modulation wave and the voltage equalization coefficient of each sub-bus, and calculating the chopping modulation wave of each sub-bus. The formula for calculating the chopped wave modulation wave of each branch line is as follows,
Umn＝Uc×(1+fn)n∈(1～N-1)
wherein Uc is the full bus chopper modulation wave calculated in step S2, fn is the voltage balance coefficient of each sub-bus calculated in step S1, Umn is the chopper modulation wave of each sub-bus, and N is the number of levels of the multilevel converter (from 1 to N-1).
Step S41: and carrying out amplitude limiting processing on each of the denominator modulation waves.
When the chopped wave modulation wave of each branch line is less than zero, limiting to zero; and when each bus chopping modulation wave is larger than the upper limit value allowed by the chopping brake circuit, the bus chopping modulation wave is equal to the upper limit value.
The invention also provides a multi-level frequency converter chopping brake control device, aiming at the problem that the voltage of a branch bus is unbalanced due to chopping braking in the multi-level frequency converter. The device comprises a chopping brake main loop unit and a chopping brake control device.
The chopping brake main loop unit has two circuit topologies, as shown in fig. 5 and fig. 6. The topological structure comprises a capacitance unit, a diode 2, an IGBT3 and a resistor 4. The capacitor unit 1 consists of 1 capacitor or a plurality of capacitors connected in series and in parallel; the anode of the diode 2 is connected in series with the collector of the IGBT3 and then connected in parallel with the two ends of the capacitor 1; or the cathode of the diode 2 is connected in series with the emitter of the IGBT3 and then connected in parallel to two ends of the capacitor 1; the diode 2 is connected in parallel with a plurality of resistors 4.
The circuit connection relationship of the chopping brake main loop unit in the multi-level frequency converter is shown in fig. 7, N-level frequency conversion is provided with N-1 component buses, and each component bus is connected with one chopping brake unit in parallel.
Further, the chopping brake control unit is used for controlling the controllable semiconductor device in the chopping brake main loop unit in the form of PWM (pulse-width modulation) pulses; when the controllable semiconductor device is switched on, the capacitor discharges the resistor through the controllable semiconductor device, and when the controllable semiconductor device is switched off, the resistor and the connecting cable follow current through the uncontrollable semiconductor device.
Fig. 8 is a schematic diagram of a chopper brake control unit, where the chopper brake control unit includes a voltage acquisition module 5, an equalization coefficient calculation module 6, a full bus chopper modulation wave calculation module 7, a sub bus chopper modulation wave calculation module 8, and a PWM pulse generation module 9.
The voltage acquisition module 5 is used for acquiring voltage values of the sub-buses;
the equalization coefficient calculation module 6 is used for calculating the imbalance coefficient among the sub-buses and carrying out amplitude limiting on the equalization coefficient of the voltage of each sub-bus;
the full bus chopping modulation wave calculation module 7 is used for performing proportional integral adjustment calculation on the full bus voltage and limiting the output result of the proportional integral adjustment of the full bus voltage;
the sub-bus chopping modulation wave calculation module 8 is used for correcting and amplitude limiting the output result of the limited full-bus voltage proportional integral adjustment according to the amplitude-limited sub-bus voltage equalization coefficient, and acquiring the chopping modulation wave of each sub-bus;
and the PWM pulse generation module 9 is used for comparing the chopped wave brake modulation wave with the carrier wave to generate a PWM signal.
The invention performs chopping control on the voltages of the plurality of the sub-buses of the multi-level frequency converter to discharge, and simultaneously controls the unbalance of the voltages of the plurality of the sub-buses in the discharging process of the multi-level frequency converter. The method effectively solves the problem that a chopper brake circuit cannot be applied due to the withstand voltage of a power semiconductor device in a high-voltage application occasion, and simultaneously realizes the dynamic balance of a plurality of sub-bus voltages in the discharging process.
Each functional module in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode or a software functional module mode.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A chopping brake control method of a multilevel frequency converter is characterized by comprising the following steps: the method comprises the following steps:
acquiring voltage values at two ends of each sub-bus and a full-bus voltage feedback value in the multi-level frequency converter;
calculating voltage equalization coefficients of the sub-buses according to voltage values at two ends of the sub-buses, and carrying out amplitude limiting on the voltage equalization coefficients of the sub-buses;
carrying out proportional integral adjustment calculation on the full bus voltage, and limiting the output result of the proportional integral adjustment of the full bus voltage;
the output result of the defined full bus voltage proportional integral adjustment is used as a full bus chopping modulation wave;
modifying and amplitude limiting the full bus chopping modulation wave according to the amplitude-limited voltage equalization coefficient of each sub-bus, and obtaining the chopping modulation wave of each sub-bus;
and comparing the chopped wave modulation waves of the respective sub-buses with a carrier to generate a PWM signal.
2. The multilevel converter chopping brake control method of claim 1, wherein: the method comprises the following steps of calculating voltage equalization coefficients of the respective sub-buses according to voltage values at two ends of the respective sub-buses, and carrying out amplitude limiting on the voltage equalization coefficients of the respective sub-buses, and specifically comprises the following steps:
calculating an expected equilibrium voltage value of the current working state;
calculating the balance coefficient of each sub-bus voltage;
the equalization coefficient of each sub-bus voltage is clipped so that the coefficient value is always limited to a value between plus or minus 1.
3. The multilevel converter chopping brake control method of claim 2, wherein: the calculation method of the expected equilibrium voltage value comprises the following steps: accumulating the voltage values of the sub-buses, and dividing the accumulated value by the number of the sub-buses to obtain an expected equilibrium voltage value Udcave。
4. The multilevel converter chopping brake control method of claim 2, wherein: the equalization coefficient is obtained by the following formula, wherein Udc(N) is N-1 direct current input voltage values of the N-level frequency converter, and N is the level number of the multi-level frequency converter;
5. the multilevel converter chopping brake control method of claim 1, wherein: the method comprises the following steps of calculating the proportional-integral adjustment of the full bus voltage and limiting the output result of the proportional-integral adjustment of the full bus voltage, and specifically comprises the following steps:
calculating the sum of all the voltage values of the sub-buses;
when the full bus voltage feedback value is higher than the chopping brake trigger voltage value, starting full bus voltage proportional integral regulation; the chopping brake trigger voltage value is set to be 1.1 times of the no-load full-direct-current input voltage;
carrying out proportional integral adjustment calculation on the full bus voltage;
and limiting the output result of the proportional integral adjustment of the full bus voltage.
6. The multilevel converter chopping brake control method of claim 5, wherein: the method for calculating the proportional integral adjustment of the full bus voltage comprises the following steps: comparing the expected full bus voltage value with a full bus voltage feedback value, and performing proportional-integral adjustment operation on the compared deviation;
the proportional-integral regulation control equation is as follows, wherein Kp is a proportional link coefficient, Ki is an integral link coefficient, e (t) is a difference value between an expected full voltage value and a full bus voltage feedback value, and u (t) is a calculation result of proportional-integral regulation:
the expected full bus voltage value is an expected value which is set manually according to rated parameters of the frequency converter, and the expected full bus voltage value is set as a no-load full bus voltage value.
7. The multilevel converter chopping brake control method of claim 5, wherein: the method for limiting the output result of the proportional integral adjustment of the full bus voltage comprises the following steps:
limiting the output result to zero when the output result is less than zero; when the output result is greater than the upper limit value, the output result is equal to the upper limit value; the upper limit value is the minimum value of the maximum power consumption of the chopper braking circuit in a short time and the maximum working current of the chopper circuit.
8. The multilevel converter chopping brake control method of claim 1, wherein: the method comprises the following steps of correcting and amplitude limiting the full bus chopping modulation wave according to the voltage equalization coefficient of each sub-bus for amplitude limiting, and obtaining the chopping modulation wave of each sub-bus, wherein the specific method comprises the following steps:
synthesizing the full bus chopping modulation wave and the voltage equalization coefficient of each sub-bus, and calculating the chopping modulation wave of each sub-bus; the formula for calculating the chopped wave modulation wave of each branch line is as follows:
Umn＝Uc×(1+fn)n∈(1～N-1)
wherein Uc is the calculated full bus chopping modulation wave, fn is the voltage balance coefficient of each sub-bus calculated in step S1, and UmnFor a chopped wave modulation wave of each sub-bus, N belongs to (1-N-1) N and is the level number of the multi-level frequency converter;
carrying out amplitude limiting processing on each branch line modulation wave; when the chopped wave modulation wave of each branch line is less than zero, limiting to zero; when each of the chopper-modulated waves of the denominator lines is larger than the upper limit value allowed by the chopper brake circuit, the limit is equal to the upper limit value.
9. A multi-level frequency converter chopping brake control device is characterized in that: the device comprises a chopping brake main loop unit and a chopping brake control unit,
the chopping brake main loop unit comprises a capacitor unit, a diode, an IGBT and a resistor, wherein,
the capacitor unit consists of 1 capacitor or a plurality of capacitors connected in series and in parallel;
the anode of the diode is connected with the collector of the IGBT in series and then connected with the two ends of the capacitor in parallel;
or the cathode of the diode is connected with the emitter of the IGBT in series and then connected with the two ends of the capacitor in parallel;
the diode is connected with a plurality of resistors in parallel;
the chopping brake control unit is used for controlling the controllable semiconductor device in the chopping brake main loop unit in a PWM pulse mode; when the controllable semiconductor device is switched on, the capacitor discharges the resistor through the controllable semiconductor device, and when the controllable semiconductor device is switched off, the resistor and the connecting cable follow current through the uncontrollable semiconductor device.
10. The multilevel converter chopping brake control device of claim 9, wherein: the chopping brake control unit comprises a voltage acquisition module, an equilibrium coefficient calculation module, a full bus chopping modulated wave calculation module, a bus bar chopping modulated wave calculation module and a PWM pulse generation module, wherein,
the voltage acquisition module is used for acquiring voltage values of the sub-buses;
the equalization coefficient calculation module is used for calculating the imbalance coefficient among the sub-buses and carrying out amplitude limiting on the equalization coefficient of the voltage of each sub-bus;
the full bus chopping modulation wave calculation module is used for performing proportional integral adjustment calculation on the full bus voltage and limiting the output result of the proportional integral adjustment of the full bus voltage;
the branch bus chopping modulation wave calculation module is used for correcting and amplitude limiting the output result of the limited full bus voltage proportional integral adjustment according to the amplitude-limited branch bus voltage equalization coefficient to obtain the chopping modulation wave of each branch bus;
and the PWM pulse generation module is used for comparing the chopped wave modulation wave of each sub-bus with a carrier to generate a PWM signal.
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