CN112750895A - High electron mobility transistor - Google Patents

High electron mobility transistor Download PDF

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CN112750895A
CN112750895A CN202110064654.0A CN202110064654A CN112750895A CN 112750895 A CN112750895 A CN 112750895A CN 202110064654 A CN202110064654 A CN 202110064654A CN 112750895 A CN112750895 A CN 112750895A
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layer
channel layer
electrode
barrier layer
channel
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王中旭
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Shaanxi Junpu Xinhang Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

The invention discloses a high electron mobility transistor, comprising: a substrate layer; the buffer layer is positioned on the substrate layer; the barrier layer is positioned on the buffer layer; a channel layer on the barrier layer; the source electrode, the grid electrode and the drain electrode are all positioned on the channel layer; a first passivation layer on the channel layer; a second passivation layer on the channel layer. The high electron mobility transistor is provided with an N-surface heterojunction, and the barrier layer with the N surface and the channel layer with the N surface are adopted, and the barrier layer is arranged below the 2DEG, so that a natural back barrier can be formed, the 2DEG is limited at an interface, and simultaneously, as the source electrode and the drain electrode are directly contacted with the channel layer with smaller forbidden bandwidth, ohmic contact with lower resistance and higher quality can be formed. In addition, the 2DEG of the high electron mobility transistor is closer to the grid electrode, is easier to control by the grid electrode, and has stronger device grid control capability.

Description

High electron mobility transistor
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a high-electron-mobility transistor.
Background
The device based on traditional semiconductor materials such as Si, GaAs and the like is limited by the properties of the materials, so that the device indexes such as power, breakdown voltage resistance and the like are difficult to improve. In recent years, a new generation of wide bandgap semiconductor material represented by group III nitride is developed rapidly, has the advantages of wide band gap, high saturated electron drift velocity, high critical breakdown field strength, high thermal conductivity and stable chemical properties, and has great development potential in the field of millimeter wave and submillimeter wave high-power electronic devices. The GaN material is taken as a typical representative of wide-bandgap semiconductor materials, is very suitable for preparing high-temperature, anti-radiation, high-working-frequency and high-power devices, is widely applied in the fields of aerospace, radar, communication and the like, and the research of the current GaN-based HEMT device is one of the international hotspots at present.
Generally, a heterojunction structure in a High Electron Mobility Transistor (HEMT) device of GaN is a Ga-face AlGaN/GaN structure, and due to polarization effect, a two-dimensional Electron gas (2DEG) having an extremely High area density and a High Mobility is formed at an AlGaN/GaN interface. Although the Ga-face AlGaN/GaN HEMT device has many advantages, it still has the following disadvantages: to realize the connection between the source electrode and the drain electrode and the 2DEG, the AlGaN barrier layer with larger resistance and wider forbidden band width is needed, the ohmic contact is difficult to form, and the quality is poorer.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a high electron mobility transistor. The technical problem to be solved by the invention is realized by the following technical scheme:
a high electron mobility transistor comprising:
a substrate layer;
a buffer layer on the substrate layer;
a barrier layer on the buffer layer, the barrier layer having an N-face;
a channel layer on the barrier layer, the channel layer having an N-face;
the source electrode, the drain electrode and the grid electrode are all positioned on the channel layer, the grid electrode is positioned between the source electrode and the drain electrode, ohmic contact is formed between the source electrode and the drain electrode and between the drain electrode and the channel layer, and Schottky contact is formed between the grid electrode and the channel layer;
a first passivation layer on the channel layer and also between the source and the gate;
a second passivation layer on the channel layer, the second passivation layer also being between the drain and the gate.
In an embodiment of the invention, the material of the substrate layer is any one of sapphire, SiC, Si and GaN.
In one embodiment of the present invention, the material of the buffer layer is at least one of GaN, AlN, AlGaN, and InGaN.
In one embodiment of the invention, the material of the barrier layer is N-face ScAlN, and the channel layer is N-face GaN.
In one embodiment of the invention, the barrier layer has a crystal orientation of N-face
Figure BDA0002903680210000021
The crystal orientation of the channel layer is N face
Figure BDA0002903680210000022
In one embodiment of the invention, the Sc composition in the barrier layer ranges from 0-55%.
In one embodiment of the invention, the source electrode and the drain electrode are made of Ti/Al/Ni/Au or Ti/Al/Pt/Au.
In one embodiment of the invention, the material of the grid electrode is any one of Ni/Au, Pt/Au and Pd/Au.
In one embodiment of the present invention, the material of the first passivation layer and the second passivation layer is SiN, Al2O3And AlN.
In one embodiment of the present invention, the high electron mobility transistor further comprises an insertion layer between the barrier layer and the channel layer.
The invention has the beneficial effects that:
the high electron mobility transistor is provided with an N-surface heterojunction, and the barrier layer with the N surface and the channel layer with the N surface are adopted, and the barrier layer is arranged below the 2DEG, so that a natural back barrier can be formed, the 2DEG is limited at an interface, and simultaneously, as the source electrode and the drain electrode are directly contacted with the channel layer with smaller forbidden bandwidth, ohmic contact with lower resistance and higher quality can be formed. In addition, the 2DEG of the high electron mobility transistor is closer to the grid electrode, is easier to control by the grid electrode, and has stronger device grid control capability.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another high electron mobility transistor according to an embodiment of the present invention.
Description of reference numerals:
a substrate layer-10; a buffer layer-20; a barrier layer-30; a channel layer-40; a source electrode-50; a gate-60; a drain electrode-70; a first passivation layer-80; a second passivation layer-90; insert layer-100.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention. The present embodiment provides a high electron mobility transistor including a substrate layer 10, a buffer layer 20, a barrier layer 30, a channel layer 40, a source electrode 50, a gate electrode 60, a drain electrode 70, a first passivation layer 80, a second passivation layer 90, wherein the buffer layer 20 is located on the substrate layer 10, the barrier layer 30 is located on the buffer layer 20, and the barrier layer 30 has N-faces, the channel layer 40 is positioned on the barrier layer 30, the channel layer 40 has N-faces, the source electrode 50, the gate electrode 60, and the drain electrode 70 are positioned on the channel layer 40, and the gate 60 is positioned between the source electrode 50 and the drain electrode 70, ohmic contacts are formed between the source electrode 50 and the drain electrode 70 and the channel layer 40, schottky contacts are formed between the gate and the channel layer, the first passivation layer 80 is positioned on the channel layer 40, and the first passivation layer 80 is further positioned between the source electrode 50 and the gate electrode 60, the second passivation layer 90 is positioned on the channel layer 40, and the second passivation layer 80 is further positioned between the gate electrode 60 and the drain electrode 70.
The high electron mobility transistor of the embodiment has an N-plane heterojunction, and because the barrier layer with an N-plane and the channel layer with an N-plane are adopted, and the barrier layer is below the 2DEG, a natural back barrier can be formed to limit the 2DEG at the interface, and simultaneously, because the source electrode and the drain electrode are directly contacted with the channel layer with a smaller forbidden bandwidth, ohmic contact with lower resistance and higher quality can be formed. In addition, the 2DEG of the high electron mobility transistor of the embodiment is closer to the gate, and is easier to be controlled by the gate, and the device gating capability is stronger.
Further, the material of the substrate layer 10 may be any one of sapphire, SiC, Si, and GaN.
Further, the buffer layer 20 may be made of any one of GaN, AlN, AlGaN, and InGaN, or may be made of several kinds of GaN, AlN, AlGaN, and InGaN.
Further, the barrier layer 30 is made of N-plane ScAlN, and the channel layer 40 is N-plane GaN.
At present, for the HEMT device in the prior art, because the wave function of the 2DEG is easily affected by an external electric field and moves towards the substrate direction, the 2DEG is enhanced by scattering effect, the mobility is reduced, and the device performance is deteriorated.
Firstly, as the present embodiment adopts the ScAlN as the material of the barrier layer 30, because the ScAlN not only has a higher polarization constant but also can be well matched with the GaN lattice, the present embodiment can greatly increase the 2DEG density while effectively reducing the material defects, secondly, as the N-plane GaN/ScAlN heterojunction is adopted, the barrier layer 30 is below the 2DEG, so that a natural back barrier can be formed, thereby limiting the 2DEG at the interface, and meanwhile, as the source electrode 50 and the drain electrode 70 are directly in contact with the channel layer made of the material with a smaller band gap, an ohmic contact with a lower resistance and a higher quality can be formed well. In addition, the 2DEG of the high electron mobility transistor of the present embodiment is closer to the gate 60, and is easier to be controlled by the gate 60, and the device gating capability is stronger. In addition, the barrier layer 30 of the high electron mobility transistor of the embodiment is N-plane ScAlN, and the channel layer 40 is N-plane GaN.
Further, the barrier layer 30 has an N-plane crystal orientation
Figure BDA0002903680210000051
The crystal orientation of the channel layer 40 is N-plane
Figure BDA0002903680210000052
Further, the Sc composition in the barrier layer 30 ranges from 0 to 55%.
When the Sc composition range in the barrier layer 30 is 0-55%, the barrier layer 30 made of the material of the ScAlN may have better lattice matching with the channel layer 40 made of the material of the GaN, so that defects of the device may be effectively reduced, performance degradation of the device may be avoided, reliability of the device may be improved, and the density of the 2DEG may be improved.
Preferably, the Sc composition in the barrier layer 30 is 18%, and when the material of the barrier layer 30 in the high electron mobility transistor of the present embodiment is ScAlN and the Sc composition is 18%, the lattice of the barrier layer 30 made of ScAlN may be completely matched with the lattice of the channel layer 40 made of GaN, so that the 2DEG density may be greatly increased while the material defects may be effectively reduced, and the 2DEG density may be increased by more than 3 times when the Sc composition is 18%.
Further, the source electrode and the drain electrode are made of Ti/Al/Ni/Au or Ti/Al/Pt/Au, the Ti/Al/Ni/Au represents that the first layer is Ti, the second layer is Al, the third layer is Ni and the fourth layer is Au from bottom to top, and the Ti/Al/Pt/Au represents that the first layer is Ti, the second layer is Al, the third layer is Pt and the fourth layer is Au from bottom to top.
Preferably, the thickness of Ti/Al/Ni/Au is 22/140/55/45nm, i.e. the first layer of material Ti is 22nm, the second layer of material Al is 140nm, the third layer of material Ni is 55nm and the fourth layer of material Au is 45 nm.
Preferably, the thickness of Ti/Al/Pt/Au is 22/140/55/45nm, i.e. the first layer of material Ti is 22nm, the second layer of material Al is 140nm, the third layer of material Pt is 55nm and the fourth layer of material Au is 45 nm.
The source electrode 50 and the drain electrode 70 of the present embodiment are located on the channel layer 40 made of GaN, so that the source electrode 50 and the drain electrode 70 can be directly contacted with the channel layer made of GaN with smaller forbidden band width, and thus ohmic contact with lower resistance and higher quality can be formed.
Further, the gate 60 is made of any one of Ni/Au, Pt/Au, and Pd/Au, where Ni/Au represents that the first layer is Ni and the second layer is Au from bottom to top, Pt/Au represents that the first layer is Pt and the second layer is Au from bottom to top, and Pd/Au represents that the first layer is Pd and the second layer is Au from bottom to top.
Further, the thickness of the gate 60 is in the range of 120-300 nm.
The gate electrode 60 of the high electron mobility transistor of the present embodiment is located on the channel layer 40 made of GaN, so that the 2DEG of the high electron mobility transistor of the present embodiment is closer to the gate electrode 60, and thus the 2DEG is more easily controlled by the gate electrode 60, and the device gating capability is stronger.
Further, the first passivation layer 80 and the second passivation layer 90 are made of SiN or Al2O3And AlN.
Preferably, the first passivation layer 80 and the second passivation layer 90 have a thickness in the range of 50-100 nm.
In an embodiment, referring to fig. 2, fig. 2 is a schematic structural diagram of another high electron mobility transistor according to an embodiment of the present invention, and the high electron mobility transistor of the embodiment may further include an insertion layer 100, where the insertion layer 100 is located between the barrier layer 30 and the channel layer 40. The present embodiment can effectively improve the carrier mobility by adding an insertion layer 100 between the barrier layer 30 and the channel layer 40.
Further, the material of the insertion layer 100 may be any one of AlN, InAlN, and AlGaN, and the insertion layer 100 may be another material, which is not particularly limited in this embodiment.
Firstly, as the ScAlN is adopted as the material of the barrier layer 30 in the embodiment, the ScAlN not only has higher polarization constant, but also can be completely matched with the GaN crystal lattice, so that the 2DEG density can be greatly improved while the material defect is effectively reduced, secondly, as the N-face GaN/ScAlN heterojunction is adopted, the barrier layer 30 is arranged below the 2DEG, so that a natural back barrier can be formed, the 2DEG is limited at an interface, and simultaneously, as the source electrode 50 and the drain electrode 70 are directly contacted with the GaN channel layer made of the material with smaller bandwidth, the ohmic contact with lower resistance and higher quality can be better formed. In addition, the 2DEG of the high electron mobility transistor of the present embodiment is closer to the gate 60, and is easier to be controlled by the gate 60, and the device gating capability is stronger. In addition, the barrier layer 30 of the high electron mobility transistor of the embodiment is N-plane ScAlN, and the channel layer 40 is N-plane GaN.
When the Sc composition range in the barrier layer 30 of this embodiment is 0 to 55%, the barrier layer 30 made of ScAlN may have better lattice matching with the channel layer 40 made of GaN, so that the defects of the device may be effectively reduced, the performance degradation of the device may be avoided, the reliability of the device may be improved, and the density of the 2DEG may be improved. Particularly, when the Sc composition in the barrier layer 30 is 18%, the barrier layer 30 made of the material of the ScAlN may be completely matched with the lattice of the channel layer 40 made of the material of the GaN, so that not only may material defects be effectively reduced, but also the 2DEG density may be increased by more than 3 times.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic data point described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A high electron mobility transistor, comprising:
a substrate layer;
a buffer layer on the substrate layer;
a barrier layer on the buffer layer, the barrier layer having an N-face;
a channel layer on the barrier layer, the channel layer having an N-face;
the source electrode, the drain electrode and the grid electrode are all positioned on the channel layer, the grid electrode is positioned between the source electrode and the drain electrode, ohmic contact is formed between the source electrode and the drain electrode and between the drain electrode and the channel layer, and Schottky contact is formed between the grid electrode and the channel layer;
a first passivation layer on the channel layer and also between the source and the gate;
a second passivation layer on the channel layer, the second passivation layer also being between the drain and the gate.
2. The hemt of claim 1, wherein said substrate layer is made of any one of sapphire, SiC, Si and GaN.
3. The hemt of claim 1, wherein said buffer layer is made of at least one of GaN, AlN, AlGaN and InGaN.
4. The hemt of claim 1, wherein said barrier layer is N-plane ScAlN and said channel layer is N-plane GaN.
5. The HEMT of claim 4, wherein the barrier layer has an N-plane crystal orientation
Figure FDA0002903680200000011
The crystal orientation of the channel layer is N face
Figure FDA0002903680200000012
6. The hemt of claim 4, wherein said Sc composition in said barrier layer is in the range of 0-55%.
7. The hemt of claim 1, wherein said source and drain are each made of Ti/Al/Ni/Au or Ti/Al/Pt/Au.
8. The hemt of claim 1, wherein said gate is made of any one of Ni/Au, Pt/Au, Pd/Au.
9. The hemt of claim 1, wherein said first and second passivation layers are of SiN, Al2O3And AlN.
10. The hemt of claim 1, further comprising an intervening layer between said barrier layer and channel layer.
CN202110064654.0A 2021-01-18 2021-01-18 High electron mobility transistor Pending CN112750895A (en)

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