CN112750759A

CN112750759A - Method for forming interconnection structure

Info

Publication number: CN112750759A
Application number: CN202011169913.8A
Authority: CN
Inventors: 黄麟淯; 游力蓁; 张家豪; 庄正吉; 林佑明; 王志豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-10-31
Filing date: 2020-10-28
Publication date: 2021-05-04

Abstract

The present disclosure provides a method of forming an interconnect structure. The method can include forming a first insulating material layer on a substrate, forming a recessed via in the first insulating material layer, filling the recessed via with a conductive material layer, selectively forming a second insulating material layer over the first insulating material layer, and opening the second insulating material layer to the conductive material layer while forming the second insulating material layer.

Description

Method for forming interconnection structure

Technical Field

Embodiments of the present invention relate generally to a method of forming an interconnect structure, and more particularly to a method of forming an interconnect structure of a semiconductor device to enhance isolation between the interconnect structure and underlying transistor structures and to improve the performance of the resulting device.

Background

As semiconductor technology has developed, there has been an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower cost. In order to meet these aforementioned needs, the semiconductor industry continues to scale down the size of semiconductor devices, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finfets), and nano-layer sheet field effect transistors (nffets). This scaling down process also increases the complexity of the manufacturing process for the semiconductor device.

Disclosure of Invention

Some embodiments of the present invention provide a method of forming an interconnect structure. The method may include forming a first layer of insulating material on a substrate and forming a via recess (via access) in the first layer of insulating material. The method further includes filling the recessed via with a layer of conductive material. The method further includes selectively forming a second insulating material layer over the first insulating material layer and opening the second insulating material layer to the conductive material layer.

Some embodiments of the present invention further provide a method for forming an interconnect structure. The method includes forming a fin structure (fin structure) on a substrate and forming a layer of conductive material over the fin structure. The method further includes forming a first insulating material layer over the fin structure, the first insulating material layer contacting the conductive material layer. The method further includes forming a second layer of insulating material over the first layer of insulating material. In some embodiments, a via access (via access) is formed in the second insulating material layer when the second insulating material layer is formed.

Some embodiments of the present invention provide an interconnect structure. The interconnect structure may include a substrate and a first layer of insulating material over the substrate. The interconnect structure further includes a first layer of conductive material within the first layer of insulating material. The interconnect structure further includes a second layer of insulating material over the first layer of insulating material. In some embodiments, the second insulating material layer may include a top surface, a sidewall, and a shoulder structure. In some embodiments, the shoulder structure may connect the sidewall to the top surface, and the shoulder structure may be sloped from the sidewall to the top surface. The interconnect structure may further include a second conductive material layer formed in the second insulating material layer and surrounded by the sidewalls of the second insulating material layer.

Drawings

The embodiments of the invention will be more fully understood from the detailed description given below and the accompanying drawings. It is emphasized that, in accordance with industry standard practice, many of the components (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A illustrates an isometric view of a semiconductor device according to some embodiments.

Fig. 1B, 1C, 1D, 1E, 1F illustrate cross-sectional views of the semiconductor device of fig. 1A, according to some embodiments.

Fig. 2 is a flow diagram of an example method for fabricating a semiconductor device according to some embodiments.

Fig. 3A illustrates an isometric view of various stages in the manufacture of a semiconductor device according to some embodiments.

Fig. 3B, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7, 8, and 9 illustrate cross-sectional views of various stages of fabrication to form a semiconductor device, in accordance with some embodiments.

Description of reference numerals:

100. 300, 400, 500, 600, 700, 800: semiconductor device with a plurality of semiconductor chips

102: field effect transistor

106: substrate

108: fin structure

108A: fin base portion

108B: stacked fin portion

110: source/drain region

112: grid structure

112A: oxide layer

112B: gate dielectric layer

112C: grid electrode

114: gate spacer

114s, 126s, 128 s: dielectric top surface

118: interlayer dielectric layer

122: channel layer

124: source/drain contact

126: source/drain pad layer

128: gate liner layer

130. 162: trench conductor layer

130 s: metal top surface

130A, 146A: backing layer

130A₁: lower lining layer

130A₂: upper lining layer

130B, 146B: metal layer

130B₁: lower metal layer

130B₂: upper metal layer

131: region(s)

138: shallow trench isolation region

140: interconnect structure

140₁: first interconnection layer

140₂: second interconnect layer

141: bottom surface

142. 148: layer of insulating material

143: side wall

144: back end connection lamination

144A: first back end of line etch stop layer

144B: second back end of line etch stop layer

144C: back end of line interlevel dielectric layer

145: top surface

147. 647: footing structure

146. 164: layer of conductive material

151. 153, 155, 157: end part

152: upper shoulder structure

154: lower shoulder structure

172: internal spacer

601. 701, a step of: through hole

602: suppression material layer

H₁₄₂: thickness of

W₁₃₀、W₆₀₁: horizontal dimension

W₁₅₂、W₁₅₄: horizontal displacement

H₁₅₂、H₁₅₄: vertical displacement

EXT₁₅₅: horizontally extend

B-B: section line segment

X, Y, Z: direction of rotation

200: method of producing a composite material

205. 210, 215, 220: step (ii) of

Detailed Description

It should be noted that references in the specification to "one embodiment", "an example embodiment", etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings herein.

Also, spatially relative terms, such as "below" … …, "below," "lower," "above," "higher," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

The fins associated with fin field effect transistors (finFETs) or gate-all-around (GAA) field effect transistors may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes to form patterns with a pitch (pitch) that is less than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fins are patterned with the remaining spacers.

The term "nominal" as used herein, means a desired value or target value of a feature or parameter of a component or process step set during the design phase of a product or process, and a range of values above and/or below this desired value. This range of values is typically a small variation caused by manufacturing processes or tolerance tolerances.

In some embodiments, the terms "about" (about) and "substantially" (substantally) may refer to a numerical value of a given quantity that is within ± 5% of a target value (e.g., ± 1%, ± 2%, ± 3%, ± 4%, ± 5% of the target value).

As used herein, the term "vertical" refers to a plane that is generally perpendicular to a surface of a substrate.

As used herein, the term "insulating layer" refers to a layer (e.g., a dielectric layer) that functions as an electrical insulator.

As used herein, the term "selectivity" refers to the ratio of the etch rates of two materials under the same etch conditions.

As used herein, the term "high-k" (high-k) refers to a high dielectric constant. In the field of semiconductor device structures and processes, high dielectric constant refers to higher than silicon dioxide (SiO)₂) A dielectric constant (e.g., greater than 3.9).

Technological advances in the semiconductor industry have driven the pursuit of Integrated Circuits (ICs) with higher device density, higher performance, and lower cost. In the course of IC development, both transistor structures and interconnect structures have been scaled down to achieve ICs with higher device densities. Such scaling may correspondingly reduce the spacing between the interconnect structure and the transistor contacts. Furthermore, due to variations in the manufacturing process, such as unintentional over-grinding during the chip planarization process, the spacing between the interconnect structure and the transistor contacts may be additionally reduced. However, such reduced spacing reduces IC manufacturing tolerances and is therefore susceptible to process variations in the IC manufacturing process. For example, during the fabrication of an IC, one or more grinding steps may substantially thin the dielectric layer between the metal lines of the interconnect structure and the underlying transistor structure. This can cause leakage in the transistor structure, such as time-dependent dielectric breakdown (TDDB), which reduces IC yield and reliability.

The present disclosure relates to a method of manufacturing and an isolation structure that enhances electrical isolation between an interconnect structure within an integrated circuit and a transistor structure below the interconnect structure. For example, the isolation structure may include an insulating layer formed between the interconnect structure and the underlying transistor structure. The insulating layer may be selectively deposited over a first portion of the top surface of the transistor structure while exposing a second portion of the top surface of the transistor structure. In some embodiments, the first portion of the top surface may be a dielectric surface (dielectric surface) and the second portion of the top surface may be a metal surface (dielectric surface) electrically connected to the interconnect structure. In some embodiments, the insulating layer may be selectively deposited over a first set of transistor metal contacts while maintaining a second set of transistor metal contacts open to the interconnect structure. One benefit of the present disclosure is that the insulating layer is utilized to effectively increase the isolation between the interconnect structure and the underlying transistor structure, thereby enhancing the electrical isolation between the aforementioned structures and preventing electrical leakage failure (electrical leakage failure) in the integrated circuit.

Referring to fig. 1A to 1F, according to some embodiments, a semiconductor device 100 has a plurality of Field Effect Transistors (FETs) 102 and an interconnect structure 140 disposed over the FETs 102. Fig. 1A illustrates an isometric view of a semiconductor device 100 according to some embodiments. Fig. 1B and 1F each illustrate a cross-sectional view along line B-B of the semiconductor device 100 of fig. 1A, in which each field effect transistor 102 may be a fin field effect transistor (finFET), according to some embodiments. Fig. 1C illustrates a cross-sectional view along line B-B of the semiconductor device 100 of fig. 1A, wherein each field effect transistor 102 may be a gate-all-around field effect transistor (GAA FET), according to some embodiments. Fig. 1D and 1E illustrate cross-sectional views along line B-B of the semiconductor device 100 of fig. 1A, according to some embodiments. The semiconductor device 100 may be provided in a microprocessor, a memory unit, or other integrated circuit. Elements in fig. 1A-1F having the same reference number designation may be used for discussion and description of each other unless otherwise indicated.

Referring to fig. 1A, each Field Effect Transistor (FET)102 may include a fin structure 108 extending along an X-axis, a gate structure 112 disposed over the fin structure 108 along a Y-axis, and a source/drain (S/D) region 110 over portions of the fin structure 108. Although fig. 1A illustrates a corresponding arrangement of two Field Effect Transistors (FETs) 102 in the fin structure 108, any number of FETs 102 may be arranged along the fin structure 108. Each Field Effect Transistor (FET)102 may be formed on a substrate 106. The substrate 106 may be a semiconductor material such as, but not limited to, silicon. In some embodiments, the substrate 106 may comprise a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 106 may include (i) an elemental semiconductor (e.g., silicon or germanium); (ii) a compound Semiconductor (SiC) including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); (iii) an alloy semiconductor (alloy semiconductor) including silicon germanium carbon (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), gallium indium phosphide (InGaP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and/or aluminum gallium arsenide (AlGaAs); or (iv) a combination of the foregoing. In addition, the substrate 106 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 106 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

The semiconductor device 100 may further include Shallow Trench Isolation (STI) regions 138, the shallow trench isolation regions 138 configured to provide electrical isolation for the fin structure 108. For example, the shallow trench isolation region 138 may electrically isolate the fin structure 108 from another fin structure 108 in the semiconductor device 100 (not shown in fig. 1A). As shown in fig. 1A, the shallow trench isolation regions 138 may be configured to provide electrical isolation between the field effect transistors 102 located on the fin structures 108. Furthermore, the shallow trench isolation regions 138 may be configured to provide electrical isolation between the field effect transistors 102, as well as electrical isolation between adjacent active and passive components (not shown in fig. 1A) integrated into the substrate 106 or deposited on the substrate 106. The shallow trench isolation region 138 may include one or more layers of dielectric material, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride. In some embodiments, the insulating layer may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorinated-silicate glass (FSG), low-k dielectric material, and/or other suitable insulating materials.

Referring to fig. 1A-1C, the fin structure 108 may include a fin base portion (fin base portion)108A and a stacked fin portion (stacked fin portion)108B disposed on the fin base portion 108A. The fin base portion 108A may comprise a material similar to the substrate 106, such as a material having a lattice constant (e.g., lattice mismatch within 5%) substantially close to the substrate 106. In some embodiments, the fin base portion 108A may comprise the same material as the substrate 106. For example, the fin base portion 108A may be formed by photolithographically patterning and etching the substrate 106. The stacked fin portion 108B may include a semiconductor layer that is a channel layer 122 of the field effect transistor 102 and source/drain (S/D) regions 110 that are in horizontal (e.g., in the X-direction) contact with the channel layer 122. In some embodiments, as shown in fig. 1B, the channel layer 122 may be connected to the fin base portion 108A and/or the substrate 106. In fig. 1C, the stacked fin portion 108B may include a plurality of channel layers 122, each channel layer 122 may be made of the same or different materials.

Source/drain (S/D) regions 110 may be grown on the fin base portion 108A. Each channel layer 122 of the field effect transistor 102 may be disposed between a pair of source/drain (S/D) regions 110. The source/drain (S/D) regions 110 may comprise epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material may be the same material as the substrate 106 material. For example, the epitaxially grown semiconductor material may have a lattice constant substantially close (e.g., within 5% lattice mismatch). In some embodiments, the epitaxially grown semiconductor material may include: (i) a semiconductor material such as germanium (Ge) or silicon (Si); (ii) a compound semiconductor material such as gallium arsenide (GaAs) and/or aluminum gallium arsenide (AlGaAs); or (iii) a semiconductor alloy, such as silicon germanium (SiGe) and/or gallium arsenide phosphide (GaAsP). The source/drain (S/D) regions 110 may be doped with a p-type dopant or doped with an n-type dopant. The p-type dopant may include boron (B), indium (In), aluminum (Al), or gallium (Ga). The n-type dopant may include phosphorus (P) or arsenic (As). In some embodiments, the source/drain (S/D) regions 110 may have a plurality of sub-regions (not shown) that may include silicon germanium (SiGe) and may differ from one another based on, for example, doping concentration, epitaxial growth process conditions, and/or the relative concentration of germanium with respect to silicon. For example, the atomic percentage of germanium (atomic percentage) in a sub-region closest to the stacked fin portion 108B may be less than the atomic percentage of germanium in a sub-region furthest from the stacked fin portion 108B.

The channel layer 122 may comprise a semiconductor material similar to the substrate 106. For example, the channel layer 122 may include a semiconductor material having a lattice constant substantially close to the substrate 106 (e.g., within 5% of lattice mismatch). In some embodiments, channel layer 122 may comprise silicon or silicon germanium (SiGe). In some embodiments, channel layer 122 may comprise silicon germanium (SiGe) having a germanium concentration of about 25 atomic percent (atomic percent) to about 50 atomic percent, while any remaining atomic percent is silicon, or may comprise silicon without any substantial germanium content. In some embodiments, the channel layer 122 and the substrate 106 may include semiconductor materials having different oxidation rates and/or etch selectivities from each other. Channel layer 122 may be undoped, doped with a p-type dopant, or doped with an n-type dopant. The p-type dopant may include boron (B), indium (In), aluminum (Al), or gallium (Ga). The n-type dopant may include phosphorus (P) or arsenic (As).

The gate structure 112 may be a multi-layer structure that surrounds a portion of one or more of the fin structures 108. For example, the gate structure 112 may surround the channel layer 122 (e.g., the semiconductor layer 122) of the field effect transistor 102 to adjust the conductivity of the channel layer 122 of the field effect transistor 102. In some embodiments, the gate structure 112 may be referred to as a gate-all-around (GAA) structure, wherein the field effect transistor 102 may be referred to as a gate-all-around field effect transistor (GAA FET) 102. The gate structure 112 may include an oxide layer 112A, a gate dielectric layer 112B disposed on the oxide layer 112A, a gate electrode 112C disposed on the gate dielectric layer 112B, and gate spacers 114 disposed on sidewalls of the gate electrode 112C. The oxide layer 112A and the gate dielectric layer 112B may be surrounded by respective channel layers 122, thereby electrically isolating the channel layers 122 from each other and from the gate electrode 112C. An oxide layer 112A and a gate dielectric layer 112B may be disposed between the gate electrode 112C and the source/drain (S/D) region 110 to avoid electrical shorts therebetween.

The oxide layer 112A may be an interfacial dielectric layer (interfacial dielectric) disposed between each of the channel layers 122 and the gate dielectric layer 112B. In some embodiments, oxide layer 112A may comprise a semiconductor oxide material (e.g., silicon oxide or silicon germanium oxide) and may have a thickness in the range of about 1nm to about 10 nm.

The gate dielectric layer 112B may include silicon oxide, and may be formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), e-beam evaporation, or other suitable processes. In some embodiments, the gate dielectric layer 112B may include: (i) oxidation of carbon monoxideA layer of silicon, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (HfO)₂) Titanium oxide (TiO)₂) Hafnium zirconium oxide (HfZrO), tantalum oxide (Ta)₂O₃) Hafnium silicate (HfSiO)₄) Zirconium oxide (ZrO)₂) Zirconium silicate (ZrSiO)₂) (iii) a high-k dielectric material having the following oxides: lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu), or (iv) a combination of the foregoing. The high dielectric constant dielectric layer may be formed by ALD and/or other suitable methods. In some embodiments, each gate dielectric layer 112B may comprise a single layer of insulating material or a stack of layers of insulating material. The gate dielectric layer 112B may have a thickness in the range of about 1nm to about 5 nm. Other materials and methods of formation for forming the gate dielectric layer 112B are within the scope and spirit of the embodiments of the present disclosure.

In some embodiments, each gate electrode 112C may be a terminal (terminal) of a field effect transistor. The gate electrode 112C may include a metal stack surrounding each of the channel layers 122. Depending on the space between adjacent channel layers 122 and the thickness of the layers of the gate structure 112, each channel layer 122 may be surrounded by one or more layers of gate electrodes 112C that fill the space between adjacent channel layers 122. In some embodiments, each gate electrode 112C may include a gate barrier layer (not shown in fig. 1A and 1B), a gate work function layer (not shown in fig. 1A and 1B), and a gate metal fill layer (not shown in fig. 1A and 1B). In some embodiments, the gate barrier layer may be used as a nucleation layer (nucleation layer) for the subsequent formation of the gate work function layer. The gate barrier layer may further help prevent metal (e.g., Al) from substantially diffusing from the gate work function layer to underlying material layers (e.g., gate dielectric layer 112B or oxide layer 112A). Each gate barrier layer may comprise titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other suitable diffusion barrier material. In some embodiments, the gate work function layer may comprise a single metal layer or a stack of multiple metal layers. The metal layer stack may include metals having work function values that are the same as or different from each other. In some embodiments, each gate work function layer may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), aluminum titanium (TiAl), aluminum titanium nitride (TiAlN), tungsten nitride (WN), metal alloys, and/or combinations thereof. In some embodiments, each gate work function layer may comprise an aluminum (Al) -doped metal, such as aluminum (Al) -doped titanium, aluminum (Al) -doped titanium nitride (TiN), aluminum (Al) -doped tantalum (Ta), or aluminum (Al) -doped tantalum nitride (TaN). Each gate metal fill layer may comprise a single metal layer or a stack of metal layers. The stack of metal layers may comprise different metals from each other. In some embodiments, each gate metal fill layer may comprise a suitable conductive material, such as titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), Zr, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys, and/or combinations of the foregoing. Other materials and methods of formation for the gate barrier layer, the gate work function layer, and the gate metal fill layer are within the scope and spirit of the embodiments of the present disclosure.

The gate structure 112 may further include a gate spacer 114, and the gate spacer 114 is in physical contact with the oxide layer 112A and the gate dielectric layer 112B. The gate spacer 114 may be a low-k material having a dielectric constant less than about 3.9. For example, the gate spacers 114 may comprise an insulating material, such as silicon oxide, silicon nitride, a low dielectric constant material, or a combination thereof. In some embodiments, the gate spacers 114 may have a thickness ranging from about 2nm to about 10 nm. Other materials and thicknesses for the gate spacers are also within the scope and spirit of the embodiments of the present disclosure.

In some embodiments, as shown in fig. 1C, the gate structure 112 may further include an inner spacer 172 disposed between the gate structure 112 and the source/drain (S/D) region 110. For example, in accordance with some embodiments, the inner spacers 172 may be in contact with the gate dielectric layer 112B and/or the oxide layer 112A. In some embodiments, the internal spacers 172 may be disposed between vertically (in the Z direction) adjacent channel layers 122. The internal spacers 172 may have a low dielectric constant material with a dielectric constant less than about 3.9. For example, the inner spacers 172 may comprise an insulating material, such as silicon oxide, silicon nitride, a low dielectric constant material, or a combination of the foregoing. In some embodiments, the thickness of the internal spacers 172 may be in the range of about 2nm to about 10 nm. Other materials and thicknesses for the interior spacer 172 are within the spirit and scope of the present disclosure.

Source/drain (S/D) contacts 124 may be formed over the source/drain (S/D) regions 110 to electrically connect the underlying source/drain (S/D) regions 110 to other elements of the integrated circuit (not shown in fig. 1A and 1B). The source/drain (S/D) contacts 124 may include a silicide layer and a conductive region (not shown in fig. 1A and 1B) over the silicide layer. The silicide layer may comprise a metal silicide and may provide a low resistance interface between the conductive region and the underlying source/drain (S/D) region 110. Examples of the metal used to form the metal silicide may be cobalt (Co), titanium (Ti), and nickel (Ni). The conductive region may include a conductive material such as tungsten (W), aluminum (Al), and cobalt (Co). The conductive region may have an average horizontal dimension (e.g., width in the X direction) in a range of about 15nm to about 25nm, and may have an average vertical dimension (e.g., height in the Z direction) in a range of about 400nm to about 600 nm. In some embodiments, at least one conductive liner layer (not shown) may be disposed between the silicide layer and the conductive region. The conductive liner may be configured as a diffusion barrier and may comprise a single layer of conductive material or a stack of multiple layers of conductive materials, such as TiN, Ti, Ni, TaN, Ta, or a combination of the foregoing. In some embodiments, the conductive liner may be used as an adhesion-promoting layer (adhesion-promoting layer), a glue layer, a primer layer, a protective layer, and/or a nucleation layer. According to some embodiments, the conductive liner may have a thickness in a range of about 1nm to about 2 nm. Based on the disclosure herein, other materials and dimensions for the conductive liner, silicide layer, and conductive region are within the spirit and scope of the present disclosure.

Referring to fig. 1A and 1B, each field effect transistor 102 may further include a source/drain (S/D) liner layer (padding layer)126, a gate padding layer (gate padding layer)128, and an interlayer dielectric (ILD) layer 118. Source/drain (S/D) liner layers 126 may be disposed over the source/drain (S/D) contacts 124, respectively, to provide electrical insulation between the source/drain (S/D) contacts 126 and the interconnect structure 140. Similarly, a gate liner layer 128 may be disposed on the gate structure 112 to provide electrical insulation between the gate structure 112 and the interconnect structure 140. The source/drain (S/D) liner layer 126 and the gate liner layer 128 may be formed using any suitable insulating material. By way of example and not limitation, source/drain (S/D) liner layer 126 and gate liner layer 128 may be formed from silicon carbide (silicon carbide), lanthanum oxide (lanthanum oxide), aluminum oxide (aluminum oxide), aluminum oxynitride (aluminum oxide), zirconium oxide (zirconium oxide), hafnium oxide (hafnium oxide), silicon nitride (silicon nitride), silicon, zinc oxide (zinc oxide), zirconium nitride (zirconium nitride), zirconium aluminum oxide (zirconium oxide), titanium oxide (titanium oxide), tantalum oxide (tantalum oxide), yttrium oxide (yttrium oxide), tantalum nitride (tantalum carbide), zirconium oxide (zirconium carbide), silicon carbide (silicon carbide), silicon carbide (silicon carbide), silicon carbide (silicon carbide), hafnium carbide (silicon carbide), or combinations thereof.

An interlayer dielectric layer 118 may be disposed over the fin structure 108 to provide electrical insulation between the fin structure 108 and the interconnect structure 140. In some embodiments, the interlayer dielectric layer 118 may further encapsulate a source/drain (S/D) liner layer 126, a gate liner layer 128, and source/drain (S/D) contacts 124. The interlayer dielectric layer 118 may comprise a dielectric material deposited using a deposition process suitable for flowable dielectric materials, such as flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide. For example, flowable silicon oxide can be deposited using Flow Chemical Vapor Deposition (FCVD). In some embodiments, the dielectric material may be silicon oxide. In some embodiments, the interlayer dielectric layer 118 may further include an etch stop liner (not shown in fig. 1A and 1B) adjacent to the gate structure 112 and/or the source/drain (S/D) region 110. By way of example and not limitation, the etch stop liner may comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron carbonitride, or combinations of the foregoing. In some embodiments, the interlayer dielectric layer 118 may have a thickness of about 50nm to about 200 nm. Other materials, thicknesses, and methods of formation for the interlayer dielectric layer 118 are within the spirit and scope of the present disclosure.

In some embodiments, the field effect transistor 102 may further include a trench conductor layer 130 formed over the source/drain (S/D) contacts 124 and/or the gate structure 112. For example, as shown in fig. 1B, the trench conductor layer 130 may be embedded in a source/drain (S/D) pad layer 126 and in contact with an underlying source/drain (S/D) contact 124. Thus, the trench conductor layer 130 may electrically bridge the interconnect structure 140 and the underlying source/drain (S/D) contacts 124. In some embodiments, the trench conductor layer 130 may be embedded in the gate liner layer 128 and in contact with the gate electrode 112C, wherein the trench conductor layer 130 may electrically bridge the interconnect structure 140 and the underlying gate electrode 112C (this embodiment is not shown in fig. 1A and 1B). The trench conductor layer 130 may be made of any suitable conductive material, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), molybdenum (Mo), a silicide material, and a conductive nitride material. The trench conductor layer 130 may have an average horizontal dimension (e.g., width in the X direction) and an average vertical dimension (e.g., height in the Z direction) based on the pitch size of the field effect transistor 102. For example, the trench conductor layer 130 may have an average horizontal dimension (e.g., width in the X direction) in a range of about 15nm to about 25nm, and may have an average vertical dimension (e.g., height in the Z direction) in a range of about 400nm to about 600 nm. Other materials and other dimensions of the trench conductor layer 130 are also within the spirit and scope of the present disclosure based on the disclosure herein.

The interconnect structure 140 may include a plurality of interconnect layers disposed over the field effect transistor 102. For example, referring to fig. 1B, the interconnect structure 140 may include a first interconnect layer 140 disposed over the field effect transistor 102 and in contact with the field effect transistor 102₁And is disposed on the first interconnect layer 140₁Over and with the first interconnect layer 140₁A second interconnect layer 140 in contact with₂. First interconnect layer 140₁A layer of insulating material 142 may be included, which is selectively disposed on the top dielectric surface of the field effect transistor 102 and selectively opened to the underlying top metal surface (metal top surfaces) of the field effect transistor 102. For example, as shown in fig. 1B, a layer of insulating material 142 may be selectively disposed on the source/drain (S/D) liner layer 126 and the gate liner layer 128 while having vias (via) to the underlying trench conductor layer 130 of the field effect transistor 102. In some embodiments, a layer of insulating material 142 may also be selectively disposed over the gate spacers 114 and have vias (via) to the underlying trench conductor layer 130 of the field effect transistor 102, while the gate spacers 114, source/drain (S/D) liner layer 126, and gate liner layer 128 may be coplanar with one another (this embodiment is not shown in fig. 1A-1D). First interconnect layer 140₁A layer of conductive material 146 disposed over the layer of insulating material 142 may also be included. Since the insulating material layer 142 may be selectively disposed over the source/drain (S/D) pad layer 126, the conductive material layer 146 may be further isolated from portions of the source/drain (S/D) contact 124 that are buried under the source/drain (S/D) pad layer 126 by the insulating material layer 142. In a similar manner, the first and second substrates are,the layer of conductive material 146 may be further isolated from portions of the gate electrode 112C that are buried under the gate liner layer 128 by the layer of insulating material 142. By further separating the conductive material layer 146 from the underlying source/drain (S/D) contacts 124 and/or gate electrode 112C, the insulating material layer 142 may reduce time dependent dielectric breakdown failure (TDDB failure) between the interconnect structure 140 and the field effect transistor 102. In some embodiments, the thickness H of the insulating material layer 142₁₄₂And may range from about 0.5nm to about 50 nm. According to some embodiments, the thickness H₁₄₂Insulating material layer 142 of less than about 0.5nm may not provide sufficient enhancement of dielectric breakdown voltage. Conversely, according to some embodiments, the thickness H₁₄₂Insulating material layer 142 greater than about 50nm may cause a problem with gap fill material (e.g., conductive material layer 146) being poorly filled into vias (e.g., via 601; as discussed below) through insulating material layer 142. In some embodiments, thickness H₁₄₂The horizontal (e.g., in the X direction) dimension W of the trench conductor layer 130₁₃₀May be less than about 50, less than about 20, less than about 15, less than about 10, or less than about 5. According to some embodiments, aspect ratios above the above threshold may result in poor gap fill when a gap fill material (e.g., a layer of conductive material 146) is filled into a via (e.g., via 601) through the layer of insulating material 142. Thickness H₁₄₂Are also within the spirit and scope of the present disclosure. In some embodiments, the layer of conductive material 146 may be formed through vias in the layer of insulating material 142 and in contact with the trench conductor layer 130. For example, fig. 1B shows the insulating material layer 142, and the insulating material layer 142 has a via that can communicate to the underlying trench conductor layer 130, wherein the conductive material layer 146 can contact the trench conductor layer 130 through the via of the insulating material 142. In some embodiments, the first interconnect layer 140₁A back end of line (BEOL) stack 144 may also be included and configured to couple the layer of conductive material 146 with the first interconnect layer 140₁Is electrically isolated from the other conductive material layer 146 (not shown in fig. 1B). Example (b)For example, a back end of line (BEOL) stack 144 may be laterally adjacent to the conductive material layer 146 and disposed over a portion of the insulating material layer 142. In some embodiments, the back end of line (BEOL) stack 144 may be coplanar with the layer of conductive material 146. In some embodiments, the back-end-of-line (BEOL) stack 144 may include a first back-end-of-line etch stop layer (first BEOL ESL)144A, a second back-end-of-line etch stop layer 144B, and a back-end-of-line interlayer dielectric (BEOL ILD) layer 144C, wherein the first back-end-of-line etch stop layer 144A, the second back-end-of-line etch stop layer 144B, and the back-end-of-line interlayer dielectric layer 144C may have different etch selectivities from each other. In some embodiments, each of the back end of line etch stop layer 144A, the back end of line etch stop layer 144B, and the back end of line interlayer dielectric (ILD) layer 144C may be in a range from about 1nm to about 30 nm. Other thicknesses of the back-end-of-line etch stop layer 144A, the back-end-of-line etch stop layer 144B, and the back-end-of-line interlayer dielectric layer 144C are within the spirit and scope of the present disclosure. Second interconnect layer 140₂May include a conductive material layer 164 and a first interconnection layer 140 disposed between the conductive material layer 164 and the first interconnection layer 140₁With a layer of insulating material 148 in between. For example, the insulating material layer 148 may be disposed over the conductive material layer 146 to separate the conductive material layer 164 from the conductive material layer 146. In some embodiments, a layer of conductive material 164 may also be disposed on the first interconnect layer 140₁Above a back-end-of-line (BEOL) stack 144. Second interconnect layer 140₂A trench conductor layer 162 may also be included that is formed through the layer of insulating material 148. The trench conductor layer 162 may be configured to electrically connect the first interconnect layer 140₁And a second interconnect layer 140₂. For example, the trench conductor layer 162 may contact and electrically bridge two interconnect layers of the conductive material layer 164 and the conductive material 146 layer. In some embodiments, the sidewalls of the trench conductor layer 162 may be sloped to the substrate 106.

In some embodiments, the interconnect structure 140 may further include a second interconnect layer 140 disposed on the second interconnect layer 140₂One or more overlying interconnect layers (not shown in FIG. 1B), wherein each of the one or more interconnect layers may have an interconnect layer with the second interconnect layer 140₂Identical or substantially similar structures. For example, each of the one or more interconnect layers may include a conductive material layer 164, an insulating material layer 148 disposed below the conductive material layer 164, and a trench conductor layer 162 formed within the insulating material layer 148, with the trench conductor layer 162 being configured to electrically bridge vertically (e.g., in the Z-direction) adjacent interconnect layers.

In some embodiments, the layers of the insulating material layer 142 and the back-end-of-line (BEOL) stack 144 may comprise any suitable dielectric material, such as silicon carbide, lanthanum oxide, aluminum oxynitride, zirconium oxide, hafnium oxide, silicon nitride, silicon, zinc oxide, zirconium nitride, aluminum zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, tantalum carbonitride, zirconium silicide, silicon oxycarbide, silicon carbonitride, hafnium silicide, silicon oxide, or combinations of the foregoing. In some embodiments, each of the conductive material layer 146, the conductive material layer 164, and the trench conductor layer 162 may include any suitable conductive material, such as W, Al, Cu, Co, Ti, Ta, Ru, Mo, a silicide material, and a conductive nitride material. Other materials that may be used for the insulating material layer 142, the back end of line (BEOL) stack 144, the conductive material layer 146, the conductive material layer 164, and the trench conductor layer 162 are also within the spirit and scope of the present disclosure.

Fig. 1D shows an enlarged cross-sectional view of region 131 of fig. 1B. As shown in fig. 1D, the insulating material layer 142 may include a top surface 145 in contact with the conductive material layer 146, a bottom surface 141 in contact with the dielectric top surface of the field effect transistor 102, e.g., the top surface of the source/drain (S/D) liner layer 126 and/or the top surface of the gate liner layer 128, and a sidewall 143. In some embodiments, the insulating material layer 142 may further include an upper shoulder structure 152, wherein the upper shoulder structure 152 may be gradually sloped from the sidewall 143 to the top surface 145 to connect the top surface 145 and the sidewall 143. For example, the upper shoulder structure 152 may have a warped surface (warped surface), a curved surface (curved surface), or a rounded surface (rounded surface) that is inclined from the end 151 on the sidewall 143 toward the end 153 on the top surface 145. Such tilting of upper shoulder structure 152The curved, or rounded surfaces may enhance gap filling of the conductive material layer 146 within vias formed in the insulating material layer 142 to contact the underlying trench conductor layer 130. The above-described upper shoulder structure 152 may have a vertical (e.g., in the Z-direction) displacement H₁₅₂And a horizontal (e.g., in the X direction) displacement W₁₅₂Determined by the growth process associated with the layer of insulating material 142 and/or the etching process associated with the patterned back end of line (BEOL) stack 144. In some embodiments, a vertical (e.g., in the Z-direction) displacement H between end 151 and end 153₁₅₂And may range between about 0.1nm to about 10 nm. This vertical (e.g., in the Z direction) displacement H₁₅₂The lower limit of the range may ensure reliable filling of the conductive material layer 146 in the via formed in the insulating material layer 142. Horizontal (e.g., in the X-direction) displacement W between end 151 and end 153₁₅₂And may range between about 0.1nm to about 10 nm. This horizontal (e.g., in the X direction) displacement W₁₅₂The lower limit of the range may ensure reliable filling of the conductive material layer 146 in the via formed in the insulating material layer 142. In some embodiments, the insulating material layer 142 may further include a lower shoulder structure 154, where the lower shoulder structure 154 is caused by a lateral (e.g., in the X-direction) extension of the insulating material layer 142 during growth of the insulating material layer 142. The lower shoulder structure 154 may connect the bottom surface 141 and the sidewalls 143 by gradually sloping from the sidewalls 143 to the bottom surface 141. For example, the lower shoulder structure 154 may have a warped surface, a curved surface, or a rounded surface that gradually slopes from the end 157 of the sidewall 143 toward the end 155 of the bottom surface 141. During growth of the layer of insulating material 142, the shoulder structures 154 may have a vertical (e.g., in the Z-direction) displacement H from the lateral extension of the insulator layer₁₅₄And a horizontal (e.g., in the X direction) displacement W₁₅₄. In some embodiments, a perpendicular (e.g., in the Z-direction) displacement H between end 155 and end 157₁₅₄And may range between about 0.1nm to about 10 nm. This vertical (e.g., in the Z direction) displacement H₁₅₄May ensure that the conductive material layer 146 is filled in an insulating layerReliability inside the via formed in the rim material layer 142. In some embodiments, a horizontal (e.g., in the X direction) displacement W between end 155 and end 157₁₅₄And may range between about 0.1nm to about 10 nm. This horizontal (e.g., in the X direction) displacement W₁₅₄The upper limit of the range may ensure reliability of filling the conductive material layer 146 inside the via hole formed in the insulating material layer 142. In some embodiments, the layer of insulating material 142 may extend horizontally (e.g., in the X-direction) from the top dielectric surface of the field effect transistor 102 to the top metal surface of the field effect transistor 102. For example, as shown in fig. 1D, the insulating material layer 142 may extend over an edge portion of the trench conductor layer 130 and open to a central portion of the trench conductor layer 130. A bottom surface 141 of the layer of insulating material 142 may cover a top dielectric surface of the two field effect transistors 102, e.g., a top surface of the source/drain (S/D) liner layer 126 and/or a top surface of the gate liner layer 128, and an edge portion of a top surface of the trench conductor layer 130. That is, the end portion 155 adjacent to the lower shoulder structure 154 may be provided on an edge portion of the trench conductor layer 130. For example, insulating material layer 142 may have a horizontal (e.g., in the X-direction) extension EXT between end 155 and a dielectric surface (e.g., source/drain liner layer 162) of field effect transistor 102₁₅₅. And this horizontally extends EXT₁₅₅And may range between about 0.1nm and about 10 nm. Such horizontal (e.g., in the X direction) extension EXT₁₅₅The upper limit of the range may ensure reliability of filling the conductive material layer 146 inside the via hole formed in the insulating material layer 142. In some embodiments, the insulating material layer 142 can extend through an edge portion of the trench conductor layer 130, wherein lines extending through the end portions 151 and 157 can extend through a top surface of the trench conductor layer 130.

In some embodiments, the sidewalls 143 of the insulating material layer 142 may comprise a flat surface substantially perpendicular to the top surface of the substrate 106, the top surface of the source/drain (S/D) contacts 124, the top surface of the gate electrode 112C, and/or the top surface of the trench conductor layer 130. For example, the lines extending through end 151 and end 157 may be substantially perpendicular to the top surface of substrate 106, the top surface of the source/drain (S/D) contacts, the top surface of gate electrode 112C, and/or the top surface of trench conductor layer 130. In some embodiments, the sidewall 143 of the insulating material layer 142 may include a warped surface, a curved surface, or a rounded surface (not shown in fig. 1D). In some embodiments, the sidewalls 143 of the insulating material layer 142 may include a flat surface that is oblique to the substrate 106, the source/drain (S/D) contacts 124, the gate electrode 112C, and/or the trench conductor layer 130. For example, a line extending through end 151 and end 157 may be inclined at an angle in a range between about 45 degrees and about 135 degrees to the top surface of substrate 106, the top surface of source/drain (S/D) contacts 124, the top surface of gate electrode 112C, and/or the top surface of trench conductor layer 130.

As previously discussed, the layer of conductive material 146 may be formed through a via of the layer of insulating material 142 and in contact with the trench conductor layer 130. Referring to fig. 1D, a layer of conductor material 146 may be in contact with the trench conductor layer 130 through a via of insulating material 142, with sidewalls 143 on opposite sides of the via of insulating material 142. In some embodiments, the conductive material layer 146 may further include footing structures (footing structures)147 on opposite sides of the via of the insulating material 142. For example, as shown in fig. 1D, each footing structure 147 may stand on the top surface of the trench conductor layer 130 and may have an inclined surface that gradually inclines from the edge of the conductive material 146 toward the central region of the conductive material 146. Each footing structure 147 can be adjacent to insulating material layer 142 and substantially conformal with insulating material layer 142. In some embodiments, each footing structure 147 can be disposed between the insulating material layer 142 and the trench conductor layer 130. For example, the footing structures 147 may be disposed below the sidewalls 143 of the insulating material layer 142 and above the trench conductor layer 130. In some embodiments, a footing structure 147 may be disposed between the layer of insulating material 142 and a top dielectric surface of the field effect transistor 102, e.g., a top surface of the source/drain (S/D) liner layer 126 and/or a top surface of the gate liner layer 128. In some embodiments, each footing structure 147 can have a horizontal (e.g., in the X-direction) dimension and a vertical (e.g., in the Z-direction) dimension, respectively, and interface with an underlying shoulderHorizontal displacement W of the structure 154₁₅₄And vertical displacement H of the lower shoulder structure 154₁₅₄Are substantially the same.

In some embodiments, the conductive material layer 146 may include a liner layer 146A and a metal layer 146B. As shown in fig. 1D, the footing structure 147 can include a lining layer 146A. In some embodiments, the footing structure 147 can also include portions of the metal layer 146B. In some embodiments, the trench conductor layer 130 may have a liner layer 130A and a metal layer 130B. By way of example and not limitation, each of the liner layer 130A, the metal layer 130B, the liner layer 146A, and the metal layer 146B may comprise any suitable conductive material, such as W, Al, Cu, Co, Ti, Ta, Ru, Mo, a silicide material (e.g., titanium silicide, cobalt silicide, or nickel silicide), a conductive nitride material (e.g., titanium nitride or tantalum nitride), or a combination of the foregoing. Based on the disclosure herein, other materials that can be used for the liner layer 130A, the metal layer 130B, the liner layer 146A, and the metal layer 146B are also within the spirit and scope of the present disclosure.

In some embodiments, referring to fig. 1E, the liner layer 130A and the metal layer 130B may be a multilayer structure. For example, the backing layer 130A may include a lower liner layer (lower liner layer)130A₁And a lower liner layer 130A formed on the lower liner layer₁An upper liner layer (130A) thereon₂And the metal layer 130B may include a lower metal layer (lower metal layer)130B₁And a lower metal layer 130B formed on the lower metal layer₁An upper metal layer (130B) thereon₂. Lower metal layer 130B₁And an upper metal layer 130B₂May be separately on the lower liner layer 130A₁And an upper liner layer 130A₂Is prominent in the middle. In some embodiments, the upper backing layer 130A₂May be located in the lower metal layer 130B₁And an upper metal layer 130B₂In the meantime. Lower liner layer 130A₁And an upper liner layer 130A₂ Lower metal layer 130B₁And an upper metal layer 130B₂May comprise any suitable conductive material, e.g., W, Al, Cu, Co, Ti, Ta, Ru, Mo, aA silicide material (e.g., titanium silicide, cobalt silicide, or nickel silicide), a conductive nitride material (e.g., titanium nitride or tantalum nitride), or a combination thereof. Other materials may be used for the lower liner layer 130A based on the disclosure herein₁And an upper liner layer 130A₂ Lower metal layer 130B₁And an upper metal layer 130B₂Are also within the spirit and scope of the present disclosure.

In some embodiments, referring to fig. 1F, a back-end-of-line (BEOL) stack 144 may be disposed between the layer of insulating material 142 and the source/drain (S/D) pad layer 126, and/or between the layer of insulating material 142 and the gate pad layer 128. For example, the back-end-of-line (BEOL) stack 144 may include a first back-end-of-line etch stop layer 144A and a second back-end-of-line etch stop layer 144B, both formed over the source/drain (S/D) liner layer 126 and the gate liner layer 128. Accordingly, the insulating material layer 142 may be combined with a back-end-of-line (BEOL) stack 144 to enhance isolation between the conductive material layer 146 and the underlying source/drain (S/D) contacts 124, and/or to enhance isolation between the conductive material layer 146 and the gate electrode 112C, thereby reducing time dependent dielectric breakdown failure (TDDB failure) between the interconnect structure 140 and the field effect transistor 102. The conductive material layer 146 may be connected to the underlying source/drain (S/D) contacts 124 and/or gate electrode 112C via the trench conductor layer 130. For example, the trench conductor layer 130 may be formed through the first back-end-link etch stop layer 144A, the second back-end-link etch stop layer 144B, and the source/drain (S/D) pad layer 126 to contact the underlying source/drain (S/D) contact 124. The layer of conductive material 146 may be formed through a portion of the layer of insulating material 142 vertically above (e.g., in the Z-direction) the trench conductor layer 130 to contact the underlying trench conductor layer 130. In some embodiments, the trench conductor layer 130 may be formed through the first back-end-of-line etch stop layer 144A, the second back-end-of-line etch stop layer 144B, and the gate liner layer 128 to contact the underlying gate electrode 112C. In some embodiments, the trench conductor layer 130 may be substantially coplanar with a back-end-of-line (BEOL) stack 144.

Fig. 2 is a flow diagram of an example method 200 for fabricating the semiconductor device 100, in accordance with some embodiments. For illustrative purposes, the steps shown in fig. 2 will be described with reference to exemplary processes for manufacturing the semiconductor device 100 shown in fig. 3A-3B, fig. 4, fig. 5A-5C, fig. 6A-6C, and fig. 7-9. Fig. 3A is an isometric view of various stages in the manufacture of semiconductor device 100, according to some embodiments. Fig. 3B, 4, 5A-5C, 6A-6C, and 7-9 are cross-sectional views of various stages of fabrication along line B-B of fig. 3A in forming semiconductor device 100, according to some embodiments. The steps shown may be performed in a different order or not performed depending on the particular application. The method 200 may not yield a complete semiconductor device 100. Thus, it can be appreciated that additional processes can be provided before, during, and after the method 200, and that some other processes are only briefly described herein. Furthermore, unless otherwise noted, the discussion of elements in fig. 1A-1F, 3A-3B, 4, 5A-5C, 6A-6C, and 7-9 applies to each other with the same notations for the discussion of elements.

In step 205, a transistor structure having a dielectric top surface and a metal top surface is provided. For example, fig. 5A illustrates a semiconductor device 500 having one or more field effect transistors 102, the field effect transistors 102 having a metal top surface 130s and dielectric

top surfaces

126s and 128 s. In step 205, a semiconductor device 300 as shown in fig. 3A and 3B is provided. The semiconductor device 300 may include a fin structure 108 laterally spanned by a gate structure 112 and clad by an interlayer dielectric (ILD) layer 118. By way of example and not limitation, the formation of the semiconductor device 300 may include forming a fin structure 108 on the substrate 106, forming shallow trench isolation regions 138 adjacent to the fin structure 108, forming a gate structure 112 across the fin structure 108, forming an inter-layer dielectric (ILD) layer 118 over portions of the fin structure 108 not covered by the gate structure 112, forming source/drain (S/D) regions 110, and forming a gate liner layer 128 having a dielectric top surface 128S on the gate structure 112. In some embodiments, as shown in fig. 3B, forming the fin structure 108 may include forming a channel layer 122 in contact with the substrate 106 (e.g., the field effect transistor 102 may become a finfet after the steps of the method 200). In some embodiments, forming the fin structure 108 may include one or more channel layers 122 below the gate structure 112 and separated from the substrate 106 (e.g., the field effect transistor 102 may become a gate-all-around field effect transistor (GAA FET) after operation of the method 200). Other methods of forming the semiconductor device 300 are also within the spirit and scope of the present disclosure.

Further, in step 205, source/drain (S/D) contacts 124 and source/drain (S/D) liner layers 126 may be formed on the semiconductor device 300 (shown in fig. 3A and 3B) to form the semiconductor device 400 (shown in fig. 4). By way of example and not limitation, the process of forming the source/drain contact 124 and the source/drain liner layer 126 may include forming an opening (not shown in fig. 4) adjacent the gate structure 112 by removing a portion of the interlayer dielectric layer 118, forming the source/drain (S/D) contact 124 in the opening, depositing a dielectric material on the source/drain (S/D) contact 124, and polishing the dielectric material to form the source/drain (S/D) liner layer 126 having a top surface 126S. By way of example and not limitation, the process of forming the source/drain contacts 124 may include depositing one or more conductive materials in the openings, polishing the deposited one or more conductive materials using a Chemical Mechanical Polishing (CMP) process, and etching back the polished one or more conductive materials using a dry etch or wet etch process to form the source/drain (S/D) contacts 124. Other methods of forming the source/drain contacts 124 and the source/drain liner layer 126 are also within the spirit and scope of the present disclosure.

Further, in step 205, a trench conductor layer 130 may be formed over the source/drain (S/D) contacts 124. Referring to fig. 5A, the process of forming the trench conductor layer 130 over the source/drain (S/D) contacts 124 may include (i) forming an opening (not shown in fig. 5A) in the source/drain (S/D) pad layer 126 via a dry etching process (e.g., reactive ion etching) or a wet etching process to expose portions of the source/drain (S/D) contacts 124, (ii) blanket forming a conductive layer over the source/drain (S/D) pad layer 126 in the opening and on the source/drain (S/D) pad layer 126(ii) depositing one or more conductive materials, and (iii) polishing the deposited one or more conductive materials using a Chemical Mechanical Polishing (CMP) process to form the trench conductor layer 130, and the metal top surface 130S of the trench conductor layer 130 is substantially coplanar with the top surface 126S of the source/drain (S/D) liner layer 126 and/or the top surface 128S of the gate liner layer 128. In some embodiments, the top surface 130s of the trench conductor layer 130 may have a horizontal (e.g., in the X-direction) dimension W in the range of about 2nm to about 50nm₁₃₀. In some embodiments, the blanket deposition of one or more conductive materials may include depositing a layer of liner material followed by a layer of metallic material, wherein the layer of liner material and the layer of metallic material form liner layer 130A (shown in fig. 1D) and metallic layer 130B (shown in fig. 1D), respectively, after a subsequent polishing process.

In some embodiments, referring to fig. 5B, polishing the deposited one or more conductive materials may further enable the top surface 130S of the trench conductor layer 130, the top surface 126S of the source/drain (S/D) liner layer 126, and the top surface 128S of the gate liner layer 128 to be coplanar with the dielectric top surface 114S of the gate spacer 114.

In some embodiments, referring to fig. 5C, a trench conductor layer 130 may be formed over the gate electrode 112C. As an example and not by way of limitation, the process of forming the trench conductor layer 130 over the gate structure 112C may include (i) forming an opening (not shown in fig. 5C) in the gate liner layer 128 via a dry etching process (e.g., reactive ion etching) or a wet etching process to expose a portion of the gate electrode 112C, (ii) blanket depositing one or more conductive materials in the opening and on the gate liner layer 128 using a deposition process, and (iii) polishing the deposited one or more conductive materials using a Chemical Mechanical Polishing (CMP) process to form the trench conductor layer 130, with the metal top surface 130S of the trench conductor layer 130 substantially coplanar with the top surface 126S of the source/drain (S/D) liner layer 126 and/or the top surface 128S of the gate liner layer 128. By way of example and not limitation, the aforementioned one or more conductive materials may include W, Al, Cu, Co, Ti, Ta, Ru, Mo, a silicide material (e.g., NiSi or CoSi), or a conductive nitride material (e.g., TiN or TaN), which may be deposited using a process selected from Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), e-beam evaporation, or other suitable process.

Referring to fig. 2, in step 210, a layer of insulating material is selectively formed over the top dielectric surface of the transistor structure, thereby exposing the top metal surface 130 s. For example, as shown in fig. 6C, a layer of insulating material 142 is selectively formed over the top surface 126S of the source/drain (S/D) pad layer 126 and the top surface 128S of the gate pad layer 128, thereby exposing the top surface 130S of the trench conductor layer 130. In some embodiments, the process of forming the insulating material layer 142 may include (i) forming a layer of inhibiting material 602 (shown in fig. 6A) on the top metal surface 130s, (ii) blanket depositing one or more insulating materials on the semiconductor device 600 of fig. 6A to form the insulating material layer 142, the insulating material layer 142 having a via 601 (shown in fig. 6B) that may be connected to the trench conductor layer 130, and (iii) removing the inhibiting material layer 602 to expose the trench conductor layer 130 (shown in fig. 6C).

Referring to fig. 6A, as an exemplary and non-limiting example, the inhibiting material layer 602 may include an oxide material, an organic material, a carbon-containing material, or amphiphilic molecules (ampiphilic-like molecules), such as an amphiphilic polymer molecule (ampiphilic polymer molecule) that may have both polar and non-polar bonds. The inhibiting material layer 602 may be selectively grown on a surface of the metal material (e.g., the top surface 130s) while exposing a surface of the insulating material (e.g., the top surface 126s and/or the top surface 128 s). For example, the inhibiting material layer 602 may be a self-assembled monolayer (SAM) material that may selectively form one or more molecular monolayers on the metal surface (e.g., the top surface 130s) using a self-assembled monolayer (SAM) process. By way of illustration and not limitation, the self-assembled monolayer film process may be a spin-on process, a liquid phase deposition process, or a vapor phase deposition process. As shown in fig. 6A, the inhibiting material layer 602 may cover a central portion of the metal surface (e.g., the top surface 130s) while exposing an edge portion (edge portion) of the metal surface. In some embodiments, the inhibiting material layer 602 may completely cover the underlying metal surface (e.g., the top surface 130 s). Other materials and methods of formation for the suppression material layer 602 are also within the spirit and scope of the present disclosure.

Referring to fig. 6B, one or more insulating materials may be blanket deposited via a deposition process to form the insulating material layer 142 while exposing the inhibiting material layer 602. By way of example and not limitation, the deposition process may include a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, a Physical Vapor Deposition (PVD) process, or an Atomic Layer Deposition (ALD) process. In some embodiments, the deposition process may be to densify the layer of insulating material 142. The densification of the insulating material layer 142 may improve the breakdown voltage associated with the insulating material layer 142 to reduce Time Dependent Dielectric Breakdown (TDDB) by reducing the porosity (porosity) and/or grain boundaries (grain boundary) of the insulating material layer 142. In some embodiments, the deposition process that may densify the insulating material layer 142 may be a deposition process associated with a deposition temperature in a range of about 300 ℃ to about 700 ℃, as such a temperature range may enhance atomic bonding within the insulating material layer 142. In some embodiments, the deposition process that may densify the insulating material layer 142 may be about

To about

A range of deposition rates associated with the deposition process, since such a range of deposition rates can both enhance atomic bonding within the insulating material layer 142 and meet throughput requirements (throughput requirements) of the semiconductor device 100 during manufacturing.

Due to the presence of the suppression material layer 602, the deposition process on the suppression material layer 602 may be delayed or suppressed, thereby forming a through-insulationThe through holes 601 of the material layer 142. The via 601 may be connected to the inhibiting material layer 602, and the via 601 may expose the sidewall 143 of the insulating material layer 142. In some embodiments, the via 601 may have a horizontal (e.g., in the X-direction) dimension W in the range of about 2nm to about 25nm₆₀₁. In some embodiments, the deposition process may further include growing the insulating material layer 142 laterally (e.g., in the X-direction and/or Y-direction) over edge portions of the suppression material layer 602. The sidewalls 143 of the formed insulating material layer 142 are thus vertically (e.g., in the Z-direction) over the underlying metal surface (e.g., top surface 130 s). Thus, the horizontal dimension W of the via 601₆₀₁May be less than or equal to the horizontal dimension W of the trench conductor layer 130₁₃₀. In some embodiments, such lateral growth may result in insulating material layer 142 having lower shoulder structures 154 and/or upper shoulder structures 152, and each of lower shoulder structures 154 and upper shoulder structures 152 having warped, curved, or rounded surfaces.

Referring to fig. 6C, removing the inhibiting material layer 602 may include using a plasma dry etch, a wet etch process, an ashing process, or a combination thereof to selectively remove the inhibiting material 602 layer from the insulating material 142 and the trench conductor layer 130. As an example and not by way of limitation, the aforementioned wet etching may use a mixture of sulfuric acid and hydrogen peroxide (SPM) of about 130 ℃, and the aforementioned ashing process may be performed using ozone radicals caused by an ultraviolet light source. After removal of the suppression material layer 602, the bottom of the via 601 is connected to the underlying trench conductor layer 130. In some embodiments, due to lateral growth of the insulating material layer 142 during its deposition, the sidewalls of the via 601 may thus form a footing structure 647 of the trench conductor layer 130 adjacent the bottom after removal of the inhibiting material layer 602. In some embodiments, the footing structure 647 is similar to the footing structure 147 previously described. For example, this footing structure 647 may have substantially the same shape as the footing structure 147 previously described. In some embodiments, this footing structure 647 may have substantially the same volume as the footing structure 147 previously described.

In some embodiments, the process of forming the layer of insulating material 142 may include selectively growing the layer of insulating material 142 on the source/drain (S/D) pad layer 126 and/or the gate pad layer 128 using a selective deposition process while exposing the trench conductor layer 130. By way of example and not limitation, the selective deposition process may include a CVD process or an ALD process. In some embodiments, the selective deposition process may deposit the insulating material layer 142 on edge portions of the top surface 130S of the trench conductor layer 130, which may be between the central portion and the source/drain (S/D) pad layer 126 or between the central portion and the gate pad layer 128, while exposing a central portion of the top surface 130S of the trench conductor layer 130.

Referring to fig. 2, in step 215, a conductive material layer is formed on the insulating material layer and the top metal surface. For example, as shown in fig. 9, a layer of conductive material 146 may be formed on the insulating material layer 142 and the top surface 130s of the trench conductor layer 130, as shown with reference to fig. 7-9. In some embodiments, the process of forming the conductive material layer 146 may include (i) forming a back-end-of-line (BEOL) stack 144 (shown in fig. 7) on a portion of the insulating material layer 142, (ii) depositing one or more conductive materials on the semiconductor device 700 of fig. 7; and (iii) polishing the deposited one or more conductive materials using a Chemical Mechanical Polishing (CMP) process to form a conductive material layer 146 (shown in fig. 8).

Referring to fig. 7, as an example and not by way of limitation, the process of forming the back-end-of-line (BEOL) stack 144 may include (i) blanket depositing one or more dielectric layers (e.g., a first back-end-of-line etchstop layer 144A, a second back-end-of-line etchstop layer 144B, and a back-end-of-line interlayer dielectric layer 144C) on the semiconductor device 600 of fig. 6C by a deposition process, (ii) masking the one or more deposited dielectric layers using a lithographically defined photoresist layer (not shown in fig. 7), and (iii) etching exposed portions of the one or more dielectric layers of the photoresist layer using a wet etching process or a dry etching (e.g., reactive ion etching) process to form a via 701, such via 701 communicating with the via 601 and exposing a metal surface (e.g., the top surface 130 s). In some embodiments, the blanket deposition of the one or more dielectric layers may be performed using any suitable deposition method, such as a Chemical Vapor Deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a Physical Vapor Deposition (PVD) process, or an Atomic Layer Deposition (ALD) process.

Referring to fig. 8, one or more conductive materials may be deposited on semiconductor device 700 (shown in fig. 7) by any suitable deposition process, such as CVD, PVD, or e-beam evaporation. In some embodiments, the deposition of the one or more conductive materials may be performed by an Atomic Layer Deposition (ALD) process of the one or more conductive materials conformal with the sidewalls of the via 601 and the sidewalls of the via 701.

Referring to fig. 2, in step 220, an interconnect structure is formed over the metal layer. For example, as shown in fig. 9, an interconnect layer 140 may be formed over a layer of insulating material 142₂. In some embodiments, interconnect layer 140 is formed₂The processes of (i) blanket depositing one or more dielectric layers (e.g., insulating material layer 148) over the semiconductor device 800 of fig. 8 by a suitable deposition process (e.g., a Chemical Vapor Deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a Physical Vapor Deposition (PVD) process, or an Atomic Layer Deposition (ALD) process), (ii) using a photolithography process and an etching process to form a via that passes through the deposited dielectric layer and exposes the insulating material layer 142, (iii) filling the via with one or more conductive materials (e.g., using a suitable deposition process (e.g., CVD, ALD, PVD, or e-beam evaporation) and using a polishing process (e.g., CMP process), and (iv) using a suitable deposition process (e.g., CVD, ALD, PVD, or electron beam evaporation), to deposit a layer 164 of conductive material over the previously deposited dielectric layer or layers, such as the layer 148 of insulating material.

The present disclosure provides example isolation structures and methods of forming the same. The isolation structure may include a layer of insulating material between the transistor structure and the interconnect structure. In some embodiments, the layer of insulating material may include an upper shoulder structure and a lower shoulder structure. In some embodiments, a method of forming an isolation structure may include selectively depositing one or more insulating materials over a top dielectric surface of a transistor structure and forming an opening to expose a top metal surface of the transistor structure. This isolation structure provides a number of advantages; for example, it may enhance electrical isolation between the interconnect structure and the underlying transistor structure, thereby avoiding leakage defects in the integrated circuit, such as Time Dependent Dielectric Breakdown (TDDB) in the integrated circuit.

In some embodiments, the present disclosure provides a method of forming an interconnect structure. The method comprises forming a first insulating material layer on a substrate; forming a via access in the first insulating material layer; filling the recessed through hole with a conductive material layer; and selectively forming a second insulating material layer on the first insulating material layer, and opening the second insulating material layer to the conductive material layer.

In some embodiments, the selectively forming the second insulating material layer includes selectively depositing the second insulating material layer over the first insulating material layer and exposing the conductive material layer.

In some embodiments, selectively forming the second layer of insulating material includes selectively forming a layer of inhibiting material over the layer of conductive material and exposing a top surface of the first layer of insulating material; and depositing the second insulating material layer above the first insulating material layer to expose the inhibiting material layer.

In some embodiments, selectively forming the second insulating material layer includes depositing the second insulating material layer over a first portion (first portion) of the conductive material layer and exposing a second portion (second portion) of the conductive material layer, wherein the first portion of the conductive material layer is between the first insulating material layer and the second portion of the conductive material layer.

In some embodiments, the method further comprises forming another conductive material layer over the second insulating material layer, wherein the another conductive material layer contacts the conductive material layer.

In some embodiments, the method further comprises forming another conductive material layer over the substrate, wherein the first insulating material layer and the conductive material layer are on the another conductive material layer.

In some embodiments, the method further comprises forming a third insulating material layer over the second insulating material layer, wherein the third insulating material layer is open to the conductive material layer.

In some embodiments, a method of forming an interconnect structure may include forming a fin structure (fin structure) on a substrate; forming a conductive material layer on the fin structure; forming a first insulating material layer on the fin structure, wherein the first insulating material layer is in contact with the conductive material layer; forming a second insulating material layer on the first insulating material layer; and forming a via access in the second insulating material layer while forming the second insulating material layer.

In some embodiments, forming the recessed via includes forming a shoulder structure in the second insulating material layer, wherein the shoulder structure connects a side surface of the second insulating material layer to a bottom surface of the second insulating material layer.

In some embodiments, forming the second layer of insulating material includes selectively depositing the second layer of insulating material over the first layer of insulating material and exposing the layer of conductive material.

In some embodiments, forming the recessed via comprises: forming a suppressing material layer over the conductive material layer; and forming the second insulating material layer above the first insulating material layer to expose the inhibiting material layer.

In some embodiments, the method of forming an interconnect structure further comprises: forming a third insulating material layer on the substrate, the third insulating material layer being substantially coplanar with the first insulating material layer, wherein the first insulating material layer is coplanar between the third insulating material layer and the conductive material layer.

In some embodiments, the method of forming an interconnect structure further comprises: forming another conductive material layer in the recessed via and over the second insulating material layer, wherein the another conductive material layer is in contact with the conductive material layer.

In some embodiments, the method of forming an interconnect structure further comprises: forming another insulating material layer on the substrate; forming another recessed via in the another insulating material layer, wherein a bottom of the another recessed via is opened to the recessed via; and forming another conductive material layer in the recessed via and the another recessed via.

In some embodiments, the method of forming an interconnect structure further comprises: forming another conductive material layer above the fin structure and adjacent to the conductive material layer; and forming another insulating material layer between the conductive material layer and the another conductive material layer.

In some embodiments, an interconnect structure is provided. The interconnection structure comprises a substrate, a first insulating material layer on the substrate, and a first conductive material layer in the first insulating material layer; and a second insulating material layer on the first insulating material layer. The second insulating material layer may include a top surface, a sidewall, and a shoulder structure. The shoulder structure may connect the sidewall to the top surface, and the shoulder structure may be sloped from the sidewall to the top surface. The interconnect structure may further include a second conductive material layer formed in the second insulating material layer and surrounded by the sidewalls of the second insulating material layer.

In some embodiments, the second insulating material layer further includes a bottom surface and another shoulder structure connecting the bottom surface to the sidewall, the another shoulder structure being inclined from the sidewall to the bottom surface; and the bottom surface is in contact with the first layer of insulating material.

In some embodiments, the shoulder structure includes a rounded surface that slopes from the sidewall to the top surface.

In some embodiments, the sidewall includes a rounded surface.

In some embodiments, the second conductive material layer contacts the first conductive material layer.

The components of several embodiments are summarized above so that those skilled in the art to which the present invention pertains can more clearly understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A method of forming an interconnect structure, comprising:

forming a first insulating material layer on a substrate;

forming a concave through hole in the first insulating material layer;

filling the recessed via with a conductive material layer; and

a second insulating material layer is selectively formed over the first insulating material layer, and the second insulating material layer is then opened to the conductive material layer.