CN112735494A - Memristor resistance value regulation and control method and device, computer terminal and storage medium - Google Patents
Memristor resistance value regulation and control method and device, computer terminal and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a memristor resistance regulating and controlling method and device, a computer terminal and a storage medium, wherein the method comprises the following steps: step 1, determining a first resistance value of a memristor, and if the first resistance value is larger than a preset threshold value, executing a step 2; step 2, performing electroforming; step 3, judging whether electroforming is successful, and if electroforming is successful, executing step 4; step 4, determining a second resistance value of the memristor; step 5, if the second resistance value is outside the target resistance value area, performing resistance value modulation; step 6, determining a third resistance value of the memristor; and 7, if the third resistance value is in the target resistance value area, performing resistance value verification, and if the resistance value verification is successful, finishing resistance value regulation and control. The scheme realizes the effect of gradually approaching the resistance value of the memristor to the target resistance value.
Description
Technical Field
The invention relates to the technical field of memristor resistance regulation, in particular to a memristor resistance regulation method and device, a computer terminal and a storage medium.
Background
The Memristor is called a memory resistor (named Memristor in english), and is a circuit device for expressing the relationship between magnetic flux and electric charge. The resistance of a memristor is determined by the charge flowing through it. The effective resistance regulation of the memristor is the premise for realizing the application of various memristors. For example, in neuromorphic and in-memory calculations based on memristors, to implement basic system functions, a fast, accurate and stable resistance value writing must be performed on the memristors.
At present, in order to solve the problem of resistance adjustment of memristors, methods widely adopted in the industry include: firstly, fixing pulse parameters and modulating resistance values by applying pulse quantity; secondly, a method for changing the pulse amplitude modulation resistance value; and thirdly, a method for changing the pulse width modulation resistance value. However, due to the limitation of the preparation process of the memristor, the operation methods have poor adaptability, and the resistance of the practical memristor is difficult to be accurately and stably regulated.
Disclosure of Invention
In view of this, the invention provides a memristor resistance value regulation and control method, a device, a computer terminal and a storage medium, which are used for realizing accurate and stable regulation and control of the resistance value of a memristor.
Specifically, the present invention proposes the following specific examples:
in a first aspect, the embodiment of the invention provides a memristor resistance value regulation and control method, wherein the memristor is connected with a transistor, the pulse amplitude applied to the memristor is constant, and the gate voltage is applied to the gate of the transistor; the method comprises the following steps:
and 7, carrying out resistance value verification on the memristor, and finishing resistance value regulation and control on the memristor if the resistance value verification is successful.
With reference to the first aspect, in some optional embodiments, the step 2 includes:
With reference to the first aspect, in some optional embodiments, the method further comprises: if the first resistance value is smaller than a preset value, determining that the memristor is damaged, and executing an ending process; the preset value is smaller than the minimum resistance value in the target resistance value region.
With reference to the first aspect, in some optional embodiments, the method further comprises: and if the first resistance value is within the target resistance value area, executing step 7.
With reference to the first aspect, in some optional embodiments, the method further comprises: and if the first resistance value is outside the target resistance value area, the first resistance value is larger than the preset value, and the first resistance value is smaller than the preset threshold value, executing the step 5.
With reference to the first aspect, in some optional embodiments, the method further comprises: if the electroforming is not successful, the grid voltage is increased; and (3) performing electroforming on the memristor through the pulse and the grid voltage after being increased, and performing step 3.
With reference to the first aspect, in some optional embodiments, the method further comprises: recording the number of unsuccessful times of performing the electroforming; and if the unsuccessful times exceed the set upper limit value, executing the ending process.
With reference to the first aspect, in some optional embodiments, the method further comprises: and if the second resistance value is within the target resistance value area, executing step 7.
The method comprises the following steps: positive and negative pulses; the step 5 comprises the following steps:
step 51, selecting a pulse width based on the second resistance value; the larger the second resistance value is, the smaller the selected pulse width is;
step 52, initializing the grid voltage according to the Set direction and the Reset direction respectively to obtain the Set grid voltage and the Reset grid voltage; the Set grid voltage is less than the Reset grid voltage;
step 53, if the second resistance value is smaller than the target resistance value of the memristor, calling the Reset gate voltage, and selecting the negative pulse to apply a group of pulses at preset time intervals according to the selected pulse width;
step 54, if the second resistance value is larger than the target resistance value, calling the Set gate voltage, and selecting the positive pulse to apply a group of pulses at the preset time interval according to the selected pulse width;
step 55, recording the resistance value of the memristor after each pulse application, and setting the recorded resistance value to be the second resistance value, so as to execute step 53 or step 54;
and 56, if the preset number of resistance values are obtained and the current latest resistance value is in the target resistance value area, completing resistance value modulation of the memristor.
With reference to the first aspect, in some optional embodiments, the method further comprises: if the current latest resistance value is outside the target resistance value area, judging whether the latest pulse causes the change of the magnitude relation between the current latest resistance value and the target resistance value; if the determination is changed, executing step 53 or step 54 based on the initial Set gate voltage and the initial Reset gate voltage; if the resistance value is judged to be unchanged, judging whether the maximum difference value of any two resistance values in the preset number of resistance values is larger than the product of the latest current resistance value and a preset percentage; the larger the current latest resistance value is, the smaller the corresponding preset percentage is; if yes, keeping the current Set grid voltage and the current Reset grid voltage to execute step 53 or step 54; if the result of the determination is negative, increasing the Set gate voltage and the Reset gate voltage to execute step 53 or step 54.
With reference to the first aspect, in some optional embodiments, increasing the Set gate voltage and the Reset gate voltage includes: increasing the Set gate voltage in a manner of increasing a first increase value each time; increasing the Reset gate voltage by increasing a second increment value each time; wherein the first increment value is less than the second increment value; the smaller the difference between the current latest resistance value and the target resistance value is, the smaller the first increment value and the second increment value are.
With reference to the first aspect, in some optional embodiments, both the Set gate voltage and the Reset gate voltage are provided with upper limit values, and the upper limit value of the Set gate voltage is smaller than the upper limit value of the Reset gate voltage.
With reference to the first aspect, in some optional embodiments, the step 6 includes: continuously reading a third resistance value of the memristor for multiple times after the resistance value is modulated to obtain multiple third resistance values, and executing step 7 if the newly obtained third resistance value is in the target resistance value region;
the step 7 comprises the following steps:
step 71, judging whether each third resistance value is in the target resistance value region, and whether the maximum difference value of any two third resistance values in the plurality of third resistance values is smaller than the product of the target resistance value of the memristor and a preset proportion; the larger the target resistance value is, the smaller the corresponding preset proportion is;
and step 72, if the judgment results are yes, determining that the resistance value verification is passed.
With reference to the first aspect, in some optional embodiments, if the determination results are not all yes, the third resistance value deviating from the target resistance value to the maximum is selected as the second resistance value, so as to execute step 5.
With reference to the first aspect, in some optional embodiments, the amplitude of the pulse is a maximum voltage amplitude that the memristor can withstand.
In a second aspect, an embodiment of the present invention further provides a memristor resistance adjusting and controlling device, where the memristor is connected to a transistor, a pulse amplitude applied to the memristor is constant, and a gate voltage is applied to a gate of the transistor; the device includes:
the first determining module is used for determining a first resistance value of the memristor to be regulated, and if the first resistance value is larger than a preset threshold value, the electroforming module is executed;
an electroforming module to perform electroforming on the memristor based on the pulse and the gate voltage; the electroforming is used for opening a conductive channel of the memristor;
the judging module is used for judging whether the electroforming is successful, and if the electroforming is successful, the second determining module is executed;
the second determining module is used for determining a second resistance value of the memristor, and if the second resistance value is outside a preset target resistance value area, the modulating module is executed;
a modulation module to perform resistance modulation on the memristor based on the pulse and the gate voltage;
the third determining module is used for determining a third resistance value of the memristor after the resistance value is modulated, and if the third resistance value is in the target resistance value area, the verifying module is executed;
and the verification module is used for verifying the resistance of the memristor, and if the resistance verification is successful, the resistance regulation and control of the memristor are completed.
In a third aspect, an embodiment of the present invention further provides a computer terminal, where the computer terminal includes a processor and a memory; the memory is stored with a program, and the processor executes the memristor resistance regulating and controlling method when running the program.
In a fourth aspect, the embodiment of the present invention further provides a storage medium, where a computer program is stored in the storage medium, and the computer program executes the memristor resistance adjusting and controlling method when running.
Compared with the prior art, the invention has the following technical effects:
according to the method, the effect of gradually approaching the resistance of the memristor to the target resistance is achieved through grid voltage adjustment, rapid and accurate writing of the resistance can be achieved, the retention time of the device is greatly prolonged, an engineering solution is provided for achieving integration of brain calculation and memory calculation of the memristor, and the progress of product application of the memristor is greatly promoted.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
FIG. 1 illustrates a structural schematic of a memristor;
FIG. 2 shows a flow chart diagram of a memristor resistance regulation method provided by an embodiment of the present invention;
FIG. 3 is a schematic flow chart illustrating a specific memristor resistance regulation method according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a computer terminal according to an embodiment of the present invention;
FIG. 5 shows a schematic structural diagram of a memristor resistance regulation device according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a frame structure of a storage medium according to an embodiment of the present invention.
Icon: 1-memristor; 11-positive electrode; 12-a negative electrode; 2-a transistor; 21-a drain electrode; 22-a gate; 23-a source electrode; 201-a processor; 202-a memory; 301-a first determination module; 302-electroforming mold; 303-a judgment module; 304-a second determination module; 305-a modulation module; 306-a third determination module; 307-check module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Example 1
The embodiment 1 of the invention discloses a memristor resistance value regulation and control method, wherein a memristor to be regulated and controlled is shown as a part surrounded by a dotted line frame in fig. 1, and the fig. 1 comprises a memristor array formed by a plurality of memristors 1 and a plurality of transistors 2; for each memristor 1, in one embodiment, the cathode 12 of the memristor 1 is connected with the drain 21 of the transistor 2, the source 23 of the transistor 2 is grounded, the amplitude of the pulse applied to the anode 11 of the memristor 1 is constant, and the gate voltage is applied to the gate 22 of the transistor 2; in the memristor array, the positive electrode 11 of each memristor 1 may be connected by a row control line, the gate 22 of each transistor 2 may be connected by a gate control line, and the source 23 of each transistor 2 may be connected by a column control line. In addition, the amplitude of the pulse is the maximum voltage amplitude that the memristor can bear, that is, the voltage amplitude of the pulse applied on the row control line is the maximum positive and negative voltage values that can be applied (the corresponding pulse includes a positive pulse and a negative pulse), for example, the maximum positive voltage value may be 4.8V, and the maximum negative voltage value is-4.8V; therefore, the grid voltage in the modulation stage can be reduced as much as possible, and the device on the same column line can be prevented from being adjusted by mistake.
In an actual scheme, when a certain memristor 1 (such as a portion enclosed by a dashed line frame in fig. 1) needs to perform resistance adjustment, the positive electrode 11 of the memristor 1 is connected with a row control line to apply a pulse with a constant voltage amplitude (the specific voltage amplitude is V in fig. 1) through the row control linep) (ii) a The gate 22 of the transistor 2 to which the memristor 1 is connected to a gate control line to apply a gate voltage (e.g., V in FIG. 1) through the gate control lineg) As for the source 23 of the transistor 2 to which this memristor 1 is connected, a column control line is connected to realize grounding based on the column control line. The aim of regulating and controlling the resistance of the memristor is to regulate the resistance of the memristor to a target resistance, a certain error can be allowed when the resistance of the memristor is specifically regulated to the target resistance, for example, the error can be plus or minus 5%, and therefore a target resistance area is generated based on the target resistance and the allowed error; the memristor can have different errors based on different product types and different practical application scenarios.
When a certain memristor 1 (as shown in fig. 1, the part not surrounded by the dashed line frame) does not need to perform resistance adjustment, the control row control line is disconnected from the positive electrode 11 of the memristor 1, that is, floating is performed, and meanwhile, the gate 22 and the source 23 of the transistor 2 connected to the memristor 1 are grounded through the gate control line and the column control line, respectively.
As shown in fig. 2 or fig. 3, a flow chart of a memristor resistance adjusting and controlling method provided by the present invention is provided, wherein the method includes:
specifically, the resistance of the memristor may be obtained by converting a current measured by an ADC (Analog-to-Digital Converter), and the obtained resistance is set as the first resistance.
After the first resistance value is determined, different operations need to be performed according to the magnitude of the first resistance value, specifically:
(1) if the first resistance value is smaller than the preset value, determining that the memristor is damaged, and executing an ending process; the preset value is smaller than the minimum resistance value in the target resistance value region. Specifically, the preset value may be set to 3K ohms, for example, so that the resistance range of the first resistance value is between 0K ohms and 3K ohms, and if it is determined that the memristor is damaged, the regulation process is directly exited.
(2) If the first resistance value is within the target resistance value region, step 7 is executed. Specifically, if the first resistance value is within the target resistance value region, it is indicated that the initial resistance value of the memristor is very close to the target resistance value, and the resistance value calibration stage corresponding to the subsequent step 7 can be directly entered without excessive adjustment.
(3) And if the first resistance value is outside the target resistance value area, the first resistance value is larger than a preset value, and the first resistance value is smaller than a preset threshold value, executing the step 5. Specifically, the first resistance value is outside the target resistance value area, the first resistance value is larger than a preset value, it is indicated that the memristor is damaged or not, and the further first resistance value is smaller than a preset threshold value, it is indicated that a certain difference exists between the first resistance value and the target resistance value, but the difference is not large, and the subsequent resistance value modulation stage can be directly entered to finely adjust the resistance value.
In addition to the above 3 cases, there is also (4) a case, if the first resistance value is greater than the preset threshold value, the specific preset threshold value may be, for example, 1M ohm; executing the step 2; the case (4) illustrates that there is a large difference between the first resistance and the target resistance, and the electroforming is performed first to perform coarse adjustment on the resistance so as to make the resistance closer to the target resistance, specifically, step 2 is performed.
the step 2 specifically comprises the following steps:
and 23, electroforming the memristor based on the pulse and the adjusted gate voltage.
Specifically, a target resistance value of the memristor is determined, then the gate voltage is adjusted according to the target resistance value of the memristor, and the larger the target resistance value is, the smaller the adjusted gate voltage is; in practical applications, for example, the resistance value is divided into a plurality of regions from large to small (or from small to large), and each region can be divided into a gear 1, a gear 2 and a gear 3 for one gear, for example, the gears can be divided into the gear from small to large; if the target resistance value is in the range of the gear 1, the grid voltage after adjustment is maximum; if the target resistance value is within the range of the gear 2, the grid voltage can be slightly reduced; and if the target resistance value is in the range of the gear 3, the grid voltage after adjustment is minimum. After the grid voltage is adjusted, electroforming is carried out on the memristor in combination with the pulse positioned at the anode of the memristor.
after each electroforming, whether the electroforming is successful or not is judged; whether electroforming is successful or not can be judged according to the resistance value change of the memristor before and after electroforming; if the resistance value changes to a certain degree, the resistance value is closer to the target resistance value, for example, the resistance value before electroforming is larger than a preset threshold value, and the resistance value after electroforming is smaller than the preset threshold value, the electroforming is successful, otherwise, if the resistance value is still larger than the preset threshold value after electroforming, the electroforming is unsuccessful.
If the electroforming is not successful, the grid voltage is increased; electroforming is carried out on the memristor through the pulse and the heightened gate voltage, and step 3 is carried out to judge whether the electroforming is successful.
Further, the method further comprises: recording the number of times of unsuccessful electroforming; and if the unsuccessful times exceed the set upper limit value, executing the ending process. Specifically, if the number of times of performing electroforming exceeds a set upper limit value (which may be set empirically), it indicates that the memristor is in poor contact, and the control process for the memristor is finished.
if the electroforming is successful, the resistance of the memristor at the moment is obtained, and the resistance at the moment is set as a second resistance.
After the second resistance value is determined, different operations are required to be executed according to the size of the second resistance value, specifically, due to the fact that electroforming is successful, the second resistance value of the memristor is closer to the target resistance value region than the first resistance value, specifically, after the electroforming process of the step 2 is performed, and after electroforming is successful, the obtained second resistance value has two conditions, wherein the first resistance value is in the target resistance value region; the second is outside the target resistance value area;
therefore, when the second resistance value corresponds to the first condition, that is, the second resistance value is within the target resistance value region, step 7 is executed. Specifically, if the second resistance value is within the target resistance value region, it indicates that the current resistance value of the memristor is very close to the target resistance value, and the resistance value calibration stage corresponding to the subsequent step 7 can be directly entered without excessive adjustment.
If the second resistance value corresponds to the second condition, go to step 5.
specifically, the pulses include: positive and negative pulses; the step 5 comprises the following steps:
step 51, selecting a pulse width based on the second resistance value; the larger the second resistance value is, the smaller the selected pulse width is;
specifically, the second resistance value is outside the target resistance value region, and based on the foregoing electroforming stage, the resistance value of the memristor at this time is already relatively close to the target resistance value, and is not suitable for performing a coarse tuning manner such as electroforming, and a fine tuning manner such as resistance value modulation is required, and specifically, the difference between the coarse tuning and the fine tuning lies in that the magnitude of the resistance value is changed during tuning; coarse tuning changes a greater resistance value than fine tuning.
When the resistance value modulation is carried out, firstly, the pulse width is selected based on a second resistance value (namely the actual resistance value of the memristor at the moment), and the larger the second resistance value is, the smaller the selected pulse width is; still, the above-mentioned gear is used for explanation, for example, the second resistance value is located in the resistance value interval corresponding to the gear 1, and since the resistance value in the gear 1 is the minimum, the selected pulse width is the maximum; if the second resistance value is located in the resistance value interval corresponding to the gear 2, the selected pulse width is centered; if the second resistance value is within the resistance value interval corresponding to the gear 3, the selected pulse width is the minimum.
Step 52, respectively initializing the grid voltage according to the Set direction and the Reset direction to obtain the Set grid voltage and the Reset grid voltage; the Set grid voltage is less than the Reset grid voltage;
specifically, the gate voltage in the Set direction is used to lower the resistance value, and the gate voltage in the Reset direction is used to raise the resistance value.
After initializing the gate voltage, there are different processing manners according to the magnitude relationship between the second resistance value and the target resistance value, as shown in the following steps 53 and 54.
Step 53, if the second resistance value is smaller than the target resistance value of the memristor, calling Reset gate voltage, and selecting a negative pulse to apply a group of pulses (a specific group of pulses may include a plurality of pulses) at a preset time interval according to the selected pulse width; specifically, if the second resistance value is smaller than the target resistance value, the Reset gate voltage V is calledg_resetSelecting the negative pulse according to the selected pulse width TpA set of pulses is applied at preset time intervals.
Step 54, if the second resistance value is larger than the target resistance value, calling Set gate voltage, and selecting a positive pulse to apply a group of pulses at a preset time interval according to the selected pulse width; specifically, if the second resistance value is greater than the target resistance value, the Set gate voltage V is calledg_setSelecting a positive pulse (e.g. V)p4.8V) according to the selected pulse width TpA set of pulses is applied at preset time intervals.
Step 55, recording the resistance value of the memristor after each pulse application, and setting the recorded resistance value as a second resistance value to execute step 53 or step 54;
specifically, after each pulse is applied (i.e., one step 54 or step 55 is performed), the resistance of the memristor is recorded, the recorded resistance is set to the second resistance, and step 54 or step 55 is repeated.
And 56, if the preset number of resistance values are obtained and the current latest resistance value is in the target resistance value area, completing resistance value modulation of the memristor.
Specifically, for example, the number of times of executing step 54 or step 55 is 3, and the resistance value of the memristor is also recorded 3 times, for example, the latest obtained resistance value is labeled as Rread2And R isread0It refers to the resistance value read after the last pulse application. Judgment of Rread2And if the memristor is located in the target resistance value region, completing resistance value modulation of the memristor, and subsequently entering step 6 to perform resistance value verification.
If the current latest resistance value is outside the target resistance value area, judging whether the latest applied pulse causes the change of the magnitude relation between the current latest resistance value and the target resistance value;
specifically, the current latest resistance value is related to the target resistance value based on the formula:
is represented by (A) wherein R isread1The current new resistance value (i.e. the current second new resistance value); rt arg etIndicating a target resistance value; when the XOR result of the formulas is 1, the size relationship is changed; when the exclusive or result of the formula is 0, it indicates that the magnitude relationship has not changed.
If it is determined that the latest pulse causes a change in the magnitude relationship between the current latest resistance value and the target resistance value, step 53 or step 54 is performed based on the initial Set gate voltage and the initial Reset gate voltage. If the magnitude relation changes, it indicates that the resistance value modulation is excessive, and the resistance value modulation needs to be performed again based on the initial Set gate voltage and the initial Reset gate voltage.
If the resistance value is judged to be unchanged, judging whether the maximum difference value of any two resistance values in the preset number of resistance values is larger than the product of the current latest resistance value and the preset percentage; the larger the current latest resistance value is, the smaller the corresponding preset percentage is;
specifically, when the magnitude relationship is not changed, it indicates that the next pulse application direction is not changed, and it needs to determine { R }read0,Rread1,Rread2Whether the maximum difference between any two resistance values exceeds the current latest resistance value percentage is set according to the gear interval in which the current latest resistance value is located, which is also described by way of example, for example, the percentage corresponding to gear 1 is 6%, the percentage corresponding to gear 2 is 5%, and the percentage corresponding to gear 3 is 4%.
If yes, keeping the current Set grid voltage and the current Reset grid voltage to execute step 53 or step 54; when the maximum difference value exceeds a certain percentage of the current latest resistance value, the internal state of the memristor is effectively changed by the pulse application, and the grid voltage value does not need to be adjusted by the next pulse application.
If the result is negative, the Set gate voltage and Reset gate voltage are increased to execute step 53 or step 54. When the maximum difference value does not exceed a certain percentage of the current latest resistance value, the internal state of the memristor cannot be effectively changed by the pulse application, and the grid voltage value needs to be increased by the next pulse application.
Further, increasing the Set gate voltage and the Reset gate voltage includes:
increasing Set grid voltage in a mode of increasing a first added value every time;
increasing Reset grid voltage by increasing a second increasing value each time;
wherein the first increment value is less than the second increment value; the smaller the difference between the current latest resistance value and the target resistance value is, the smaller the first incremental value and the second incremental value are.
Specifically, the increased value of the gate voltage is different according to the modulation direction and the current resistance range. An example is described, for example, the current latest resistance value is out of the range of ± 20% of the target resistance value, which means that the current adjustment margin is large, so that the second increment in Reset direction is Set to 0.1V, and the first increment in Set direction is Set to 0.02V; when the target resistance value is within +/-20%, the current adjustment margin is small, the increment value is reduced to avoid over modulation, the second increment value in the Reset direction is changed into 0.02V, and the first increment value in the Set direction is changed into 0.01V.
Furthermore, both the Set grid voltage and the Reset grid voltage are provided with upper limit values, and the upper limit value of the Set grid voltage is smaller than the upper limit value of the Reset grid voltage. For example, the upper limit value of Reset grid voltage and the upper limit value of Set grid voltage are respectively 4V and 2.5V, so that the situation that the grid voltage is infinitely increased and the frequency of resistance value modulation is controlled is avoided, and when the frequency of resistance value modulation reaches the preset frequency, the memristor is stopped to be regulated.
After the resistance value modulation is completed, step 6 is executed.
specifically, if the third resistance value is within the target resistance value region, step 7 is executed.
And 7, verifying the resistance of the memristor, and if the resistance verification is successful, finishing the resistance regulation and control of the memristor.
Specifically, a plurality of third resistance values are obtained in step 6, and step 7 includes:
step 71, judging whether each third resistance value is in the target resistance value area, and whether the maximum difference value of any two third resistance values in the plurality of third resistance values is smaller than the product of the target resistance value of the memristor and a preset proportion; the larger the target resistance value is, the smaller the corresponding preset proportion is;
and step 72, if the judgment results are yes, determining that the resistance value verification is passed.
Continuing to explain by taking the example of obtaining the third resistance value for 5 times as an example, when the third resistance values obtained for 5 times are all within the target resistance value region, and meanwhile, the maximum difference value of any two third resistance values in the third resistance values obtained for 5 times is lower than the product of the target resistance value and a certain proportion (for example, when the target resistance value is in the gear 1, the corresponding percentage is 6%, the corresponding percentage is 5% in the gear 2, and the corresponding percentage is 4% in the gear 3), the resistance value verification is considered to be passed, and the resistance value regulation of the memristor is completed.
And if the judgment results are not yes, executing the step 5.
Taking the example of obtaining the third resistance value for 5 times as an example, if the third resistance values obtained for 5 times are not within the target resistance value region, or the maximum difference value of any two third resistance values in the third resistance values obtained for 5 times is not lower than the product of the target resistance value and a certain proportion, the third resistance value most deviated from the target resistance value in the third resistance values obtained for 5 times is taken as the current actual resistance value of the memristor, and the resistance value modulation operation is performed again.
Example 2
The embodiment 2 of the present invention further discloses a computer terminal, which comprises a processor 201 and a memory 202; as shown in fig. 4, a program is stored in the memory 202, and the processor 201 executes the memristor resistance adjusting and controlling method in embodiment 1 when running the program.
Example 3
The embodiment 3 of the invention further discloses a memristor resistance value regulating and controlling device, which can be applied to the computer terminal in the embodiment 2 and can be used for executing or realizing the steps in the method. The memristor resistance regulating device may include at least one software functional module which may be stored in the memory 202 in the form of software or Firmware (Firmware) or solidified in an Operating System (OS) of the computer terminal. The processor 201 is configured to execute executable modules stored in the memory 202, such as software functional modules and computer programs included in the memristor resistance adjusting device. Specifically, as shown in fig. 5, the memristor resistance regulating device may include the following modules:
a first determining module 301, configured to determine a first resistance value of the memristor to be controlled, and if the first resistance value is greater than a preset threshold, execute an electroforming module 302;
an electroforming module 302 to perform electroforming on the memristor based on the pulse and the gate voltage; electroforming a conductive channel for opening the memristor;
a judging module 303, configured to judge whether electroforming is successful, and if electroforming is successful, execute a second determining module 304;
a second determining module 304, configured to determine a second resistance value of the memristor, and if the second resistance value is outside the preset target resistance value region, execute the modulating module 305;
a modulation module 305 to perform resistance modulation on the memristor based on the pulse and the gate voltage;
a third determining module 306, configured to determine a third resistance value of the memristor after the resistance value modulation, and if the third resistance value is within the target resistance value region, execute the verifying module 307;
the verification module 307 is configured to perform resistance verification on the memristor, and if the resistance verification is successful, the resistance regulation and control on the memristor are completed.
An electroforming module 302 to:
and 23, electroforming the memristor based on the pulse and the adjusted gate voltage.
The first determining module 301 is further configured to:
if the first resistance value is smaller than the preset value, determining that the memristor is damaged, and executing an ending process; the preset value is smaller than the minimum resistance value in the target resistance value region.
The first determining module 301 is further configured to:
if the first resistance value is within the target resistance value region, a verification block 307 is executed.
The first determining module 301 is further configured to:
if the first resistance value is outside the target resistance value area, the first resistance value is greater than the preset value, and the first resistance value is smaller than the preset threshold, the modulation module 305 is executed.
The determining module 303 is further configured to:
if the electroforming is not successful, the grid voltage is increased;
electroforming is performed on the memristor through the pulse and the gate voltage after the increase, and a judgment module 303 is performed.
The determining module 303 is further configured to:
recording the number of times of unsuccessful electroforming;
and if the unsuccessful times exceed the set upper limit value, executing the ending process.
The second determining module 304 is further configured to:
if the second resistance value is within the target resistance value region, the verification block 307 is executed.
The pulses include: positive and negative pulses;
a modulation module 305 for performing the steps of:
step 51, selecting a pulse width based on the second resistance value; the larger the second resistance value is, the smaller the selected pulse width is;
step 52, respectively initializing the grid voltage according to the Set direction and the Reset direction to obtain the Set grid voltage and the Reset grid voltage; the Set grid voltage is less than the Reset grid voltage;
step 53, if the second resistance value is smaller than the target resistance value of the memristor, calling Reset grid voltage, and selecting a negative pulse to apply a group of pulses at a preset time interval according to the selected pulse width;
step 54, if the second resistance value is larger than the target resistance value, calling Set gate voltage, and selecting a positive pulse to apply a group of pulses at a preset time interval according to the selected pulse width;
step 55, recording the resistance value of the memristor after each pulse application, and setting the recorded resistance value as a second resistance value to execute step 53 or step 54;
and 56, if the preset number of resistance values are obtained and the current latest resistance value is in the target resistance value area, completing resistance value modulation of the memristor.
A modulation module 305, further configured to:
if the current latest resistance value is outside the target resistance value area, judging whether the latest applied pulse causes the change of the magnitude relation between the current latest resistance value and the target resistance value;
if the determination is changed, executing step 53 or step 54 based on the initial Set gate voltage and the initial Reset gate voltage;
if the resistance value is judged to be unchanged, judging whether the maximum difference value of any two resistance values in the preset number of resistance values is larger than the product of the current latest resistance value and the preset percentage; the larger the current latest resistance value is, the smaller the corresponding preset percentage is;
if yes, keeping the current Set grid voltage and the current Reset grid voltage to execute step 53 or step 54;
if the result is negative, the Set gate voltage and Reset gate voltage are increased to execute step 53 or step 54.
Specifically, increasing the Set gate voltage and the Reset gate voltage includes:
increasing Set grid voltage in a mode of increasing a first added value every time;
increasing Reset grid voltage by increasing a second increasing value each time;
wherein the first increment value is less than the second increment value; the smaller the difference between the current latest resistance value and the target resistance value is, the smaller the first incremental value and the second incremental value are.
Furthermore, both the Set grid voltage and the Reset grid voltage are provided with upper limit values, and the upper limit value of the Set grid voltage is smaller than the upper limit value of the Reset grid voltage.
A third determining module 306, configured to perform the following steps:
continuously reading the third resistance values of the memristor for multiple times after the resistance values are modulated to obtain multiple third resistance values, and if each third resistance value is in the target resistance value area, executing the step 7;
a checking module 307, configured to perform the following steps:
step 71, judging whether the maximum difference value of any two third resistance values in the plurality of third resistance values is smaller than the product of the target resistance value of the memristor and a preset proportion; the larger the target resistance value is, the smaller the corresponding preset proportion is;
and step 72, if the judgment result is yes, determining that the resistance value verification is passed.
The checking module 307 is further configured to select a third resistance value with the maximum deviation from the target resistance value as the second resistance value if the determination result is not yes, so as to execute the modulating module 305.
Further, the amplitude of the pulse is the maximum voltage amplitude that the memristor can withstand.
Example 4
The embodiment 4 of the invention further discloses a storage medium, as shown in fig. 6, a computer program is stored in the storage medium, and the memristor resistance adjusting and controlling method described in embodiment 1 is executed when the computer program runs.
According to the scheme, the memristor is electroformed and modulated by the grid voltage and the pulse, the effect that the resistance value of the memristor gradually approaches the target resistance value is achieved, the rapid and accurate writing of the resistance value can be achieved, the holding time of a device is greatly prolonged, an engineering solution is provided for achieving the integration of brain calculation and memory calculation of the memristor, and the process of product application of the memristor is greatly promoted.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.
Claims (18)
1. The memristor resistance value regulation and control method is characterized in that the memristor is connected with a transistor, the pulse amplitude applied to the memristor is constant, and the grid voltage is applied to the grid electrode of the transistor; the method comprises the following steps:
step 1, determining a first resistance value of the memristor to be regulated, and executing step 2 if the first resistance value is larger than a preset threshold value;
step 2, performing electroforming on the memristor based on the pulse and the gate voltage; the electroforming is used for opening a conductive channel of the memristor;
step 3, judging whether the electroforming is successful, and if the electroforming is successful, executing step 4;
step 4, determining a second resistance value of the memristor, and if the second resistance value is outside a preset target resistance value region, executing step 5;
step 5, performing resistance value modulation on the memristor based on the pulse and the grid voltage;
step 6, determining a third resistance value of the memristor after the resistance value is modulated, and if the third resistance value is in the target resistance value area, executing step 7;
and 7, carrying out resistance value verification on the memristor, and finishing resistance value regulation and control on the memristor if the resistance value verification is successful.
2. The method of claim 1, wherein the step 2 comprises:
step 21, determining a target resistance value of the memristor;
step 22, adjusting the grid voltage according to the target resistance value; the larger the target resistance value is, the smaller the adjusted grid voltage is;
step 23, electroforming the memristor based on the pulse and the adjusted gate voltage.
3. The method of claim 1, further comprising:
if the first resistance value is smaller than a preset value, determining that the memristor is damaged, and executing an ending process; the preset value is smaller than the minimum resistance value in the target resistance value region.
4. The method of claim 1, further comprising:
and if the first resistance value is within the target resistance value area, executing step 7.
5. The method of claim 4, further comprising:
and if the first resistance value is outside the target resistance value area, the first resistance value is larger than the preset value, and the first resistance value is smaller than the preset threshold value, executing the step 5.
6. The method of claim 1, further comprising:
if the electroforming is not successful, the grid voltage is increased;
and (3) performing electroforming on the memristor through the pulse and the grid voltage after being increased, and performing step 3.
7. The method of claim 6, further comprising:
recording the number of unsuccessful times of performing the electroforming;
and if the unsuccessful times exceed the set upper limit value, executing the ending process.
8. The method of claim 1, further comprising:
and if the second resistance value is within the target resistance value area, executing step 7.
9. The method of claim 1, wherein the pulsing comprises: positive and negative pulses;
the step 5 comprises the following steps:
step 51, selecting a pulse width based on the second resistance value; the larger the second resistance value is, the smaller the selected pulse width is;
step 52, initializing the grid voltage according to the Set direction and the Reset direction respectively to obtain the Set grid voltage and the Reset grid voltage; the Set grid voltage is less than the Reset grid voltage;
step 53, if the second resistance value is smaller than the target resistance value of the memristor, calling the Reset gate voltage, and selecting the negative pulse to apply a group of pulses at preset time intervals according to the selected pulse width;
step 54, if the second resistance value is larger than the target resistance value, calling the Set gate voltage, and selecting the positive pulse to apply a group of pulses at the preset time interval according to the selected pulse width;
step 55, recording the resistance value of the memristor after each pulse application, and setting the recorded resistance value to be the second resistance value, so as to execute step 53 or step 54;
and 56, if the preset number of resistance values are obtained and the current latest resistance value is in the target resistance value area, completing resistance value modulation of the memristor.
10. The method of claim 9, further comprising:
if the current latest resistance value is outside the target resistance value area, judging whether the latest pulse causes the change of the magnitude relation between the current latest resistance value and the target resistance value;
if the determination is changed, executing step 53 or step 54 based on the initial Set gate voltage and the initial Reset gate voltage;
if the resistance value is judged to be unchanged, judging whether the maximum difference value of any two resistance values in the preset number of resistance values is larger than the product of the latest current resistance value and a preset percentage; the larger the current latest resistance value is, the smaller the corresponding preset percentage is;
if yes, keeping the current Set grid voltage and the current Reset grid voltage to execute step 53 or step 54;
if the result of the determination is negative, increasing the Set gate voltage and the Reset gate voltage to execute step 53 or step 54.
11. The method of claim 10, wherein increasing the Set gate voltage and the Reset gate voltage comprises:
increasing the Set gate voltage in a manner of increasing a first increase value each time;
increasing the Reset gate voltage by increasing a second increment value each time;
wherein the first increment value is less than the second increment value; the smaller the difference between the current latest resistance value and the target resistance value is, the smaller the first increment value and the second increment value are.
12. The method of claim 10 or 11, wherein the Set gate voltage and the Reset gate voltage are both provided with an upper limit value, and the upper limit value of the Set gate voltage is smaller than the upper limit value of the Reset gate voltage.
13. The method of claim 1, wherein the step 6 comprises:
continuously reading a third resistance value of the memristor for multiple times after the resistance value is modulated to obtain multiple third resistance values, and executing step 7 if the newly obtained third resistance value is in the target resistance value region;
the step 7 comprises the following steps:
step 71, judging whether each third resistance value is in the target resistance value region, and whether the maximum difference value of any two third resistance values in the plurality of third resistance values is smaller than the product of the target resistance value of the memristor and a preset proportion; the larger the target resistance value is, the smaller the corresponding preset proportion is;
and step 72, if the judgment results are yes, determining that the resistance value verification is passed.
14. The method according to claim 13, wherein if the determination results in not all yes, selecting the third resistance value deviating from the target resistance value to be the maximum as the second resistance value to perform step 5.
15. The method of claim 1, in which a magnitude of the pulse is a maximum voltage magnitude that the memristor can withstand.
16. The memristor resistance value regulating and controlling device is characterized in that the memristor is connected with a transistor, the amplitude of a pulse applied to the memristor is constant, and a gate voltage is applied to the gate of the transistor; the device includes:
the first determining module is used for determining a first resistance value of the memristor to be regulated, and if the first resistance value is larger than a preset threshold value, the electroforming module is executed;
an electroforming module to perform electroforming on the memristor based on the pulse and the gate voltage; the electroforming is used for opening a conductive channel of the memristor;
the judging module is used for judging whether the electroforming is successful, and if the electroforming is successful, the second determining module is executed;
the second determining module is used for determining a second resistance value of the memristor, and if the second resistance value is outside a preset target resistance value area, the modulating module is executed;
a modulation module to perform resistance modulation on the memristor based on the pulse and the gate voltage;
the third determining module is used for determining a third resistance value of the memristor after the resistance value is modulated, and if the third resistance value is in the target resistance value area, the verifying module is executed;
and the verification module is used for verifying the resistance of the memristor, and if the resistance verification is successful, the resistance regulation and control of the memristor are completed.
17. A computer terminal is characterized in that the computer terminal comprises a processor and a memory; the memory stores a program, and the processor executes the program to perform the memristor resistance adjusting and controlling method according to any one of claims 1 to 15.
18. A storage medium, wherein a computer program is stored in the storage medium, and when the computer program runs, the method for adjusting and controlling the resistance of the memristor according to any one of claims 1 to 15 is performed.
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