CN112731778B - Control method for semiconductor alignment precision and laminated mark - Google Patents
Control method for semiconductor alignment precision and laminated mark Download PDFInfo
- Publication number
- CN112731778B CN112731778B CN201911032221.6A CN201911032221A CN112731778B CN 112731778 B CN112731778 B CN 112731778B CN 201911032221 A CN201911032221 A CN 201911032221A CN 112731778 B CN112731778 B CN 112731778B
- Authority
- CN
- China
- Prior art keywords
- overlay
- mark
- main
- value
- auxiliary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/708—Mark formation
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Abstract
The invention discloses a control method of semiconductor alignment precision, which comprises the steps of obtaining a main measurement value according to a main alignment laminated mark; acquiring an auxiliary measurement value according to the auxiliary overlay lamination mark; and carrying out overlay compensation based on the main measurement value and the auxiliary measurement value. In addition, a semiconductor overlay stack mark is also disclosed. The method improves the precision of the semiconductor alignment.
Description
Technical Field
The present invention relates to semiconductor manufacturing processes, and more particularly, to a method for controlling alignment precision of a semiconductor and a stack mark.
Background
With the continuous development of electronic technology, the process size of semiconductor manufacturing is smaller and smaller, and the requirement on the precision of semiconductor manufacturing is higher and higher. At present, in a small-sized process, in order to ensure that the overlay lamination mark can truly reflect the overlay alignment behavior in the chip, the overlay lamination mark is designed as the pattern in the chip. However, the quality of the overlay mark is often affected by the subsequent processes, which results in erroneous or inaccurate measurement results and hinders the quality control of the process.
Disclosure of Invention
The present invention is directed to a method for controlling the overlay accuracy of a semiconductor device and a stack mark, so as to solve the problems mentioned in the background art.
In order to achieve the above object, the present invention provides a method for controlling semiconductor alignment precision, the method comprising:
acquiring a main measurement value according to the main overlay lamination mark;
acquiring an auxiliary measurement value according to the auxiliary overlay lamination mark;
and carrying out overlay compensation based on the main measurement value and the auxiliary measurement value.
According to the technical scheme, the auxiliary overlay laminated mark is further arranged on the basis of the main overlay laminated mark, and when the main overlay laminated mark deviates, compensation is carried out through the auxiliary measurement mark, so that the measurement precision is improved.
Preferably, the main overlay laminated mark includes an abnormal main overlay laminated mark, and it is determined whether the main overlay laminated mark is the abnormal main overlay laminated mark according to a comparison result between the main measurement value and a preset threshold value. The measurement precision is improved.
Preferably, the step of determining whether the primary overlay mark is an abnormal primary overlay mark according to the comparison result between the primary measurement value and a preset threshold value includes:
the primary measurement value comprises an offset value and/or a Q-Merit value;
and judging that the main overlay laminated mark is the abnormal main overlay laminated mark when the deviation value and/or the Q-Merit value is larger than the preset threshold value.
Preferably, the step of performing overlay compensation based on the main measurement value and the auxiliary measurement value includes:
obtaining an abnormal Q-Merit value of the abnormal main overlay lamination mark;
determining a feedback compensation value according to the abnormal Q-Merit value and the auxiliary measurement value;
and carrying out overlay compensation according to the feedback compensation value.
Preferably, the step of determining a feedback compensation value according to the abnormal Q-Merit value and the auxiliary measurement value further includes:
determining the direction of the abnormal Q-Merit value according to the main measurement value of the abnormal main overlay lamination and the auxiliary measurement value of the auxiliary overlay lamination mark;
the feedback compensation value is the sum of the abnormal Q-Merit value of the belt direction and the auxiliary measuring value.
Preferably, the distance between the primary overlay mark and the secondary overlay mark is less than 5 mm.
Correspondingly, a semiconductor overlay stack mark is also provided, the mark comprising:
a main overlay mark comprising a plurality of main sub-lines extending along a first direction;
the auxiliary overlay laminated mark comprises a plurality of auxiliary sub-lines extending along a second direction;
the first direction is different from the second direction.
According to the technical scheme, the second direction of the extension of the auxiliary sub-lines of the auxiliary overlay laminated mark is different from the first direction of the extension of the main lines of the main overlay laminated mark, so that the sensitivity of the auxiliary overlay laminated mark to a manufacturing process is reduced.
Preferably, the Pitch of the auxiliary sub-bar is greater than the Pitch of the main sub-bar. The larger auxiliary sub-line pitch in the technical scheme further increases the redundancy of the auxiliary lamination overlay mark on the process difference.
Preferably, the Pitch of the subsidiary sub-line is 2-5 times the Pitch of the main sub-line. The redundancy of the auxiliary lamination overlay mark to the process technology difference is increased.
Preferably, the main overlay lamination mark includes a main overlay lamination abnormal mark, and the main overlay lamination abnormal mark is distributed in a partial area on the wafer.
Preferably, the distance between the primary overlay mark and the secondary overlay mark is less than 5 mm. The influence of the placement positions of the main overlay laminated mark and the auxiliary overlay laminated mark on the measurement result is eliminated.
Preferably, the first direction is the same as the extending direction of the main pattern in the chip.
According to the embodiment of the invention, the auxiliary overlay laminated mark is placed near the main overlay laminated mark, and when the main overlay laminated mark is abnormal, the measurement value of the auxiliary overlay laminated mark is used for correction, so that the control accuracy of the overlay process is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1a is a schematic diagram of an embodiment of a main overlay mark of a semiconductor overlay mark according to the present invention.
FIG. 1b is a schematic diagram of an embodiment of an alignment overlay mark assisted by a semiconductor alignment overlay mark according to the present invention.
Fig. 2a is a schematic cross-sectional view of a main overlay stack anomaly mark of a semiconductor overlay stack mark of the present invention taken along a direction perpendicular to a first direction.
Fig. 2b is a schematic cross-sectional view of a main overlay stack normal mark of a semiconductor overlay stack mark of the present invention taken perpendicular to a first direction.
Fig. 3 is a flowchart illustrating a method for controlling the alignment precision of a semiconductor device according to a first embodiment of the present invention.
Fig. 4 is a flowchart illustrating a method for controlling the alignment precision of a semiconductor device according to a second embodiment of the present invention.
Detailed Description
The following describes embodiments of the present invention in detail with reference to the accompanying drawings.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1a-1b, the overlay stack mark includes a primary overlay stack mark and a secondary overlay stack mark.
As an example, the main overlay stack mark and the auxiliary overlay stack mark may be formed in a layer of the semiconductor substrate or an epitaxial layer thereof, and specifically, the main overlay stack mark and the auxiliary overlay stack mark may be disposed on the wafer scribe line, and in order to eliminate an influence of the placement positions of the main overlay stack mark and the auxiliary overlay stack mark on the measurement result, the auxiliary overlay stack mark should be disposed near the main overlay stack mark, for example, the distance between the main overlay stack mark and the auxiliary overlay stack mark is less than 1mm or 5 mm.
As an example, the main overlay mark and the auxiliary overlay mark are placed in pairs on the dicing streets. A plurality of pairs of main overlay engraving lamination marks and auxiliary overlay engraving lamination marks can be placed on a single shot, specifically, 5 pairs of main overlay engraving lamination marks and auxiliary overlay engraving lamination marks can be placed on the single shot and are respectively positioned at the upper left corner, the upper right corner, the lower left corner, the lower right corner and the middle part of the shot, the requirement for minimum measurement data can be met, the feedback effect can be improved as far as possible, and the measurement time and the machine time can be saved. In addition, the main overlay mark and the auxiliary overlay mark can be placed on a cutting channel between die and die in the shot in pairs, so that the number of the overlay marks is increased, and the accuracy of overlay compensation is improved.
As an example, as shown in fig. 1a, the main overlay stack mark includes a plurality of main sub-lines 101 extending in a first direction, and as shown in fig. 1b, the auxiliary overlay stack mark includes a plurality of auxiliary sub-lines 201 extending in a second direction, the first direction being different from the second direction. Specifically, the first direction is diagonal, and the second direction is along the horizontal direction or the vertical direction. The second direction is different from the first direction, so that the sensitivity of the auxiliary overlay lamination mark to the process technology is reduced.
As an example, the distance (Pitch) between the auxiliary sub-bars 201 is greater than the Pitch of the main sub-bar 101. Specifically, the Pitch of the auxiliary sub-bar 201 is 2-5 times, such as 2.5 times, 3 times, etc., the Pitch of the main sub-bar 101, which is 2 times as large as that of FIG. 1 b. The larger auxiliary sub-line pitch further increases the redundancy of the auxiliary lamination overlay mark to the process technology difference.
As an example, the master overlay stack mark includes a master overlay stack anomaly mark. As shown in fig. 2a-2b, the cross section of the main overlay laminated anomaly mark presents an asymmetric shape, specifically, the cross section of the main overlay laminated anomaly mark may present other anomaly shapes, such as unfilled corner, top collapse, etc., which is not limited herein. The cross-section of the normal mark of the primary overlay stack exhibits a symmetrical shape. The main overlay laminated abnormal mark is distributed on partial area of the wafer. Specifically, the factors causing the abnormality of the main overlay lamination mark are often related to the process, for example, the etching deviation of the middle and edge of the wafer may cause the abnormality of the main overlay lamination mark at the edge of the wafer, the main overlay lamination mark at the center of the wafer may be caused by the interval pressure in the chemical mechanical polishing, and the main overlay lamination mark in the local area on the wafer caused by the pattern density difference may be abnormal, so the abnormal main overlay lamination mark may be distributed at any position of the wafer.
As an example, the semiconductor overlay stack mark further includes a main pattern in the chip, and specifically, the main pattern in the die on the wafer may be a line/space of the minimum pitch, an extending direction of the line/space of the minimum pitch is the same as the first direction, and the extending direction of the line/space of the minimum pitch determines an illumination mode of the exposure, that is, the illumination mode is optimized according to the extending direction of the line/space of the minimum pitch. For example, a line/space pattern may be obtained by exposure using a dipole illumination mode, the direction of the dipole being obtained from the direction of extension of the line/space pattern.
Another aspect of the present invention is described below.
Referring to fig. 3, the flowchart of a first embodiment of the method for controlling semiconductor overlay accuracy according to the embodiment of the present invention is shown, where the flowchart includes the following steps:
step s11, obtaining a main measurement value according to the main overlay lamination mark;
step s12, acquiring an auxiliary measurement value according to the auxiliary overlay lamination mark;
and step s13, performing overlay compensation based on the main measurement value and the auxiliary measurement value.
According to the technical scheme, the auxiliary overlay laminated mark is arranged on the basis of the main overlay laminated mark, overlay compensation is carried out through measurement of the auxiliary overlay mark, and the overlay accuracy of the semiconductor is improved.
Referring to fig. 4, the flowchart of a second embodiment of the method for controlling semiconductor overlay accuracy according to the embodiment of the present invention is shown, where the flowchart includes:
step s21, obtaining a main measurement value according to the main overlay laminated mark;
step s22, judging whether the deviation value and/or the Q-Merit value included in the main measurement value is larger than a preset threshold value, if so, judging that the main overlay laminated mark is an abnormal main overlay laminated mark, otherwise, returning to the step s 21;
step s23, obtaining an abnormal Q-Merit value of the abnormal main overlay lamination mark;
step s24, determining a feedback compensation value according to the abnormal Q-Merit value and the auxiliary measurement value; during specific implementation, firstly, determining the direction of an abnormal Q-Merit value according to a main measurement value of an abnormal main overlay lamination and an auxiliary measurement value of an auxiliary overlay lamination mark; then, a feedback compensation value is determined based on the direction of the abnormal Q-Merit value.
As an example, in step s22, the offset value is an OVL value obtained by actually measuring the overlay mark by the machine, the OVL value is divided into an OVL-X direction value and an OVL-Y direction value, and a threshold is preset to determine whether the main overlay mark is an abnormal main overlay mark. In an actual process, when the main overlay laminated mark is an abnormal main overlay laminated mark, the measured value of the OVL is abnormally large, a threshold value of 10nm, 15nm, 20nm and the like can be preset according to the actual process, when the value of the OVL-X direction or the value of the OVL-Y direction of a certain main overlay laminated mark actually measured by a machine station is larger than the threshold value, the main overlay laminated mark can be judged to be the abnormal main overlay laminated mark, and the measured value of the OVL is not credible and cannot be used for overlay feedback. In another example, the Q-score value of the main overlay mark may also be used to determine whether the main overlay mark is abnormal, in the same way as the offset value.
As an example, in step s23, an anomaly Q-Merit value of the anomaly master overlay mark is obtained. Specifically, in step S22, the measurement recipe may measure the offset values and Q-merit values of all the main overlay marks at the same time, and an abnormal Q-merit value of the abnormal main overlay mark needs to be found according to the determination method in step S22, where the abnormal Q-merit value is the Q-merit value of the abnormal main overlay mark determined by the Q-merit value in step S22.
As an example, in step s24, a feedback compensation value is determined based on the abnormal Q-Merit value and the auxiliary measurement value. Specifically, the feedback compensation value is the sum of the abnormal Q-Merit value of the belt direction and the auxiliary measurement value. The abnormal Q-score may be considered to be added when the direction of the main measurement value of the abnormal main overlay mark and the auxiliary measurement value of the auxiliary overlay mark coincide, and subtracted when the direction of the main measurement value of the abnormal main overlay mark and the auxiliary measurement value of the auxiliary overlay mark do not coincide. In another example, the abnormal Q-score value may be considered to be subtracted when the directions of the main measurement value of the abnormal main overlay stack and the auxiliary measurement value of the auxiliary overlay stack mark coincide, and added when the directions of the main measurement value of the abnormal main overlay stack and the auxiliary measurement value of the auxiliary overlay stack mark do not coincide.
As an example, the wafer includes a plurality of pairs of main overlay lamination marks and auxiliary lamination marks, where the main overlay lamination marks include abnormal main overlay lamination marks and normal main overlay lamination marks that are locally distributed on the wafer, and the feedback compensation value of the wafer is obtained by calculating a main measurement value of the normal main overlay lamination marks, an abnormal Q-score value of the abnormal main overlay lamination marks, and an auxiliary measurement value of the auxiliary overlay lamination marks. Specifically, the actual measurement value of the abnormal main overlay laminated mark is obtained by using the abnormal Q-merit value of the abnormal main overlay laminated mark and the auxiliary measurement value of the auxiliary overlay laminated mark, and the feedback compensation value of the wafer is calculated by using the normal main measurement value of the main overlay laminated mark and the actual measurement value of the abnormal main overlay laminated mark.
The foregoing description shows and describes several preferred embodiments of the invention, but as before, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for controlling the alignment precision of a semiconductor is characterized by comprising the following steps:
acquiring a main measurement value according to the main overlay lamination mark; the main overlay laminated mark comprises an abnormal main overlay laminated mark, and whether the main overlay laminated mark is the abnormal main overlay laminated mark is judged according to a comparison result of the main measurement value and a preset threshold value;
acquiring an auxiliary measurement value according to the auxiliary overlay lamination mark;
performing overlay compensation based on the main measurement value and the auxiliary measurement value;
wherein the step of overlay compensation based on the primary metrology value and the secondary metrology value comprises:
obtaining an abnormal Q-Merit value of the abnormal main overlay lamination mark;
determining a feedback compensation value according to the abnormal Q-Merit value and the auxiliary measurement value;
and carrying out overlay compensation according to the feedback compensation value.
2. The method of controlling the accuracy of semiconductor alignment as set forth in claim 1, wherein: the step of determining whether the primary overlay mark is an abnormal primary overlay mark according to the comparison result of the primary measurement value and a preset threshold value includes:
the primary measurement value comprises an offset value and/or a Q-Merit value;
and judging that the main overlay laminated mark is the abnormal main overlay laminated mark when the deviation value and/or the Q-Merit value is larger than the preset threshold value.
3. The method of controlling semiconductor overlay accuracy of claim 1, wherein the step of determining a feedback compensation value based on the abnormal Q-Merit value and the auxiliary measurement value further comprises:
determining the direction of the abnormal Q-Merit value according to the main measurement value of the abnormal main overlay lamination and the auxiliary measurement value of the auxiliary overlay lamination mark;
the feedback compensation value is the sum of the abnormal Q-Merit value of the belt direction and the auxiliary measuring value.
4. The method of controlling the accuracy of semiconductor alignment according to claim 1, wherein:
the distance between the main overlay mark and the auxiliary overlay mark is less than 5 mm.
5. A semiconductor overlay stack mark, comprising:
a main overlay mark comprising a plurality of main sub-lines extending along a first direction;
the auxiliary overlay laminated mark comprises a plurality of auxiliary sub-lines extending along a second direction;
the first direction is different from the second direction;
the main overlay lamination mark is used for determining a main measurement value, the auxiliary overlay lamination mark is used for determining an auxiliary measurement value, so as to determine an abnormal main overlay lamination mark and an abnormal Q-Merit value of the abnormal main overlay lamination mark according to the main measurement value, determine a feedback compensation value according to the abnormal Q-Merit value and the auxiliary measurement value, and then perform overlay compensation according to the feedback compensation value.
6. The semiconductor overlay stack mark of claim 5, wherein:
the Pitch of the auxiliary sub-bar is greater than the Pitch of the main sub-bar.
7. The semiconductor overlay stack mark of claim 6, wherein:
the Pitch of the auxiliary sub-line is 2-5 times the Pitch of the main sub-line.
8. The semiconductor overlay stack mark of claim 5, wherein:
the main overlay lamination mark comprises a main overlay lamination abnormal mark, and the main overlay lamination abnormal mark is distributed in a partial area on the wafer.
9. The semiconductor overlay stack mark of claim 5, wherein:
the distance between the main overlay mark and the auxiliary overlay mark is less than 5 mm.
10. The semiconductor overlay stack mark of claim 5, wherein:
the first direction is the same as the extending direction of the main pattern in the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911032221.6A CN112731778B (en) | 2019-10-28 | 2019-10-28 | Control method for semiconductor alignment precision and laminated mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911032221.6A CN112731778B (en) | 2019-10-28 | 2019-10-28 | Control method for semiconductor alignment precision and laminated mark |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112731778A CN112731778A (en) | 2021-04-30 |
| CN112731778B true CN112731778B (en) | 2022-08-02 |
Family
ID=75588861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911032221.6A Active CN112731778B (en) | 2019-10-28 | 2019-10-28 | Control method for semiconductor alignment precision and laminated mark |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112731778B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115616861A (en) * | 2021-07-15 | 2023-01-17 | 长鑫存储技术有限公司 | Measurement mark, measurement layout and measurement method |
| CN117410276B (en) * | 2023-12-12 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Optical measuring structure of semiconductor device and measuring method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62126634A (en) * | 1985-11-28 | 1987-06-08 | Canon Inc | Alignment mark for semiconductor wafer |
| TW410457B (en) * | 1995-12-18 | 2000-11-01 | Nippon Electric Co | Misergistration detecting marks for pattern formed on semiconductor substrate |
| CN103713477A (en) * | 2012-09-28 | 2014-04-09 | 无锡华润上华半导体有限公司 | Alignment structure and alignment method for dual surface lithography machine |
| WO2019139685A1 (en) * | 2018-01-12 | 2019-07-18 | Kla-Tencor Corporation | Metrology targets and methods with oblique periodic structures |
-
2019
- 2019-10-28 CN CN201911032221.6A patent/CN112731778B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62126634A (en) * | 1985-11-28 | 1987-06-08 | Canon Inc | Alignment mark for semiconductor wafer |
| TW410457B (en) * | 1995-12-18 | 2000-11-01 | Nippon Electric Co | Misergistration detecting marks for pattern formed on semiconductor substrate |
| CN103713477A (en) * | 2012-09-28 | 2014-04-09 | 无锡华润上华半导体有限公司 | Alignment structure and alignment method for dual surface lithography machine |
| WO2019139685A1 (en) * | 2018-01-12 | 2019-07-18 | Kla-Tencor Corporation | Metrology targets and methods with oblique periodic structures |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112731778A (en) | 2021-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6218200B1 (en) | Multi-layer registration control for photolithography processes | |
| US9123583B2 (en) | Overlay abnormality gating by Z data | |
| CN112731778B (en) | Control method for semiconductor alignment precision and laminated mark | |
| US6484064B1 (en) | Method and apparatus for running metrology standard wafer routes for cross-fab metrology calibration | |
| JP4890846B2 (en) | Measuring apparatus, measuring method, exposure apparatus, and device manufacturing method | |
| US20060160037A1 (en) | Automated sub-field blading for leveling optimization in lithography exposure tool | |
| US20200150547A1 (en) | Method of determining a position of a feature | |
| CN115309005A (en) | Method and apparatus for optimizing a lithographic process | |
| US20160334208A1 (en) | Overlay mark pattern and method of measuring overlay | |
| CN114038776B (en) | Method for solving alignment deviation caused by wafer warping deformation | |
| US7507508B2 (en) | Method for manufacturing a semiconductor device | |
| CN101789386A (en) | Method for chip alignment | |
| JP2007328289A (en) | Reticle, semiconductor chip, and method of manufacturing semiconductor device | |
| CN107561875B (en) | Overlay error measurement and problem assessment method | |
| US6440821B1 (en) | Method and apparatus for aligning wafers | |
| JP2011066323A (en) | Method for correction of exposure treatment | |
| US20030104292A1 (en) | Semiconductor device and fabrication method therefor | |
| US20040002172A1 (en) | Methods and apparatus for aligning a wafer in which multiple light beams are used to scan alignment marks | |
| CN114236974A (en) | Method for compensating deviation of wafer marking structure | |
| US6586143B1 (en) | Accurate wafer patterning method for mass production | |
| US8212990B2 (en) | Exposure apparatus, information processing apparatus, and method of manufacturing device | |
| KR960007621B1 (en) | Method of compensating for overlaying error in semiconductor device | |
| JP2012164811A (en) | Method of manufacturing semiconductor device, method of determining shipping of exposure mask and method of manufacturing exposure mask | |
| US20170139329A1 (en) | Lithography system and semiconductor processing process | |
| CN116344511B (en) | Alignment mark layout and operation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |