CN112731130A - F-type leakage circuit breaker testing device and testing method - Google Patents
F-type leakage circuit breaker testing device and testing method Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
Abstract
The invention discloses a testing device and a testing method for an F-type residual current circuit breaker, which are characterized in that: the testing device comprises a controller, an upper computer, a waveform generation and current detection unit, a current output unit, a surge current generation unit and a test port; the invention is used for testing the action characteristics of the F-type electric leakage breaker, the upper computer is used for setting a test mode and test parameters and sending the test mode and the test parameters to the controller, the controller enters different test steps by judging the test mode, controls the generation of basic waveform signals and the selection of test current, and carries out current detection by setting a feedback signal for processing the test state and test data of a tested article, thereby controlling and covering the GB/T22794 and 2017 items (1) to (6) of the test items of the F-type electric leakage breaker, and filling the blank of the testing device of the F-type electric leakage breaker.
Description
Technical Field
The invention relates to a testing device and a testing method for an F-type residual current circuit breaker, and belongs to the field of intelligent detection instruments for low-voltage electrical appliances.
Background
In the field of low-voltage electrical appliances, the national standard GB/T22794-. The following requirements are made in the standard for the action characteristic test of the F-type circuit breaker: (1) correct action when the composite residual current steadily increases; (2) correct action when a compound residual current is suddenly applied; (3) the four-pole F-type circuit breaker has correct residual current action under the condition of only supplying power to two poles; (4) performance at 3000A inrush current (8/20us inrush current test); (5) performance under inrush residual current (single 50Hz or 60Hz sinusoidal half wave); (6) the correct action when the pulsating direct current residual current (continuous 50Hz or 60Hz sine half wave) is superposed with 10mA smooth direct current.
At present, an operation characteristic testing device for an earth leakage protection circuit breaker is provided with an AC type, an A type and a B type, and the device with the most complete functions is a B type testing device. Patent CN201510334792 discloses a multi-output power supply capable of generating composite residual current, pulsating direct current residual current and superimposed smooth direct current, and using the power supply and a simple peripheral logic control loop, the above items (1), (2), (3) and (6) of testing items of the F-type residual current circuit breaker can be realized. Patent CN204287413U discloses a B-type residual current circuit breaker testing device, which describes an alternating current residual current superposition smoothing direct current residual current testing mode, and can realize item (6) of the above F-type residual current circuit breaker testing item. It can be seen that the B-type testing device with the most complete testing function cannot complete the items (4) and (5) of the testing items of the F-type residual current circuit breaker at present. Therefore, no test device capable of covering the test strip of the F-type residual current circuit breaker exists.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the prior art does not have a testing device capable of covering an F-type leakage circuit breaker testing strip.
In order to solve the above problems, the technical solution of the present invention is to provide a testing apparatus for an F-type residual current circuit breaker, which is characterized in that: the device comprises a controller, an upper computer, a waveform generation and current detection unit, a current output unit, a surge current generation unit and a test port;
the upper computer is connected with a communication port of the controller for bidirectional communication, the upper computer is used for setting test parameters and sending the test parameters to the controller, and the controller sends test data to the upper computer for real-time display;
the controller is connected with the waveform generation and current detection unit through the second communication port and the analog output port, the controller sends waveform information received from the upper computer to the waveform generation and current detection unit through the second communication port, and the waveform generation and current detection unit generates a basic waveform signal according to the waveform information, processes the basic waveform signal and then performs signal operation on the basic waveform signal and an analog signal output by the analog output port of the controller to obtain an analog signal with the amplitude required by a test;
the input end of the current output unit is connected with the output end of the waveform generation and current detection unit, the waveform generation and current detection unit outputs an analog signal to the current output unit, and the current output unit outputs leakage current to the test port after amplifying the power of the analog signal; meanwhile, the current output unit samples the leakage current, outputs a feedback signal to the waveform generation and current detection unit for current detection, and is used for processing the test state and test data of the tested object;
the controller is connected with the input end of the surge current generating unit through the first digital output port, and controls a switch in the surge current generating unit through outputting a digital signal, so that the surge current generating unit is charged and discharged to generate surge current and output the surge current to the test port;
the controller is connected with the input end of the test port through the second digital output port, the test port is controlled through the second output digital signal, so that the test current finally output to the tested object is selected to be leakage current or surge current, and the current output by the test port is used as the final test current and is output to the tested object.
Preferably, the base waveform signal comprises a composite waveform signal, a single 50Hz or 60Hz sinusoidal half-wave signal or a pulsating direct current residual current superimposed direct current waveform signal.
Preferably, the waveform generating and current detecting unit comprises a single chip with digital/analog signal conversion and analog/digital signal conversion functions, a subtraction circuit, a multiplication circuit, an addition circuit, a first proportional operation circuit, a second proportional operation circuit, a first isolation circuit and a second isolation circuit;
the communication port of the single chip microcomputer is connected with the communication port II of the controller and used for acquiring waveform information; a first waveform signal is output from a digital/analog signal conversion port of the single chip microcomputer, a second waveform signal is output after the first waveform signal is subtracted from a bias voltage through a subtraction circuit, a third waveform signal is output after the second waveform signal is subjected to signal operation with an analog signal output from an analog output port of the controller in a multiplication circuit, a fourth waveform signal is output after the third waveform signal is subjected to signal operation through a first proportional operation circuit, a fifth waveform signal is output after the fourth waveform signal is subjected to signal operation through a first isolation circuit, and the fifth waveform signal is an analog signal with the amplitude required by the test;
the feedback signal passes through the second isolation circuit and then outputs a first feedback signal, the first feedback signal passes through the second proportional operation circuit and then outputs a second feedback signal, the second feedback signal passes through the addition circuit and is added with a bias voltage and then outputs a third feedback signal, the third feedback signal is input to an analog/digital signal conversion port of the single chip microcomputer, the single chip microcomputer calculates according to the third feedback signal to obtain a leakage current value, and meanwhile calculates according to the time when the third feedback signal appears and disappears to obtain the tripping time of the tested object.
Preferably, the current output unit comprises a power operational amplifier and a load resistor, the power operational amplifier supplies power for a positive power supply and a negative power supply and is designed in a voltage following mode, an input signal of the power operational amplifier is the waveform signal five, and an output signal of the power operational amplifier is loaded to the load resistor to generate the required leakage current; the voltage across the load resistor is the feedback signal.
Preferably, the inrush current generating unit includes a control switch S1, a high-voltage power supply, a charging loop and a discharging loop, the charging loop includes a resistor R1 and a capacitor C1, the discharging loop includes a capacitor C1, a resistor R2, a resistor R3 and an inductor L1, a digital output port of the controller is connected to the high-voltage power supply and a control end of the control switch S1, a positive electrode of the high-voltage power supply is connected to one end of the capacitor C1, one end of the resistor R3 and one end of the control switch S1 through the resistor R1, the other end of the control switch S1 is connected to one end of the inductor L1 through the resistor R2, and the other end of the inductor L1, the other end of the resistor R3 and the other end of the capacitor C1 are connected to a negative.
Preferably, the test port comprises a change-over switch, two change-over ends of the change-over switch are respectively connected with the output end of the current output unit and the output end of the surge current generation unit, the leakage current and the surge current are accessed, and the controller outputs a digital signal II to control the change-over switch in the test port, so that the finally output test current can select one of the leakage current and the surge current according to different tests.
Another technical solution of the present invention is to provide a testing method for an F-type residual current circuit breaker, which applies the testing apparatus for an F-type residual current circuit breaker described above, and is characterized in that: the method comprises the following steps:
step 1, inputting test parameters by an upper computer, wherein the test parameters comprise a test mode and a test current, and the upper computer sends the set test parameters to a controller;
and 7, the controller controls the test port to be switched into leakage current through the digital signal II, the waveform generating and current detecting unit generates a pulsating direct current residual current superposed direct current waveform signal, the analog signal output by the analog output port of the controller slowly rises from 0V to enable the leakage current to slowly rise until the switch of the tested object is tripped and disconnected, and the controller records the magnitude of the current when the switch of the tested object is tripped and disconnected and displays the current value on the upper computer.
Compared with the prior art, the invention has the beneficial effects that:
the F-type electric leakage circuit breaker testing device and the testing method are used for testing the action characteristics of the F-type electric leakage circuit breaker, a testing mode and testing parameters are set through an upper computer and are sent to a controller, the controller enters different testing steps through judging the testing mode, generation of basic waveform signals and selection of testing current are controlled, current detection is carried out through setting feedback signals and is used for processing a tested article testing state and testing data, and then GB/T22794 and 2017 are controlled to cover the items (1) to (6) of the F-type electric leakage circuit breaker testing items, and the blank of the F-type electric leakage circuit breaker testing device is filled.
Drawings
FIG. 1 is a block diagram of a testing device for an F-type residual current circuit breaker according to the present invention;
FIG. 2 is a schematic diagram of a waveform generation and current detection unit according to the present invention;
FIG. 3 is a schematic diagram of a circuit structure of a current output unit according to the present invention;
FIG. 4 is a schematic diagram of a circuit structure of an inrush current generation unit according to the present invention;
FIG. 5 is a schematic diagram of a test port according to the present invention;
fig. 6 discloses a flow chart of the testing method of the F-type residual current circuit breaker of the present invention.
Detailed Description
In order to make the invention more comprehensible, preferred embodiments are described in detail below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 shows a block diagram of a testing device for an F-type residual current circuit breaker according to the present invention, which includes a controller 101, an upper computer 102, a waveform generating and current detecting unit 103, a current output unit 104, an inrush current generating unit 105, and a test port 106. Wherein: the controller 101 is connected with the upper computer 102 through the first communication port 107 to transmit bidirectional communication signals 112, a tester sets test parameters on the upper computer 102, the upper computer 102 sends the test parameters to the controller 101, the controller 101 sends data to be displayed in the test process to the upper computer 102, and the data is displayed on the upper computer 102 in real time.
The controller 101 is connected to the waveform generation and current detection unit 103 via the second communication port 109 and the analog output port 108, and transmits a bidirectional communication signal 114 and an analog signal 113. The controller 101 sends waveform information received from the upper computer 102 to the waveform generation and current detection unit 103 through the second communication port 109, the waveform generation and current detection unit 103 generates relevant basic waveforms according to the waveform information, the basic waveforms comprise composite waveforms and single 50Hz or 60Hz sine half-wave or pulsating direct current residual current superposed direct current waveforms, and in the waveform generation and current detection unit 103, the basic waveforms are subjected to signal processing and then are subjected to signal operation with 0-5V analog signals 113 output by the analog port 108 of the controller, so that signals with amplitude required by tests are obtained.
The output end of the waveform generation and current detection unit 103 is connected to the current output unit 104, the waveform generation and current detection unit 103 outputs an analog signal 115 to the current output unit 104, and the current output unit 104 amplifies the power of the signal and outputs a leakage current 117 to the test port 106. Meanwhile, the current output unit 104 samples the leakage current 117, outputs a feedback signal 116 in the form of a voltage signal to the waveform generation and current detection unit 103, and performs current detection for the test state of the test object and test data processing.
The controller 101 is connected to the inrush current generating unit 105 through a first digital output port 110, and the controller 101 outputs digital signals 118-1 and 118-2 to control switches in the inrush current generating unit 105, so that the inrush current generating unit 105 charges and discharges to generate an inrush current 119 and output the inrush current 119 to the test port 106.
The controller 101 is connected to the test port 106 through the second digital output port 111, the second digital signal 120 output by the controller 101 controls the switch in the test port 106, so that the test current 121 finally output to the test object is selected as the leakage current 117 or the surge current 119, and the current output by the test port 106 is output to the test object as the final test current 121.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of the waveform generation and current detection unit 103 according to an embodiment of the invention. The waveform generating and current detecting unit comprises a singlechip with digital/analog signal conversion and analog/digital signal conversion functions, a subtraction circuit, a multiplication circuit, an addition circuit, a proportional operation circuit and an isolation circuit. The single chip microcomputer communicates with the controller 101 through a communication port, transmits a communication signal 114, and acquires waveform information. A first waveform signal is output from a digital/analog signal conversion port of the single chip microcomputer, a second waveform signal is output through a subtraction circuit, the second waveform signal is subjected to signal operation with an analog signal 113 output from an analog port 108 of the controller 101 in a multiplication circuit and then outputs a third waveform signal, the third waveform signal is subjected to signal operation through a first proportional operation circuit and then outputs a fourth waveform signal, and the fifth waveform signal is an analog signal 115 after the fourth waveform signal passes through a first isolation circuit; the feedback signal 116 outputs a first feedback signal after passing through a second isolation circuit, the first feedback signal outputs a second feedback signal after passing through a second proportional operation circuit, the second feedback signal outputs a third feedback signal after passing through an addition circuit, the third feedback signal is input to an analog/digital signal conversion port of the single chip microcomputer, the single chip microcomputer calculates according to the third feedback signal to obtain a leakage current value, and meanwhile, the tripping time of the tested product can be calculated according to the appearing and disappearing time of the third feedback signal.
The waveform generating and current detecting means will be further described. The waveform signal output by the singlechip is a positive voltage signal, and finally positive and negative voltage waveforms are needed, so that the waveform signal I needs to be subtracted from a bias voltage by a subtraction circuit to obtain a positive and negative voltage waveform signal II, and the subtraction circuit can be realized by an operational amplifier and a resistor; the second waveform signal is a signal with a fixed voltage amplitude, and the test requirement of slow rise of leakage current cannot be finally realized, so the second waveform signal needs to be multiplied by the analog signal 113 through a multiplication circuit to obtain a third variable voltage amplitude waveform signal, the analog signal 113 is provided by the controller 101, the amplitude of the third variable voltage amplitude waveform signal is variable, and the multiplication circuit can be realized by selecting the chip AD633 and corresponding peripheral circuits; the amplitude of the waveform signal III cannot reach the final test requirement, so that the waveform signal III needs to be subjected to proportional amplification through a proportional operation circuit I to obtain a waveform signal IV, and the proportional operation circuit can be realized by an operational amplifier and a resistor; in order to ensure the safety of the waveform generation and current detection unit, the waveform generation and current detection unit needs to be isolated from the test loop, so that the waveform signal four passes through the isolation circuit one to obtain the analog signal 115 and is transmitted backwards, and the isolation circuit is an analog signal isolation circuit and can be realized by selecting the chip AD210 and corresponding peripheral circuits. Aiming at the processing of the feedback signal 116, firstly, a first feedback signal is obtained through the isolation of a second isolation circuit, and the implementation mode of the second isolation circuit is the same as that of the first isolation circuit; the amplitude of the first feedback signal exceeds the input voltage limit of the analog/digital signal port of the singlechip, so that the first feedback signal needs to be scaled down by a second proportional operation circuit to obtain a second feedback signal; the proportional operation circuit can be realized by an operational amplifier and a resistor; the second feedback signal is a positive and negative voltage waveform signal, and only a positive voltage waveform can be input into the analog/digital signal port of the singlechip, so that the second feedback signal needs to be added with a bias voltage through an adding circuit to obtain a positive voltage waveform feedback signal III, and the adding circuit can be realized by an operational amplifier and a resistor.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of the current output unit 104 according to an embodiment of the invention. The current output unit 104 includes a power operational amplifier and a load resistor R, and the power operational amplifier may select the chip OPA549, etc. The power operational amplifier is powered by positive and negative double power supplies (V + and V-) and is designed in a voltage following mode, an input signal of the power operational amplifier is an analog signal 115 output by the waveform generation and current detection unit 103, and an output signal of the power operational amplifier is loaded to the load resistor R to generate a required leakage current 117. The voltage across the load resistor R is fed back as a feedback signal 116 to the waveform generation and current detection unit 103.
Referring to fig. 4, fig. 4 is a schematic diagram of a circuit structure of the inrush current generation unit 105 according to an embodiment of the invention. The inrush current generation unit 105 includes a control switch S1, a high-voltage power supply HV, a charging circuit configured by R1 and C1, and a discharging circuit configured by C1, R2, R3, and L1. A first digital output port 110 of the controller 101 is connected to a high-voltage power supply and a control end of the control switch S1, a positive electrode of the high-voltage power supply is connected to one end of the capacitor C1, one end of the resistor R3 and one end of the control switch S1 through the resistor R1, the other end of the control switch S1 is connected to one end of the inductor L1 through the resistor R2, and the other end of the inductor L1, the other end of the resistor R3 and the other end of the capacitor C1 are connected to a negative electrode of the high-voltage power supply. The controller 101 outputs a digital signal 118-1 to control the high-voltage power supply to be electrified, the charging loop works, the controller 101 times for 30S, and then the controller 101 outputs a digital signal 118-2 to control S1 to switch on the discharging loop to discharge and output an inrush current 119. The internal resistance of the surge current generation unit is 2 omega, the short-circuit output peak current is 3000A, and the waveform is 8/20us attenuation wave.
To achieve the above parameters, a set of optional component parameters is as follows: the high-voltage power supply HV has the voltage of +/-6 kV and the power of 100W; the resistance of the resistor R1 is 200k omega, and the power is 200W; the capacitance value of the capacitor C1 is 10uF, and the voltage resistance is 6 kV; s1 selecting a mercury relay; the resistance of the resistor R2 is 2 omega, and the power is 200W; the resistance of the resistor R3 is 10 omega, and the power is 200W; the inductance L1 has a value of 10uH, and is wound by copper wires with the cross section of 2.5 square.
Referring to FIG. 5, FIG. 5 discloses a schematic diagram of a test port 106 according to an embodiment of the present invention. The test port 106 comprises a change-over switch, two change-over terminals of the change-over switch are respectively connected to the leakage current 117 and the surge current 119, the controller 101 outputs a second digital signal 120 to control the change-over switch in the test port 106, so that the test current 121 finally output to the tested object is selected as the leakage current 117 or the surge current 119 and is output to the tested object.
Referring to fig. 6, fig. 6 is a flow chart of a testing method for an F-type residual current circuit breaker according to the present invention. The testing method adopting the F-type residual current circuit breaker testing device comprises the following steps:
step 1, a tester inputs test parameters including a test mode and a test current into an upper computer 102, and the upper computer 102 sends the parameters set by the tester to a controller 101.
And 3, the controller 101 controls the test port 106 to be switched into leakage current through the second digital signal 120, the waveform generating and current detecting unit 103 generates a composite waveform signal, the analog signal 113 output by the analog port 108 of the controller 101 slowly rises from 0V to enable the leakage current 117 to slowly rise until the switch of the tested object is tripped and disconnected, and the controller 101 records the current magnitude when the switch of the tested object is tripped and disconnected and displays the current value on the upper computer 102.
And 4, the controller 101 controls the test port 106 to be switched into leakage current through the second digital signal 120, the waveform generating and current detecting unit 103 generates a composite waveform signal, the controller 101 calculates according to a test current value input by a tester, and outputs a corresponding analog signal 113 with a fixed amplitude value at the analog port 108 so as to enable the leakage current 117 to instantly rise to a set current value of the tester, so that the switch of the tested article is tripped and disconnected, the controller 101 records the time of the switch of the tested article from the application of the leakage current to the complete disconnection, and the time value is displayed on the upper computer 102.
And 5, the controller 101 controls the test port 106 to be switched into the surge current through the second digital signal 120, the controller 101 outputs a digital signal 118-1 to control a high-voltage power supply in the surge current generating unit 105 to be electrified, a charging loop works, the controller times for 30s, then the controller 101 outputs a digital signal 118-2 to control a discharging loop in the surge current generating unit 105 to be switched on and discharged, the surge current 119 is output, and a tester automatically observes whether the tested product is tripped or broken.
And 6, the controller 101 controls the test port 106 to be switched into leakage current through the second digital signal 120, the waveform generating and current detecting unit 103 generates a single 50Hz or 60Hz sine half-wave signal, the controller 101 calculates according to a test current value input by a tester, and outputs a corresponding analog signal 113 with a fixed amplitude at the analog port 108, so that the leakage current 117 instantly rises to a set current value of the tester, and the tester can automatically observe whether the tested object is tripped or broken.
And 7, the controller 101 controls the test port 106 to be switched into leakage current through the second digital signal 120, the waveform generating and current detecting unit 103 generates a pulsating direct current residual current superposed direct current waveform signal, an analog signal 113 output by an analog port 108 of the controller 101 slowly rises from 0V to enable the leakage current 117 to slowly rise until the switch of the tested object is tripped and disconnected, the controller 101 records the current magnitude of the switch of the tested object when the switch of the tested object is tripped and disconnected, and the upper computer 102 displays the current value.
Claims (7)
1. The utility model provides a F type electric leakage circuit breaker testing arrangement which characterized in that: the device comprises a controller (101), an upper computer (102), a waveform generation and current detection unit (103), a current output unit (104), an inrush current generation unit (105) and a test port (106);
the upper computer (102) is connected with a first communication port (107) of the controller (101) for bidirectional communication, the upper computer (102) is used for setting test parameters and sending the test parameters to the controller (101), and the controller (101) sends test data to the upper computer (102) for real-time display;
the controller (101) is connected with the waveform generation and current detection unit (103) through a communication port II (109) and an analog output port (108), the controller (101) sends waveform information received from the upper computer (102) to the waveform generation and current detection unit (103) through the communication port II (109), and the waveform generation and current detection unit (103) generates a basic waveform signal according to the waveform information, performs signal processing on the basic waveform signal and then performs signal operation on an analog signal output by the analog output port (108) of the controller (101) to obtain an analog signal with the amplitude required by a test;
the input end of the current output unit (104) is connected with the output end of the waveform generation and current detection unit (103), the waveform generation and current detection unit (103) outputs an analog signal to the current output unit (104), and the current output unit (104) amplifies the power of the analog signal and then outputs leakage current to the test port (106); meanwhile, the current output unit (104) samples leakage current, outputs a feedback signal to the waveform generation and current detection unit (103) for current detection, and is used for processing the test state and test data of the tested object;
the controller (101) is connected with the input end of the surge current generating unit (105) through a first digital output port (110), and controls a switch in the surge current generating unit (105) through outputting digital signals (118-1 and 118-2), so that the surge current generating unit (105) is charged and discharged to generate surge current and output the surge current to the test port (106);
the controller (101) is connected with the input end of the test port (106) through the digital output port II (111), controls the test port (106) through outputting a digital signal II (120) to enable the test current finally output to the tested object to be selected as leakage current or surge current, and outputs the current output by the test port (106) to the tested object as the final test current.
2. The testing device of an F-type residual current circuit breaker according to claim 1, wherein: the basic waveform signal comprises a composite waveform signal, a single 50Hz or 60Hz sine half-wave signal or a pulsating direct current residual current superposed direct current waveform signal.
3. The testing device of an F-type residual current circuit breaker according to claim 1, wherein: the waveform generation and current detection unit (103) comprises a single chip microcomputer with digital/analog signal conversion and analog/digital signal conversion functions, a subtraction circuit, a multiplication circuit, an addition circuit, a first proportional operation circuit, a second proportional operation circuit, a first isolation circuit and a second isolation circuit;
the communication port of the single chip microcomputer is connected with a second communication port (109) of the controller (101) and used for acquiring waveform information; a digital/analog signal conversion port of the single chip microcomputer outputs a first waveform signal, the first waveform signal is subtracted from a bias voltage through a subtraction circuit and then outputs a second waveform signal, the second waveform signal is subjected to signal operation with an analog signal output by an analog output port (108) of the controller (101) in a multiplication circuit and then outputs a third waveform signal, the third waveform signal is subjected to signal operation through a first proportional operation circuit and then outputs a fourth waveform signal, the fourth waveform signal is subjected to signal operation through a first isolation circuit and then outputs a fifth waveform signal, and the fifth waveform signal is an analog signal with the amplitude required by the test;
the feedback signal passes through the second isolation circuit and then outputs a first feedback signal, the first feedback signal passes through the second proportional operation circuit and then outputs a second feedback signal, the second feedback signal passes through the addition circuit and is added with a bias voltage and then outputs a third feedback signal, the third feedback signal is input to an analog/digital signal conversion port of the single chip microcomputer, the single chip microcomputer calculates according to the third feedback signal to obtain a leakage current value, and meanwhile calculates according to the time when the third feedback signal appears and disappears to obtain the tripping time of the tested object.
4. The testing device of an F-type residual current circuit breaker according to claim 1, wherein: the current output unit (104) comprises a power operational amplifier and a load resistor, the power operational amplifier supplies power for a positive power supply and a negative power supply and is designed to be in a voltage following mode, an input signal of the power operational amplifier is the waveform signal five, and an output signal of the power operational amplifier is loaded to the load resistor to generate the required leakage current; the voltage across the load resistor is the feedback signal.
5. The testing device of an F-type residual current circuit breaker according to claim 1, wherein: the surge current generation unit (105) comprises a control switch S1, a high-voltage power supply, a charging loop and a discharging loop, wherein the charging loop comprises a resistor R1 and a capacitor C1, the discharging loop comprises a capacitor C1, a resistor R2, a resistor R3 and an inductor L1, a first digital output port (110) of the controller (101) is respectively connected with the high-voltage power supply and a control end of the control switch S1, the positive electrode of the high-voltage power supply is respectively connected with one end of the capacitor C1, one end of the resistor R3 and one end of the control switch S1 through the resistor R1, the other end of the control switch S1 is connected with one end of the inductor L1 through the resistor R2, and the other end of the inductor L1, the other end of the resistor R3 and the other end of the capacitor C1.
6. The testing device of an F-type residual current circuit breaker according to claim 1, wherein: the test port (106) comprises a change-over switch, two change-over ends of the change-over switch are respectively connected with the output end of the current output unit (104) and the output end of the surge current generation unit (105) and are connected with the leakage current and the surge current, and the second output digital signal (120) of the controller (101) controls the change-over switch in the test port (106), so that the finally output test current can select one of the leakage current and the surge current according to different tests.
7. A testing method of an F-type residual current circuit breaker, applying the testing device of an F-type residual current circuit breaker according to any one of claims 1 to 6, characterized in that: the method comprises the following steps:
step 1, inputting test parameters by an upper computer, wherein the test parameters comprise a test mode and a test current, and the upper computer sends the set test parameters to a controller;
step 2, judging a test mode by the controller: if the correct action test is carried out when the composite residual current is stably increased or the correct action test of the residual current occurs when the four-pole F-type circuit breaker only supplies power to two poles, the step 3 is carried out; if the correct action test is carried out when the composite residual current is suddenly applied, the step 4 is carried out; if the performance test under 3000A surge current is carried out, entering step 5; if the performance test under the inrush residual current is carried out, entering step 6; if the correct action test is carried out when the pulsating direct current residual current is superposed with 10mA smooth direct current, the step 7 is carried out;
step 3, the controller controls the test port to be switched into leakage current through the digital signal II, the waveform generating and current detecting unit generates a composite waveform signal, an analog signal output by the analog output port of the controller slowly rises from 0V to enable the leakage current to slowly rise until the switch of the tested object is tripped and disconnected, the controller records the magnitude of the current when the switch of the tested object is tripped and disconnected, and the upper computer displays the current value;
step 4, the controller controls the test port to be switched into leakage current through the digital signal II, the waveform generating and current detecting unit generates a composite waveform signal, the controller calculates according to the input test current value and outputs a corresponding analog signal with a fixed amplitude value at the analog output port so as to enable the leakage current to instantly rise to the set test current value and enable the switch of the tested object to be tripped and disconnected, the controller records the time of the switch of the tested object from the application of the leakage current to the complete disconnection, and the time value is displayed on the upper computer;
step 5, the controller controls the test port to be switched into surge current through the second digital signal, the controller outputs the digital signal to control a high-voltage power supply in the surge current generating unit to be electrified, a charging loop works, the controller times for 30s, then the controller outputs the digital signal to control a discharging loop in the surge current generating unit to be switched on and discharged, the surge current is output, and testers can automatically observe whether the tested object is tripped or broken;
step 6, the controller controls the test port to be switched into leakage current through the digital signal II, the waveform generating and current detecting unit generates a single 50Hz or 60Hz sine half-wave signal, the controller calculates according to the input test current value, and outputs a corresponding analog signal with fixed amplitude at the analog output port so as to enable the leakage current to rise to the set test current value instantly, and a tester can automatically observe whether the tested object is tripped or broken;
and 7, the controller controls the test port to be switched into leakage current through the digital signal II, the waveform generating and current detecting unit generates a pulsating direct current residual current superposed direct current waveform signal, the analog signal output by the analog output port of the controller slowly rises from 0V to enable the leakage current to slowly rise until the switch of the tested object is tripped and disconnected, and the controller records the magnitude of the current when the switch of the tested object is tripped and disconnected and displays the current value on the upper computer.
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| CN202011499860.6A CN112731130A (en) | 2020-12-18 | 2020-12-18 | F-type leakage circuit breaker testing device and testing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116430221A (en) * | 2023-05-09 | 2023-07-14 | 国网江苏省电力有限公司宿迁供电分公司 | Test data simulation method, system, medium and test system for photovoltaic grid-connected circuit breaker |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116430221A (en) * | 2023-05-09 | 2023-07-14 | 国网江苏省电力有限公司宿迁供电分公司 | Test data simulation method, system, medium and test system for photovoltaic grid-connected circuit breaker |
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