CN112713161B - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
- Publication number
- CN112713161B CN112713161B CN202011603545.3A CN202011603545A CN112713161B CN 112713161 B CN112713161 B CN 112713161B CN 202011603545 A CN202011603545 A CN 202011603545A CN 112713161 B CN112713161 B CN 112713161B
- Authority
- CN
- China
- Prior art keywords
- electrode
- layer
- thin film
- film transistor
- array substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000010409 thin film Substances 0.000 claims abstract description 99
- 238000001514 detection method Methods 0.000 claims abstract description 67
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 230000031700 light absorption Effects 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims description 51
- 239000003990 capacitor Substances 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 31
- 230000009286 beneficial effect Effects 0.000 abstract description 7
- 238000009776 industrial production Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 210
- 238000002161 passivation Methods 0.000 description 32
- 239000000463 material Substances 0.000 description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 description 20
- 125000006850 spacer group Chemical group 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000035945 sensitivity Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14649—Infrared imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application discloses an array substrate and a preparation method thereof. The array substrate includes: a thin film transistor layer including a first thin film transistor; the infrared detection element is arranged on the first side of the thin film transistor layer and comprises a first electrode, a light absorption layer and a second electrode which are sequentially stacked on the first side, and the infrared detection element is electrically connected with the first thin film transistor; the light absorption layer is made of microcrystalline silicon. The thickness and band gap of the microcrystalline silicon can simultaneously meet the purpose of infrared detection, and the preparation process of the light absorption layer can be integrated into a production line of the display panel, so that the method is beneficial to large-scale industrial production and application.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
In recent years, with the progress of the display panel industry, users have made higher demands on display panels. The functions of the display panel are enriched, the man-machine interaction is enhanced, the competitiveness of the display panel is improved, and the display panel is an important development direction at present. Infrared detection elements have wide application in cell phones, computers and wearable electronics. The light absorption layer in the existing infrared detection element is usually made of monocrystalline silicon and InGaAs material. However, the growth temperature of single crystal silicon (900 ℃) is far higher than the upper temperature limit (600 ℃) in the display panel production process; the growth process of InGaAs, the molecular beam epitaxy process (Molecular Beam Epitaxy, MBE), is not compatible with the production line of display panels. Therefore, developing an array substrate compatible with an infrared detection element has become an important point of development of the display panel industry.
Disclosure of Invention
In order to solve the problems, the application provides an array substrate integrated with an infrared detection element and a preparation method thereof.
The application provides an array substrate, comprising:
a thin film transistor layer including a first thin film transistor;
the infrared detection element is arranged on the first side of the thin film transistor layer and comprises a first electrode, a light absorption layer and a second electrode which are sequentially stacked on the first side, and the infrared detection element is electrically connected with the first thin film transistor;
wherein the light absorption layer is made of microcrystalline silicon.
In some embodiments, the light absorbing layer has a thickness of 60 nanometers to 3000 nanometers; the bandgap of the light absorbing layer is 1.1eV to 1.5eV.
In some embodiments, the light absorbing layer has a thickness of 300 nanometers to 3000 nanometers.
In some embodiments, an orthographic projection of the infrared detection element on the thin film transistor layer is located within a range of the first thin film transistor.
In some embodiments, the first electrode is electrically connected to a source/drain of the first thin film transistor.
In some embodiments, the infrared detection element further includes a first semiconductor layer positioned between the first electrode and the light absorbing layer.
In some embodiments, the infrared detection element further includes a second semiconductor layer located between the light absorbing layer and the second electrode.
In some embodiments, the infrared detection element further includes a first semiconductor layer between the first electrode and the light absorbing layer and a second semiconductor layer between the light absorbing layer and the second electrode.
In some embodiments, the material of the first semiconductor layer is n-type amorphous silicon and the material of the second semiconductor layer is p-type amorphous silicon.
In some embodiments, the material of the first semiconductor layer is n-type microcrystalline silicon and the material of the second semiconductor layer is p-type microcrystalline silicon.
In some embodiments, the array substrate further includes a second thin film transistor and a pixel electrode electrically connected to the second thin film transistor, where the pixel electrode is disposed on the same layer as the second electrode.
In some embodiments, the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer in the array substrate, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are located in the same layer in the array substrate, and the active layer of the first thin film transistor and the active layer of the second thin film transistor are located in the same layer in the array substrate.
The application also provides a preparation method of the array substrate,
the method comprises the following steps:
forming a thin film transistor layer, wherein the thin film transistor layer comprises a first thin film transistor;
and sequentially preparing a first electrode, a light absorption layer and a second electrode on the first side of the thin film transistor layer to form an infrared detection element, and electrically connecting the infrared detection element to the first thin film transistor, wherein the light absorption layer is made of microcrystalline silicon.
In some embodiments, the microcrystalline silicon is prepared by a plasma enhanced chemical vapor deposition process.
Compared with the prior art, the application has the following beneficial effects:
the application provides an array substrate, wherein an infrared detection element of the array substrate comprises a first electrode, a light absorption layer and a second electrode which are sequentially stacked on a first side of a thin film transistor layer, and the infrared detection element is electrically connected with the first thin film transistor. The light absorption layer is made of microcrystalline silicon. The microcrystalline silicon can meet the infrared detection requirement of the display panel, and the infrared detection accuracy is improved. The manufacturing process of the light absorbing layer can be integrated into a production line of a display panel, and the production line of the display panel can be completely compatible with the manufacturing process of the light absorbing layer, thereby being beneficial to realizing large-scale industrial production and application.
Drawings
The technical solution of the present application and other advantageous effects will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic cross-sectional structure of an array substrate according to an embodiment of the present application.
Fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
Fig. 1 is a schematic cross-sectional structure of an array substrate 100 according to an embodiment of the present application. As shown in fig. 1, the array substrate 100 includes a thin film transistor layer 110, and the thin film transistor layer 110 includes a first thin film transistor 111.
The infrared detection element 120 is disposed on a first side 110S of the thin film transistor layer 110, where the first side 110S is an upper side of the thin film transistor layer 110. The infrared detection element 120 includes a first electrode 124, a light absorbing layer 122, and a second electrode 125 sequentially stacked on the first side 110S, and the infrared detection element 120 is electrically connected to the first thin film transistor 111. The first thin film transistor 111 is configured to provide a reverse bias voltage to the infrared detection element 120.
The infrared detection element 120 of the embodiment is composed of the first electrode 124, the light absorption layer 122 and the second electrode 125, so that the arrangement of an intermediate layer is omitted, the manufacturing process can be simplified on the basis of meeting the infrared detection purpose, the thickness of a panel is reduced, and the production cost is saved.
The material of the light absorbing layer 122 is microcrystalline silicon. The materials of the light absorbing layer in the prior art are typically polysilicon and amorphous silicon. However, due to the limitation of the growth process of the polysilicon, the thickness of the polysilicon is too thin (less than 45 nanometers) to absorb enough light, and the accuracy performance of infrared detection is affected. The prior art can prepare amorphous silicon with enough thickness, but the band gap of amorphous silicon with the thickness meeting the requirement cannot meet the requirement of infrared detection. The light absorption layer of the embodiment can simultaneously meet the infrared detection requirement of the display panel in the aspects of thickness (more than 45 nanometers) and band gap by using microcrystalline silicon, and the accuracy performance of infrared detection is improved.
The manufacturing process of the microcrystalline silicon can be integrated into a production line of a display panel, for example, the low-temperature polysilicon (Low Temperature Poly Silicon, LTPS) process can be compatible with the manufacturing process of the light absorption layer 122, and the compatibility is high, so that the manufacturing process is beneficial to large-scale industrial production and application.
In some embodiments, the thickness of the light absorbing layer 122 is between 60 nanometers and 3000 nanometers, for example, the thickness may be 100 nanometers, 200 nanometers, 500 nanometers, 1000 nanometers, 1500 nanometers, and 2000 nanometers. While its bandgap is between 1.1eV and 1.5eV, e.g., the bandgap may be 1.2eV, 1.3eV, 1.4eV. The thickness and band gap enable infrared detection element 120 to perform infrared detection.
In some embodiments, the thickness of the light absorbing layer 122 may be 300 nanometers to 3000 nanometers, for example, 400 nanometers, 800 nanometers, 1700 nanometers, and 2500 nanometers. The microcrystalline silicon within the thickness range can absorb more light, and the accuracy of infrared detection is improved.
In some embodiments, the orthographic projection of infrared detection element 120 onto thin film transistor layer 110 is within the range of first thin film transistor 111.
Specifically, the infrared detection element 120 is located directly above the first thin film transistor 111, and a decrease in the aperture ratio of the display panel due to the introduction of the infrared detection element 120 can be avoided.
In some embodiments, the infrared detection element 120 is connected to the source/drain of the first thin film transistor 111 through the first electrode 124.
In some embodiments, infrared detection element 120 further includes a first semiconductor layer 121, first semiconductor layer 121 being located between first electrode 124 and light absorbing layer 122. In this embodiment, a first semiconductor layer 121 is disposed between the first electrode 124 and the light absorbing layer 122, and the first semiconductor layer 121 can inhibit the leakage current caused by direct contact between the first electrode 124 and the light absorbing layer 122, and can absorb part of visible light, further promote the absorption of infrared light by the light absorbing layer 122, and further promote the detection sensitivity of the infrared detection element 120.
In some embodiments, infrared detection element 120 further includes a second semiconductor layer 123, second semiconductor layer 123 being located between light absorbing layer 122 and second electrode 125. In this embodiment, a second semiconductor layer 123 is disposed between the light absorbing layer 122 and the second electrode 125, and the second semiconductor layer 123 can inhibit the leakage current caused by direct contact between the light absorbing layer 122 and the second electrode 125, and can absorb part of visible light, further promote the absorption of infrared light by the light absorbing layer 122, and further promote the detection sensitivity of the infrared detection element 120.
In some embodiments, infrared detection element 120 further includes a first semiconductor layer 121 and a second semiconductor layer 123, first semiconductor layer 121 being located between first electrode 124 and light absorbing layer 122, second semiconductor layer 123 being located between light absorbing layer 122 and second electrode 125. The first semiconductor 121 and the second semiconductor 123 serve as a charge transport layer and a built-in electric field building layer for suppressing dark current and separating photo-generated electrons and holes and suppressing dark current and separating photo-generated electrons and holes. The generation of leakage current can be further suppressed as compared with the case where the first semiconductor 121 or the second semiconductor 123 is formed only on one side of the light absorbing layer 122. The light absorbing layer 122 is used to absorb infrared light.
In some embodiments, the material of the first semiconductor layer 121 is n-type amorphous silicon or n-type microcrystalline silicon.
In some embodiments, the material of the second semiconductor layer 123 is p-type amorphous silicon or p-type microcrystalline silicon.
Specifically, n-type amorphous silicon and p-type amorphous silicon, or n-type microcrystalline silicon and p-type microcrystalline silicon, are formed on both sides of the light absorbing layer 122, respectively, so that generation of leakage current can be suppressed, light of low light quantity can be detected, and sensitivity of infrared detection can be improved. In one embodiment, the material of the first semiconductor layer 121 is n-type amorphous silicon, and the material of the second semiconductor layer 123 is p-type amorphous silicon, so that the debugging cost can be reduced and the interference of visible light can be reduced.
In some embodiments, the array substrate 100 further includes a second thin film transistor 112 and a pixel electrode 180 electrically connected to the second thin film transistor 112, where the pixel electrode 180 is disposed on the same layer as the second electrode 125.
In some embodiments, the source and drain electrodes of the first thin film transistor 111 and the second thin film transistor 112 are located at the same layer in the array substrate 100, the gate electrode of the first thin film transistor 111 and the gate electrode of the second thin film transistor 112 are located at the same layer in the array substrate 100, and the active layer of the first thin film transistor 111 and the active layer of the second thin film transistor 112 are located at the same layer in the array substrate 100. The functional layers positioned on the same layer can be prepared by using the same photomask, so that the preparation cost and the preparation period can be saved.
Specifically, the array substrate 100 further includes a substrate 130, a light shielding layer 140 disposed on the substrate 130, a first spacer layer 150 covering the light shielding layer 140, and a second spacer layer 160 on the first spacer layer 150. The thin film transistor layer 110 is disposed on the second spacer layer 160.
In this embodiment, as shown in fig. 1, the first thin film transistor 111 and the second thin film transistor 112 may be bottom gate structures. The first thin film transistor 111 includes a first active layer 1111, a first gate electrode 1112, a first source electrode 1113, and a first drain electrode 1114. Similarly, the second thin film transistor 112 includes a second active layer 1121, a second gate electrode 1122, a second source electrode 1123, and a second drain electrode 1124. The first and second active layers 1111 and 1121, the first and second gates 1112 and 1122, the first and second sources 1113 and 1123, and the first and second drains 1114 and 1124 are located at the same layer in the array substrate 100. The same layer arrangement of the first thin film transistor 111 and the second thin film transistor 112 can save a photomask, simplify the whole preparation process of the array substrate related to the application, and reduce the production cost and the period of the array substrate 100.
The pixel electrode 180 is electrically connected to the second drain electrode 1124 of the second thin film transistor 112.
In some embodiments, the array substrate 100 further includes a touch electrode 170, and the touch electrode 170 includes an electrode line 171 and a touch pad (pad) 172 electrically connected to the electrode line 171. In some embodiments, the electrode lines 171 of the touch electrode 170 are disposed on the same layer as the first electrodes 124 of the infrared detection element 120. The arrangement structure can save the manufacturing process of the photomask.
In some embodiments, the array substrate 100 further includes a sensor capacitor 190C1, as shown in fig. 1, a first bottom electrode 191 is disposed above the first electrode 124 of the infrared detection element 120 and is electrically connected to the first electrode 124. The corresponding first top electrode 192 is electrically connected to and disposed in the same layer as the second electrode 125 of the infrared detection element 120. The first bottom electrode 191 and the first top electrode 192 constitute a sensor capacitance 190C1 as shown in fig. 1. The sensor capacitor 190C1 may make the voltage controlling the first thin film transistor 111 more stable. The sensor capacitor 190C1 is also connected to the Com potential, specifically, the first top electrode 192 of the sensor capacitor 190C1 is electrically connected to the common electrode 197. Common electrode 197 is disposed in the same layer as first electrode 124 of infrared detection element 120. In some embodiments, to improve stability of the sensor capacitor 190C1, the first top electrode 192 may be electrically connected to the common electrode 197 through a transition layer 196, and the transition layer 196 may be disposed on the same layer as the first bottom electrode 191 of the infrared detection element 120.
Of course, the array substrate 100 further includes the pixel capacitor 190C2, the second bottom electrode 193 and the first bottom electrode 191 of the sensor capacitor 190C1 are disposed in the same layer, the second top electrode 194 and the first top electrode 192 of the sensor capacitor 190C1 are disposed in the same layer, and the same photomask can be used for the structural layer disposed in the same layer, so as to save the manufacturing process and the manufacturing period of the array substrate. The second bottom electrode 193 and the second top electrode 194 constitute the pixel capacitor 190C2 as shown in fig. 1.
The embodiment provides an array substrate, in which an infrared detection element comprises a first electrode, a light absorption layer and a second electrode which are sequentially stacked, and the infrared detection element is electrically connected with a first thin film transistor. The light absorption layer is made of microcrystalline silicon. The microcrystalline silicon can meet the infrared detection requirement of the display panel at the same time in the thickness and band gap. The manufacturing process of the light absorption layer is integrated into the production line of the display panel, and the production line of the display panel can be completely compatible with the manufacturing process of the light absorption layer, thereby being beneficial to large-scale industrial production and application.
Fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application. Referring to fig. 1, as shown in fig. 2, the preparation method includes the steps of:
step 101: a thin film transistor layer 110 is formed, and the thin film transistor layer 110 includes a first thin film transistor 111.
In some embodiments, the thin film transistor layer 110 further includes a second thin film transistor 112 and a pixel electrode 180 electrically connected to the second thin film transistor 112.
Specifically, a substrate 130 is provided, a light shielding layer 140 is deposited on the substrate 130, and then the light shielding layer 140 is patterned by exposure etching or the like. A first spacer layer 150 and a second spacer layer 160 are sequentially deposited on the substrate 130. An active layer is deposited on the second spacer layer 160, using amorphous silicon (α -Si) as a material, which is converted to polysilicon (poly-Si) by laser annealing (Excimer Laser Annealing, ELA) or solid phase crystallization (Solid Phase Crystallization, SPC). When the laser annealing method is adopted, the laser generally used is XeCl laser, arF laser, krF laser, xeF laser and the like, and the amorphous silicon in the active layer is irradiated by the laser beam of short pulse of ultraviolet band, and the amorphous silicon can quickly absorb laser energy to melt and recrystallize. Then, after exposure, development, etching, peeling, or the like of the active layer using a mask plate, a first active layer 1111 and a second active layer 1121 are formed. The first active layer 1111 and the second active layer 1121 are ion-implanted to form source and drain regions. In some embodiments, the ion implantation may be performed by P ion doping. A gate insulating layer 113 and the gate layer disposed thereon are deposited on the second spacer layer 160, which is patterned using a repeated etching (Re-etch) process to form a first gate 1112 and a second gate 1122. An interlayer dielectric layer 114 is deposited on the gate insulating layer 113 and patterned to form a first via hole V1 and a second via hole V2, and a source drain layer is deposited on the interlayer dielectric layer 114 and patterned to form a first source 1113 and a first drain 1114 of the first thin film transistor 111 and a second source 1123 and a second drain 1124 of the second thin film transistor 112. A planarization layer 115 is covered on the interlayer dielectric layer 114, a first passivation layer 116 is deposited on the planarization layer 115, and patterning is performed on the planarization layer 115 and the first passivation layer 116 to form a third via V3.
Step 102: a first electrode 124, a light absorbing layer 122, and a second electrode 125 are sequentially formed on the first side 110S of the thin film transistor layer 110 to form an infrared detection element 120, and the infrared detection element 120 is electrically connected to the first thin film transistor 111, where the light absorbing layer 122 is formed of microcrystalline silicon.
Specifically, a layer of ITO material is deposited on the first passivation layer 116, and patterned to form a first electrode 124, where the first electrode 124 is electrically connected to the first drain electrode 1114 of the first thin film transistor 111 through the third via hole V3 on the first passivation layer 116.
In some embodiments, the ITO material layer is patterned, and the first electrode 124 and the electrode line 171 forming the touch electrode 170 may be formed simultaneously using the same mask.
A second passivation layer 126 is deposited on the first passivation layer 116 and covers the first electrode 124. In some embodiments, the second passivation layer 126 also covers the electrode lines 171 of the touch electrode 170.
The second passivation layer 126 is then processed to form an opening W exposing a portion of the first electrode 124, and the light absorbing layer 122 is deposited in the opening W.
In some embodiments, a first semiconductor layer 121 and a light absorbing layer 122 are sequentially deposited in the opening W, the first semiconductor layer 121 being located between the first electrode 124 and the light absorbing layer 122.
In some embodiments, a light absorbing layer 122 and a second semiconductor layer 123 are sequentially deposited in the opening W, the second semiconductor layer 123 being located between the light absorbing layer 122 and the second electrode 125.
In some embodiments, a first semiconductor layer 121, a light absorbing layer 122, and a second semiconductor layer 123 are sequentially deposited in the opening W.
In some embodiments, the material of the first semiconductor layer 121 adopts n-type amorphous silicon or n-type microcrystalline silicon.
In some embodiments, the material of the second semiconductor is p-type amorphous silicon or p-type microcrystalline silicon.
Specifically, n-type amorphous silicon and p-type amorphous silicon, or n-type microcrystalline silicon and p-type microcrystalline silicon, are formed on both sides of the light absorbing layer 122, respectively, so that generation of leakage current can be suppressed, light of low light quantity can be detected, and sensitivity of infrared detection can be improved. In one embodiment, the material of the first semiconductor layer 121 is n-type amorphous silicon, and the material of the second semiconductor layer 123 is p-type amorphous silicon, so that the debugging cost can be reduced and the interference of visible light can be reduced.
A third passivation layer 127 is deposited on the second passivation layer 126, a layer of ITO material is deposited on the third passivation layer 127, and the ITO material layer is subjected to patterning process to form a second bottom electrode 193 of the pixel capacitor 190C2. In some embodiments, when the ITO material layer is patterned, the first bottom electrode 191 of the sensor capacitor 190C1 may also be formed at the same time, and the fourth via V4 is formed in the third passivation layer 127, where the first bottom electrode 191 is electrically connected to the first electrode 124 of the infrared detection element 120 through the fourth via V4.
In some embodiments, the second passivation layer 126 and the third passivation layer 127 are patterned to form a fifth via V5. The fifth via hole V5 penetrates the second passivation layer 126 and the third passivation layer 127, exposing a portion of the electrode line 171. A touch pad 172 of the touch electrode 170 is formed on the corresponding position of the third passivation layer 127, and the touch pad 172 is electrically connected to the electrode line 171 through the fifth via V5.
A fourth passivation layer 128 is deposited on the third passivation layer 127, and the fourth passivation layer 128 is patterned to form a sixth via V6, the sixth via V6 penetrating through the planarization layer 115, the first passivation layer 116, the second passivation layer 126, the third passivation layer 127, and the fourth passivation layer 128. A layer of ITO material is deposited on the fourth passivation layer 128 and covers the second semiconductor layer 123. The ITO material layer is patterned to form the second electrode 125 of the infrared detection element 120, the first top electrode 192 of the sensor capacitor 190C1, the second top electrode 194 of the pixel capacitor 190C2, and the pixel electrode 180, respectively. The pixel electrode 180 is electrically connected to the second drain electrode 1124 of the second thin film transistor 112 through the sixth via hole V6.
In some embodiments, the first electrode 124 and the common electrode 197 are formed using the same mask. A seventh via V7 is formed on the second passivation layer 126 and the third passivation layer 127, and the seventh via V7 penetrates the third passivation layer 127 and exposes a portion of the common electrode 197. The first bottom electrode 191 and the transition layer 196 of the sensor capacitor 190C1 are formed using the same mask, and the transition layer 196 is filled in the seventh via hole V7 and electrically connected to the common electrode 197. An eighth via V8 is formed on the fourth passivation layer 128, and the first top electrode 192 of the sensor capacitor 190C1 is electrically connected to the transition layer 196 through the eighth via V8. A transition layer 196 is disposed between the first top electrode 192 and the common electrode 197 of the sensor capacitor 190C1 to connect the sensor capacitor 190C1 to the Com potential, so as to avoid forming a through hole directly in the second passivation layer 126, the third passivation layer 127 and the fourth passivation layer 128, and the through hole is easy to be over-etched when formed, which results in a reduced stability of the sensor capacitor 190C1.
In some embodiments, the light absorbing layer 122 is prepared using a plasma enhanced chemical vapor deposition process using H as the starting material 2 And SiH 4 Wherein H is 2 Is H in volume 2 And SiH 4 2% to 10% of the total volume. Wherein the temperature is 200 ℃ to 450 ℃ and the pressure is 1000mtor to 3000mtor during preparation. The process parameters of the plasma enhanced chemical vapor deposition process for preparing the microcrystalline silicon material are within the acceptable range of the production line of the display panel, and the production line of the display panel can be completely compatible with the manufacturing process of the light absorption layer 122, thereby being beneficial to realizing large-scale production.
The embodiment provides a preparation method of an array substrate, in the preparation method, microcrystalline silicon is prepared by utilizing a plasma enhanced chemical vapor deposition process and is used as a light absorption layer of an infrared detection element, so that the purpose of photosensitive detection is achieved. The manufacturing process of the light absorption layer can be integrated into a production line of the display panel, and is beneficial to realizing the mass production of display products integrated with the infrared detection element. In addition, the first thin film transistor and the second thin film transistor are arranged on the same layer, so that a photomask can be saved, the process of the array substrate is simplified, and the production period is shortened.
The above describes an array substrate and a preparation method thereof in detail, and specific examples are applied to describe the principle and the implementation of the application, and the description of the above implementation is only used for helping to understand the technical scheme and the core idea of the application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (7)
1. An array substrate, characterized by comprising:
a thin film transistor layer including a first thin film transistor;
the infrared detection element is arranged on the first side of the thin film transistor layer and comprises a first electrode, a light absorption layer and a second electrode which are sequentially stacked on the first side, the infrared detection element is electrically connected with the first thin film transistor, the infrared detection element further comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is positioned between the first electrode and the light absorption layer, and the second semiconductor layer is positioned between the light absorption layer and the second electrode;
the light absorption layer is made of microcrystalline silicon, the first semiconductor layer is made of n-type microcrystalline silicon, the second semiconductor layer is made of p-type microcrystalline silicon, and the band gap of the light absorption layer is 1.1eV to 1.5eV;
the sensor capacitor comprises a first bottom electrode and a first top electrode, wherein the first bottom electrode is arranged above the first electrode, the first top electrode and the second electrode are electrically connected and arranged in the same layer, the first top electrode is electrically connected with the common electrode through a transition layer, and the transition layer is arranged in the same layer as the first bottom electrode;
the pixel capacitor comprises a second bottom electrode and a second top electrode, wherein the second bottom electrode and the first bottom electrode are arranged in the same layer, and the second top electrode and the first top electrode are arranged in the same layer;
the touch electrode comprises an electrode wire and a touch pad connected with the electrode wire, and the electrode wire and the first electrode are arranged on the same layer;
the array substrate further comprises a second thin film transistor and a pixel electrode electrically connected with the second thin film transistor, wherein the pixel electrode and the second electrode are arranged in the same layer; the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located on the same layer in the array substrate, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are located on the same layer in the array substrate, and the active layer of the first thin film transistor and the active layer of the second thin film transistor are located on the same layer in the array substrate.
2. The array substrate of claim 1, wherein the light absorbing layer has a thickness of 60 nm to 3000 nm.
3. The array substrate of claim 2, wherein the light absorbing layer has a thickness of 300 nm to 3000 nm.
4. The array substrate according to claim 1, wherein an orthographic projection of the infrared detection element on the thin film transistor layer is located within a range of the first thin film transistor.
5. The array substrate of claim 1, wherein the first electrode is electrically connected to a source/drain of the first thin film transistor.
6. The preparation method of the array substrate is characterized by comprising the following steps of:
forming a thin film transistor layer, wherein the thin film transistor layer comprises a first thin film transistor;
sequentially preparing a first electrode, a light absorption layer and a second electrode on a first side of the thin film transistor layer to form an infrared detection element, and enabling the infrared detection element to be electrically connected with the first thin film transistor, wherein the infrared detection element further comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is positioned between the first electrode and the light absorption layer, the second semiconductor layer is positioned between the light absorption layer and the second electrode, the light absorption layer is made of microcrystalline silicon, the first semiconductor layer is made of n-type microcrystalline silicon, the second semiconductor layer is made of p-type microcrystalline silicon, and the band gap of the light absorption layer is 1.1eV to 1.5eV; wherein the method comprises the steps of
The step of sequentially preparing a first electrode, a light absorption layer and a second electrode on the first side of the thin film transistor layer further comprises the following steps:
forming a sensor capacitor, wherein the sensor capacitor comprises a first bottom electrode and a first top electrode, the first bottom electrode is arranged above the first electrode, the first top electrode and the second electrode are electrically connected and arranged in the same layer, the first top electrode is electrically connected with a common electrode through a transition layer, and the transition layer is arranged in the same layer as the first bottom electrode;
forming a pixel capacitor, wherein the pixel capacitor comprises a second bottom electrode and a second top electrode, the second bottom electrode and the first bottom electrode are arranged in the same layer, and the second top electrode and the first top electrode are arranged in the same layer;
forming a touch electrode, wherein the touch electrode comprises an electrode wire and a touch pad connected with the electrode wire, and the electrode wire and the first electrode are arranged on the same layer;
the thin film transistor layer further comprises a second thin film transistor and a pixel electrode electrically connected with the second thin film transistor, and the pixel electrode and the second electrode are arranged in the same layer; the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located on the same layer in the array substrate, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are located on the same layer in the array substrate, and the active layer of the first thin film transistor and the active layer of the second thin film transistor are located on the same layer in the array substrate.
7. The method of claim 6, wherein the microcrystalline silicon is produced by a plasma enhanced chemical vapor deposition process.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011603545.3A CN112713161B (en) | 2020-12-30 | 2020-12-30 | Array substrate and preparation method thereof |
| US17/278,342 US20240038793A1 (en) | 2020-12-30 | 2020-12-31 | Array substrate and manufacturing method thereof |
| PCT/CN2020/142362 WO2022141493A1 (en) | 2020-12-30 | 2020-12-31 | Array substrate and preparation method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011603545.3A CN112713161B (en) | 2020-12-30 | 2020-12-30 | Array substrate and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112713161A CN112713161A (en) | 2021-04-27 |
| CN112713161B true CN112713161B (en) | 2023-10-31 |
Family
ID=75546996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011603545.3A Active CN112713161B (en) | 2020-12-30 | 2020-12-30 | Array substrate and preparation method thereof |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20240038793A1 (en) |
| CN (1) | CN112713161B (en) |
| WO (1) | WO2022141493A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299674B (en) * | 2021-05-08 | 2022-09-09 | 武汉华星光电技术有限公司 | Array substrate |
| CN113345917B (en) * | 2021-05-21 | 2024-03-08 | 武汉华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714589A (en) * | 2008-10-01 | 2010-05-26 | 精工爱普生株式会社 | Photoelectric conversion element, photoeletric conversion device, and image sensor |
| CN105720063A (en) * | 2016-04-13 | 2016-06-29 | 京东方科技集团股份有限公司 | Array substrate and preparation method therefor, sensor and detection equipment |
| CN109686808A (en) * | 2018-12-27 | 2019-04-26 | 厦门天马微电子有限公司 | Diode and preparation method thereof, array substrate, display panel |
| CN110444553A (en) * | 2019-08-14 | 2019-11-12 | 京东方科技集团股份有限公司 | Photosensitive device and its manufacturing method, detection substrate and array substrate |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4271268B2 (en) * | 1997-09-20 | 2009-06-03 | 株式会社半導体エネルギー研究所 | Image sensor and image sensor integrated active matrix display device |
| CN109037249B (en) * | 2017-06-12 | 2021-11-02 | 上海耕岩智能科技有限公司 | Image detection display device, device and preparation method thereof |
| TWI680397B (en) * | 2018-04-03 | 2019-12-21 | 薛英家 | Sensor board and display with sensor board |
-
2020
- 2020-12-30 CN CN202011603545.3A patent/CN112713161B/en active Active
- 2020-12-31 US US17/278,342 patent/US20240038793A1/en active Pending
- 2020-12-31 WO PCT/CN2020/142362 patent/WO2022141493A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714589A (en) * | 2008-10-01 | 2010-05-26 | 精工爱普生株式会社 | Photoelectric conversion element, photoeletric conversion device, and image sensor |
| CN105720063A (en) * | 2016-04-13 | 2016-06-29 | 京东方科技集团股份有限公司 | Array substrate and preparation method therefor, sensor and detection equipment |
| CN109686808A (en) * | 2018-12-27 | 2019-04-26 | 厦门天马微电子有限公司 | Diode and preparation method thereof, array substrate, display panel |
| CN110444553A (en) * | 2019-08-14 | 2019-11-12 | 京东方科技集团股份有限公司 | Photosensitive device and its manufacturing method, detection substrate and array substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022141493A1 (en) | 2022-07-07 |
| US20240038793A1 (en) | 2024-02-01 |
| CN112713161A (en) | 2021-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101621635B1 (en) | Array substrate and manufacturing method thereof and display device | |
| KR101710179B1 (en) | Flat panel display apparatus and manufacturing method of the same | |
| CN112713161B (en) | Array substrate and preparation method thereof | |
| WO2017128575A1 (en) | Manufacturing method for ltps array substrate | |
| CN103123910B (en) | Array base palte and manufacture method, display unit | |
| CN108735819B (en) | Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof and display substrate | |
| TWI284917B (en) | Circuit array substrate and method of manufacturing the same | |
| TW200407960A (en) | Method of forming a liquid crystal display | |
| TW200836347A (en) | Semiconductor device and manufacturing method thereof | |
| US20190027612A1 (en) | Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus | |
| CN112259556A (en) | Array substrate and preparation method thereof | |
| US20190371904A1 (en) | Thin film transistor and manufacturing method thereof, array substrate and display device | |
| US7176074B1 (en) | Manufacturing method of thin film transistor array substrate | |
| US10748944B2 (en) | Array substrate comprising transistor and capacitor, manufacturing method therefor, display device | |
| US20230163136A1 (en) | Display panel, array substrate, and manufacturing method thereof | |
| CN108511464A (en) | The production method of CMOS type LTPS TFT substrates | |
| KR100611759B1 (en) | CMOS Thin Film Transitor and Method of fabricating thereof | |
| TW201413825A (en) | Method of producing thin film transistor | |
| US10424605B2 (en) | Integrated gate driver | |
| CN110047800B (en) | Array substrate and preparation method thereof | |
| US10916641B2 (en) | Thin film transistor, method of manufacturing thin film transistor, and manufacturing system | |
| CN114005857A (en) | Array substrate, manufacturing method thereof and display device | |
| WO2011155127A1 (en) | Method for manufacturing semiconductor device | |
| CN108766935B (en) | Array substrate, preparation method thereof and display device | |
| TWI446458B (en) | Thin film transistor and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |