CN112713157A - Array substrate, display panel and preparation method of array substrate - Google Patents
Array substrate, display panel and preparation method of array substrate Download PDFInfo
- Publication number
- CN112713157A CN112713157A CN202011581390.8A CN202011581390A CN112713157A CN 112713157 A CN112713157 A CN 112713157A CN 202011581390 A CN202011581390 A CN 202011581390A CN 112713157 A CN112713157 A CN 112713157A
- Authority
- CN
- China
- Prior art keywords
- insulating layer
- layer
- substrate
- low
- array substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 110
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 24
- 239000001257 hydrogen Substances 0.000 claims abstract description 24
- -1 hydrogen ions Chemical class 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 260
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 75
- 229920005591 polysilicon Polymers 0.000 claims description 51
- 239000011229 interlayer Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 abstract description 15
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 239000003990 capacitor Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000001994 activation Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Abstract
The application provides an array substrate, a display panel and a preparation method of the array substrate, wherein the array substrate comprises: a substrate; a first insulating layer stacked on the substrate layer; a plurality of oxide transistors located on a side of the substrate where the first insulating layer is provided; wherein the first insulating layer contains hydrogen ions, and an orthographic projection of the oxide transistor on the substrate is staggered from an orthographic projection of the first insulating layer on the substrate. The design mode can prevent hydrogen ions in the first insulating layer from invading the oxide transistor in the subsequent high-temperature process and other processes, so that the stability of the oxide transistor can be improved.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate, a display panel and a preparation method of the array substrate.
Background
LTPO (low temperature polycrystalline silicon oxide) technology is a technology that combines LTPS (low temperature polycrystalline silicon) with IGZO (indium gallium zinc oxide); for example, some LTPS transistors in the pixel driving circuit may be replaced with IGZO transistors to realize low-frequency driving by using the characteristic that IGZO transistors have a small leakage current.
Because two transistors are used simultaneously, the film structure and the manufacturing process in the array substrate are relatively complex, conditions influencing the characteristics and the stability of the transistors are more, and especially the characteristics of the IGZO transistors are easily influenced.
Disclosure of Invention
The application provides an array substrate and a display panel to solve the technical problem that an oxide semiconductor layer of an oxide transistor is easy to be invaded by hydrogen ions.
In order to solve the technical problem, the application adopts a technical scheme that: provided is an array substrate including: a substrate; a first insulating layer stacked on the substrate layer; a plurality of oxide transistors located on a side of the substrate where the first insulating layer is provided; wherein the first insulating layer contains hydrogen ions, and an orthographic projection of the oxide transistor on the substrate is staggered from an orthographic projection of the first insulating layer on the substrate.
Wherein, still include: and the low-temperature polysilicon transistors are positioned on one side of the substrate, which is provided with the first insulating layer, and the orthographic projection of the low-temperature polysilicon transistors on the substrate is overlapped with the orthographic projection of the first insulating layer on the substrate.
In the direction far away from the substrate, the array substrate comprises a first gate insulating layer, a first insulating layer, a buffer layer and an interlayer insulating layer which are sequentially stacked, the first insulating layer comprises a hollow area, and the buffer layer fills at least part of the hollow area; at least part of the oxide transistor is located in the interlayer insulating layer and is arranged corresponding to the hollow-out region, and at least part of the low-temperature polycrystalline silicon transistor is located in the first gate insulating layer, the first insulating layer and the buffer layer.
The low-temperature polycrystalline silicon transistor adopts a top gate structure and comprises a low-temperature polycrystalline silicon layer, a first grid electrode, a first source electrode and a first drain electrode; the low-temperature polycrystalline silicon layer is positioned in the first grid insulation layer, the first grid is positioned in the first insulation layer above the low-temperature polycrystalline silicon layer, first holes are formed in the first insulation layer and the first grid insulation layer at positions corresponding to a source electrode region and a drain electrode region of the low-temperature polycrystalline silicon layer, and the first holes at corresponding positions are filled with the first source electrode and the first drain electrode respectively; or the low-temperature polycrystalline silicon transistor adopts a bottom gate structure and comprises a first grid electrode, a low-temperature polycrystalline silicon layer, a first source electrode and a first drain electrode; the first grid is positioned in the first grid insulating layer, the low-temperature polycrystalline silicon layer is positioned in the first insulating layer above the first grid, first holes are formed in the positions, corresponding to a source electrode region and a drain electrode region of the low-temperature polycrystalline silicon layer, of the first insulating layer, and the first holes in the corresponding positions are filled with the first source electrode and the first drain electrode respectively.
Wherein the oxide transistor includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode; the interlayer insulating layer contains hydrogen ions, the second grid electrode is located on the side, away from the buffer layer, of the oxide semiconductor layer, the second grid electrode and the oxide semiconductor layer are separated by the second grid electrode insulating layer, second holes are formed in the position, corresponding to a source electrode region and a drain electrode region of the oxide semiconductor layer, of the interlayer insulating layer, and the second source electrode and the second drain electrode respectively fill the second holes in the corresponding positions and respectively comprise portions located above the interlayer insulating layer.
The oxide transistor further comprises a third grid electrode, wherein the third grid electrode is arranged opposite to the oxide semiconductor layer and is positioned on the first grid electrode insulating layer exposed from the hollow area; preferably, the third gate, the first source and the second source are made of the same material.
Wherein, still include: the interlayer insulating layer and the buffer layer are provided with third holes corresponding to the first source electrode and the first drain electrode; the first connection electrode and the second connection electrode fill the third holes at corresponding positions, respectively, and include portions located above the interlayer insulating layer, respectively.
In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a display panel including: the array substrate according to any of the above embodiments; and the light emitting layer is positioned on one side of the array substrate and is used for emitting light under the driving of the array substrate.
In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a method for preparing an array substrate, including: forming a first insulating layer and a plurality of oxide transistors on one side of a substrate; wherein the first insulating layer contains hydrogen ions, and an orthographic projection of the oxide transistor on the substrate is staggered from an orthographic projection of the first insulating layer on the substrate.
Wherein the step of forming a first insulating layer and a plurality of oxide transistors on one side of the substrate comprises: forming a first insulating layer and a plurality of low-temperature polysilicon transistors on one side of the substrate; wherein at least a portion of the low temperature polysilicon transistor is located within the first insulating layer; forming a plurality of oxide transistors on the side, away from the substrate, of the first insulating layer; the first insulating layer is provided with a hollow area corresponding to the position of the oxide transistor, the first insulating layer is provided with a first hole corresponding to the positions of a first source electrode and a first drain electrode of the low-temperature polycrystalline silicon transistor, and the hollow area and the first hole are formed simultaneously.
Being different from the prior art situation, the beneficial effect of this application is: the first insulating layer rich in hydrogen ions in the array substrate and the orthographic projection of the oxide transistor on the substrate are arranged in a staggered mode, and the design mode can prevent the hydrogen ions in the first insulating layer from invading the oxide transistor in the subsequent high-temperature process and other process processes, so that the stability of the oxide transistor can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic structural diagram of an embodiment of an array substrate according to the present application;
FIG. 2 is a schematic structural diagram of another embodiment of an array substrate of the present application;
FIG. 3 is a schematic structural diagram of an embodiment of a pixel driving unit;
fig. 4 is a schematic structural diagram of an embodiment of a display panel according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In general, low temperature polysilicon transistors generally require activation, and therefore, materials such as hydrogen-rich silicon nitride need to be introduced into the surrounding inorganic insulating layer; the subsequent high temperature process makes hydrogen ions easily intrude into the oxide semiconductor layer of the oxide transistor, thereby causing the oxide transistor to fail.
To solve the above technical problem, please refer to fig. 1, in which fig. 1 is a schematic structural diagram of an embodiment of an array substrate according to the present application, the array substrate includes a substrate 10, a first insulating layer 12, and a plurality of oxide transistors 14 (only one is schematically shown in fig. 1); the substrate 10 may have flexibility, and a material thereof may be polyimide PI or the like. A first insulating layer 12, which is stacked on the substrate 10 and contains hydrogen ions, and may be made of silicon nitride or the like; the oxide transistor 14 is located on the side of the substrate 10 where the first insulating layer 12 is located, and the orthographic projection of the oxide transistor 14 on the substrate 10 and the orthographic projection of the first insulating layer 12 on the substrate 10 are staggered, so that the design mode can prevent hydrogen ions in the first insulating layer 12 from invading into the oxide transistor 14 in subsequent high-temperature process and other processes, and the stability of the oxide transistor 14 can be improved.
With reference to fig. 1, the array substrate provided by the present application further includes a plurality of low temperature polysilicon transistors 16 located on one side of the substrate 10 where the first insulating layer 12 is located, and an orthogonal projection of the low temperature polysilicon transistors 16 on the substrate 10 overlaps an orthogonal projection of the first insulating layer 12 on the substrate 10; for example, an orthographic projection of the first insulating layer 12 on the substrate 10 may cover at least a portion of an orthographic projection of the low temperature polysilicon transistor 16 on the substrate 10. This design may utilize hydrogen ions in the first insulating layer 12 to activate the low temperature polysilicon transistor 16 to improve its performance.
In the direction away from the substrate 10, the array substrate includes a first gate insulating layer 18, the above-mentioned first insulating layer 12, a first buffer layer 11, and an interlayer insulating layer 13, which are sequentially stacked, and the first insulating layer 12 includes a hollow-out region, and the first buffer layer 11 fills at least a portion of the hollow-out region (not labeled); at least a portion of the oxide transistor 14 is located in the interlayer insulating layer 13 and is disposed corresponding to the hollow region, and at least a portion of the low temperature polysilicon transistor 16 is located in the first gate insulating layer 18, the first insulating layer 12 and the first buffer layer 11. Optionally, in this embodiment, the array substrate may further include a plurality of capacitors 15 (only one capacitor is schematically illustrated in fig. 1), each capacitor 15 may include two oppositely disposed capacitor plates, one capacitor plate is located in the first insulating layer 12, and the other capacitor plate is located on the first insulating layer 12, where the first insulating layer 12 may be regarded as a capacitor insulating layer. The structure of the array substrate is simple, and the low-temperature polysilicon transistor 16 and the oxide transistor 14 are arranged in different layers, so that the design mode can reduce the process manufacturing cost and improve the yield; in addition, the oxide transistor 14 is disposed far from the substrate 10 relative to the low-temperature polysilicon transistor 16, which can effectively improve the reliability of the oxide transistor 14 and reduce loff and power consumption.
In one embodiment, as shown in FIG. 1, the low temperature polysilicon transistor 16 employs a top gate structure; specifically, the low-temperature polysilicon transistor 16 includes a low-temperature polysilicon layer 160, a first gate 162, a first source 164, and a first drain 166; wherein the low-temperature polysilicon layer 160 is located in the first gate insulating layer 18, and the first gate 162 is located in the first insulating layer 12 above the low-temperature polysilicon layer 160, for example, the position of the first gate 162 may correspond to a channel region located in the middle of the low-temperature polysilicon layer 160; first holes (not shown) are formed in the first insulating layer 12 and the first gate insulating layer 18 at positions corresponding to source regions (not shown) and drain regions (not shown) on both sides of the low-temperature polysilicon layer 160, and the first source electrode 164 and the first drain electrode 166 fill the first holes at the corresponding positions, respectively. Further, in the present embodiment, the first source electrode 164 and the first drain electrode 166 may further include a portion located in the first buffer layer 11 above the low temperature polysilicon layer 160, respectively, and the portion may be used as a connection region for electrically connecting with other electrical structures.
Of course, in other embodiments, the low temperature polysilicon transistor 16a may also be a bottom gate structure. For example, as shown in fig. 2, fig. 2 is a schematic structural diagram of another embodiment of the array substrate of the present application. The low temperature polysilicon transistor 16a also includes a first gate 162a, a low temperature polysilicon layer 160a, a first source 164a and a first drain 166 a; the first gate 162a is located in the first gate insulating layer 18a, the low-temperature polysilicon layer 160a is located in the first insulating layer 12a above the first gate 162a, first holes (not labeled) are disposed in the first insulating layer 12a at positions corresponding to a source region (not labeled) and a drain region (not labeled) of the low-temperature polysilicon layer 160a, and the first holes at corresponding positions are filled with the first source 164a and the first drain 166a, respectively; further, in the present embodiment, the first source electrode 164a and the first drain electrode 166a may further include a portion in the first buffer layer 11a above the low-temperature polysilicon layer 160a, respectively, and the portion may be used as a connection region for electrically connecting with other electrical structures.
Regardless of the top gate or bottom gate structure, the structure of the low temperature polysilicon transistor 16a is simpler, and the depth of the first hole filled by the first source 164/164a and the first drain 166/166a is smaller, for example, the depth of the first hole is generally less than 1 micron, so as to reduce the difficulty of dry etching and reduce the probability of poor dry etching.
Alternatively, the first holes in the two embodiments may be formed simultaneously with the hollowed-out regions on the first insulating layer 12/12 a. For example, a half-tone mask process may be used to expose the first insulating layer 12/12a to remove the first insulating layer 12/12a at the position where the oxide transistor 14 is to be formed, so as to form the above-mentioned hollow region; meanwhile, the blocking material at the source region and the drain region of the low temperature polysilicon transistor 16 may also be removed, thereby forming the first hole. The design method can reduce the manufacturing cost and the process time.
Correspondingly, the low temperature polysilicon transistor 16 of either the bottom gate or top gate structure described above may be combined with the oxide transistor 14 of the structure described below. With reference to fig. 1, the oxide transistor 14 includes an oxide semiconductor layer 140, a second gate 142, a second source 144 and a second drain 146; the interlayer insulating layer 13 contains hydrogen ions, and the hydrogen ions in the interlayer insulating layer 13 contribute to the activation process of the lower low-temperature polysilicon transistor 16. The second gate electrode 142 is positioned on a side of the oxide semiconductor layer 140 facing away from the first buffer layer 11, and the second gate electrode 142 and the oxide semiconductor layer 140 are spaced apart by the second gate insulating layer 17, and the position of the second gate electrode 142 may correspond to a channel region in the middle of the oxide semiconductor layer 140. A second hole (not shown) is formed in the interlayer insulating layer 13 at a position corresponding to a source region (not shown) and a drain region (not shown) of the oxide semiconductor layer 140, and the second source 144 and the second drain 146 fill the second hole at the corresponding positions and respectively include a portion located above the interlayer insulating layer 13, which can be used as a connection region for electrically connecting other electrical structures. The oxide transistor 14 corresponds to a top gate structure, and since the interlayer insulating layer 13 contains hydrogen ions, the second gate electrode 142 in the top gate structure can also function to block hydrogen ions from invading the oxide semiconductor layer 140 directly below the top gate structure, so as to further improve the stability of the oxide semiconductor layer 140.
Of course, in other embodiments, the oxide transistor 14 may also have a dual-gate structure, and the oxide transistor 14 having the dual-gate structure has the advantages of high input impedance, low power consumption for voltage control, simple control circuit, high voltage resistance, large current tolerance, and the like. Specifically, with reference to fig. 1, the oxide transistor 14 may further include a third gate 148 in addition to the above-mentioned oxide semiconductor layer 140, the second gate 142, the second source 144 and the second drain 146, wherein the third gate 148 is disposed opposite to the oxide semiconductor layer 140 and is located on the first gate insulating layer 18 exposed from the hollow region of the first insulating layer 12.
Alternatively, the third gate 148 and the first and second sources 164 and 166 of the low temperature polysilicon transistor 16 may be formed simultaneously and have the same material. For example, the third gate 148, the first source 164 and the second source 166 may be formed simultaneously by depositing a second metal layer M2 on the first insulating layer 12 and the first gate insulating layer 18 exposed from the first insulating layer 12 and then etching the second metal layer M2. Of course, the other capacitor plate of the capacitor 15 can also be formed at the same time. The design method can save the process time.
In addition, since the low temperature polysilicon transistor 16 is disposed close to the substrate 10 with respect to the oxide transistor 14, in order to facilitate electrical connection between the low temperature polysilicon transistor 16 and the oxide transistor 14, as shown in fig. 1, the array substrate further includes a first connection electrode 190 and a second connection electrode 192; third holes (not shown) are formed in the interlayer insulating layer 13 and the first buffer layer 11 at positions corresponding to the first source 164 and the first drain 166 of the low temperature polysilicon transistor 16; the first and second connection electrodes 190 and 192 fill the third holes at corresponding positions, respectively, and include portions above the interlayer insulating layer 13, respectively.
Optionally, the first connection electrode 190, the second connection electrode 192, the second source 144 and the second drain 146 are made of the same material and are formed at the same time, which can reduce the difficulty and time of the manufacturing process. For example, the interlayer insulating layer 13 may be exposed and dry-etched twice to form the second hole and the third hole, respectively; then, after the film formation of the fourth metal layer M4 is completed on the interlayer insulating layer 13, a portion of the fourth metal layer M4 is etched away to simultaneously form the first connection electrode 190, the second connection electrode 192, the second source electrode 144, and the second drain electrode 146.
In addition, a plurality of pixel driving units may be included in the array substrate, each pixel driving unit is used to drive a corresponding light emitting unit to emit light, and the transistor generally electrically connected to the anode of the light emitting unit is the low temperature polysilicon transistor 16, and at this time, as shown in fig. 1, a third connection electrode 194 may be further introduced on a portion of the low temperature polysilicon transistor 16; at this time, the array substrate further includes a passivation layer 20 and a first planarization layer 22, which are stacked, wherein the passivation layer 20 is located between the first planarization layer 22 and the interlayer insulating layer 13, a fourth hole is formed in a position of the passivation layer 20 and a portion of the first planarization layer 22 corresponding to the second connection electrode 192, and the third connection electrode 194 fills the fourth hole and includes a portion located on the surface of the first planarization layer 22.
In one embodiment, the pixel driving unit in the array substrate may be a 5T1C driving circuit, a 6T1C driving circuit, a 7T1C driving circuit, a 7T2C driving circuit, and the like. Each of the pixel driving units may respectively include:
the power supply unit is used for receiving the light-emitting enable signal EM and providing a power supply signal for the corresponding light-emitting unit according to the light-emitting enable signal; specifically, as shown in fig. 3, fig. 3 is a schematic structural diagram of an embodiment of a pixel driving unit; when the pixel driving unit has a 7T1C circuit structure, the power supply unit includes switching transistors T3 and T5, and control terminals of T3 and T5 receive the light emission enable signal EM.
The writing unit receives the scanning signal Sn of the current stage and writes a driving signal Vdata under the driving of the scanning signal Sn of the current stage; specifically, as shown in fig. 3, the driving signal writing unit includes switching transistors T2, T4, and T7.
A driving unit connected to the writing unit and the power supply unit to generate a driving current matching the driving signal Vdata using a power signal Vdd according to the written driving signal Vdata, thereby driving the light emitting unit using the driving current; specifically, as shown in fig. 3, the driving unit includes a driving transistor T1.
The initialization unit receives the previous scanning signal Sn-1, receives the reference signal Vref under the driving of the previous scanning signal Sn-1, and initializes the driving unit and the light-emitting unit by using the reference signal Vref; specifically, as shown in fig. 3, the initialization unit includes a switching transistor T6.
At least part of the thin film transistors in the initialization unit and/or the writing unit are oxide transistors, and the rest thin film transistors in the pixel driving unit are low-temperature polysilicon transistors. For example, T4 and T6 in the pixel driving unit in fig. 3 are designed as oxide transistors 14, and T1, T2, T3, T5, T7 are designed as low temperature polysilicon transistors 16. Since the leakage current of the oxide transistor 14 is small, the T4 and the T6 respectively correspond to the gate data signal writing and gate resetting functions, and the display effect can be improved and the low-frequency driving can be realized by adopting the above design mode.
The array substrate provided in the present application is further described below in terms of a manufacturing method. Referring to fig. 1, the preparation process of the array substrate provided by the present application may include: forming a first insulating layer 12 and a plurality of oxide transistors 14 on one side of a substrate 10; the first insulating layer 12 contains hydrogen ions, and an orthographic projection of the oxide transistor 14 on the substrate 10 is offset from an orthographic projection of the first insulating layer 12 on the substrate 10.
In this embodiment, the array substrate further includes a plurality of low temperature polysilicon transistors 16, and the step of forming the first insulating layer 12 and the plurality of oxide transistors 14 on one side of the substrate 10 specifically includes: forming a first insulating layer 12 and a plurality of low temperature polysilicon transistors 16 on one side of a substrate 10; wherein at least a portion of the low temperature polysilicon transistor 16 is located within the first insulating layer 12; forming a plurality of oxide transistors 14 on a side of the first insulating layer 12 facing away from the substrate 10; a hollow-out region is disposed at a position of the first insulating layer 12 corresponding to the oxide transistor 14, a first hole is disposed at a position of the first insulating layer 12 corresponding to the first source 164 and the first drain 166 of the low temperature polysilicon transistor 16, and the hollow-out region and the first hole are formed at the same time. In this design, the oxide transistor 14 is disposed far from the substrate 10 relative to the low-temperature polysilicon transistor 16, which can effectively improve the reliability of the oxide transistor 14 and reduce loff and power consumption; and the hollow area and the first hole are formed simultaneously in the design mode, so that the cost of the preparation process can be reduced.
In a specific application scenario, the preparation process of the array substrate provided in the present application is specifically as follows:
A. forming a second buffer layer 24 on one side of the substrate 10;
B. forming a polysilicon semiconductor layer 160 on a partial region of the second buffer layer 24 on the side facing away from the substrate 10;
C. forming a first gate insulating layer 18 on a side of the second buffer layer 24 away from the substrate 10, and covering the polysilicon semiconductor layer 160 on the first gate insulating layer 18; the material of the first gate insulating layer 18 may be a material that does not contain hydrogen ions, such as silicon oxide.
D. Forming a first metal layer M1 on the first gate insulating layer 18, and patterning the first metal layer M1 to form the first gate 162 and one of the electrode plates of the capacitor 15;
E. depositing a first insulating layer 12 on the first gate insulating layer 18, wherein the first metal layer M1 is covered by the first insulating layer 12, and the material of the first insulating layer 12 may be a material containing hydrogen ions, such as silicon nitride; simultaneously removing the first insulating layer 12 at the position of the oxide transistor 14 to be formed, and the first insulating layer 12 and the first gate insulating layer 18 at the positions of the source region and the drain region of the low-temperature polysilicon layer 160 (i.e., forming a first hole) by using a half-tone mask process;
F. depositing a second metal layer M2 on the first gate insulating layer 18 and the first insulating layer 12, and patterning the second metal layer M2 to form the third gate 148 of the oxide transistor 14, the first source 164 and the first drain 166 of the low temperature polysilicon transistor 16;
G. forming a first buffer layer 11 on the first gate insulating layer 18 and the first insulating layer 12; the material of the first buffer layer 11 may be silicon oxide containing no hydrogen ions.
H. Forming an oxide semiconductor layer 140 on the first buffer layer 11, and forming a second gate insulating layer 17 and a second gate electrode 142 on the oxide semiconductor layer 140;
I. forming an interlayer insulating layer 13 on the first buffer layer 11, the interlayer insulating layer 13 covering the second gate electrode 142;
J. the exposure and dry etching processes are performed twice to form a second hole in the interlayer insulating layer 13 at a position corresponding to the source region and the drain region of the oxide semiconductor layer 140, and a third hole in the interlayer insulating layer 13 and the first buffer layer 11 at a position corresponding to the first source 164 and the first drain 166, respectively.
K. Forming a fourth metal layer M4 on the interlayer insulating layer, and patterning the fourth metal layer M4 to form the first connection electrode 190, the second connection electrode 192, the second source electrode 144, and the second drain electrode 146;
l, forming a passivation layer 20 and a first planarization layer 22 on the interlayer insulating layer 13, and removing a portion of the passivation layer 20 and the first planarization layer 22 at the position of the second connection electrode 192 to form a fourth hole;
m, a fifth metal layer M5 is formed on the first planarization layer, and the fifth metal layer M5 is patterned to form a third connection electrode 194.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of a display panel of the present application, which may be an OLED display panel or the like, and which may include the array substrate 30 and the light-emitting layer 32 mentioned in any of the above embodiments; the light emitting layer 32 is located on one side of the array substrate 30 and is used for emitting light under the driving action of the array substrate 30.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.
Claims (10)
1. An array substrate, comprising:
a substrate;
a first insulating layer stacked on the substrate layer;
a plurality of oxide transistors located on a side of the substrate where the first insulating layer is provided;
wherein the first insulating layer contains hydrogen ions, and an orthographic projection of the oxide transistor on the substrate is staggered from an orthographic projection of the first insulating layer on the substrate.
2. The array substrate of claim 1, further comprising:
and the low-temperature polysilicon transistors are positioned on one side of the substrate, which is provided with the first insulating layer, and the orthographic projection of the low-temperature polysilicon transistors on the substrate is overlapped with the orthographic projection of the first insulating layer on the substrate.
3. The array substrate of claim 2,
in the direction far away from the substrate, the array substrate comprises a first gate insulating layer, a first insulating layer, a buffer layer and an interlayer insulating layer which are sequentially stacked, the first insulating layer comprises a hollow area, and at least part of the hollow area is filled with the buffer layer;
at least part of the oxide transistor is located in the interlayer insulating layer and is arranged corresponding to the hollow-out region, and at least part of the low-temperature polycrystalline silicon transistor is located in the first gate insulating layer, the first insulating layer and the buffer layer.
4. The array substrate of claim 3,
the low-temperature polycrystalline silicon transistor adopts a top gate structure and comprises a low-temperature polycrystalline silicon layer, a first grid electrode, a first source electrode and a first drain electrode; the low-temperature polycrystalline silicon layer is positioned in the first grid insulation layer, the first grid is positioned in the first insulation layer above the low-temperature polycrystalline silicon layer, first holes are formed in the first insulation layer and the first grid insulation layer at positions corresponding to a source electrode region and a drain electrode region of the low-temperature polycrystalline silicon layer, and the first holes at corresponding positions are filled with the first source electrode and the first drain electrode respectively; alternatively, the first and second electrodes may be,
the low-temperature polycrystalline silicon transistor adopts a bottom gate structure and comprises a first gate, a low-temperature polycrystalline silicon layer, a first source electrode and a first drain electrode; the first grid is positioned in the first grid insulating layer, the low-temperature polycrystalline silicon layer is positioned in the first insulating layer above the first grid, first holes are formed in the positions, corresponding to a source electrode region and a drain electrode region of the low-temperature polycrystalline silicon layer, of the first insulating layer, and the first holes in the corresponding positions are filled with the first source electrode and the first drain electrode respectively.
5. The array substrate of claim 4,
the oxide transistor includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode;
the interlayer insulating layer contains hydrogen ions, the second grid electrode is located on the side, away from the buffer layer, of the oxide semiconductor layer, the second grid electrode and the oxide semiconductor layer are separated by the second grid electrode insulating layer, second holes are formed in the position, corresponding to a source electrode region and a drain electrode region of the oxide semiconductor layer, of the interlayer insulating layer, and the second source electrode and the second drain electrode respectively fill the second holes in the corresponding positions and respectively comprise portions located above the interlayer insulating layer.
6. The array substrate of claim 5,
the oxide transistor further comprises a third grid electrode, wherein the third grid electrode is arranged opposite to the oxide semiconductor layer and is positioned on the first grid electrode insulating layer exposed from the hollow area;
preferably, the third gate, the first source and the second source are made of the same material.
7. The array substrate of claim 3, further comprising:
the interlayer insulating layer and the buffer layer are provided with third holes corresponding to the first source electrode and the first drain electrode; the first connection electrode and the second connection electrode fill the third holes at corresponding positions, respectively, and include portions located above the interlayer insulating layer, respectively.
8. A display panel, comprising:
an array substrate of any one of claims 1-7;
and the light emitting layer is positioned on one side of the array substrate and is used for emitting light under the driving of the array substrate.
9. A preparation method of an array substrate is characterized by comprising the following steps:
forming a first insulating layer and a plurality of oxide transistors on one side of a substrate; wherein the first insulating layer contains hydrogen ions, and an orthographic projection of the oxide transistor on the substrate is staggered from an orthographic projection of the first insulating layer on the substrate.
10. The method according to claim 9, wherein the step of forming a first insulating layer and a plurality of oxide transistors on the substrate side comprises:
forming a first insulating layer and a plurality of low-temperature polysilicon transistors on one side of the substrate; wherein at least a portion of the low temperature polysilicon transistor is located within the first insulating layer;
forming a plurality of oxide transistors on the side, away from the substrate, of the first insulating layer; the first insulating layer is provided with a hollow area corresponding to the position of the oxide transistor, the first insulating layer is provided with a first hole corresponding to the positions of a first source electrode and a first drain electrode of the low-temperature polycrystalline silicon transistor, and the hollow area and the first hole are formed simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011581390.8A CN112713157A (en) | 2020-12-28 | 2020-12-28 | Array substrate, display panel and preparation method of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011581390.8A CN112713157A (en) | 2020-12-28 | 2020-12-28 | Array substrate, display panel and preparation method of array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112713157A true CN112713157A (en) | 2021-04-27 |
Family
ID=75545858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011581390.8A Pending CN112713157A (en) | 2020-12-28 | 2020-12-28 | Array substrate, display panel and preparation method of array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112713157A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022241834A1 (en) * | 2021-05-21 | 2022-11-24 | 武汉华星光电半导体显示技术有限公司 | Display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104867921A (en) * | 2014-02-24 | 2015-08-26 | 乐金显示有限公司 | Thin Film Transistor Substrate And Display Using The Same |
| US20160087022A1 (en) * | 2014-09-24 | 2016-03-24 | Apple Inc. | Silicon and Semiconducting Oxide Thin-Film Transistor Displays |
| CN106935549A (en) * | 2017-03-20 | 2017-07-07 | 昆山工研院新型平板显示技术中心有限公司 | The preparation method and thin-film transistor array base-plate of thin-film transistor array base-plate |
| CN109300915A (en) * | 2018-09-30 | 2019-02-01 | 厦门天马微电子有限公司 | A kind of array substrate, display panel and display device |
| CN110649044A (en) * | 2019-09-30 | 2020-01-03 | 厦门天马微电子有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| US20200395488A1 (en) * | 2019-06-14 | 2020-12-17 | Tianma Japan, Ltd. | Thin-film device |
-
2020
- 2020-12-28 CN CN202011581390.8A patent/CN112713157A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104867921A (en) * | 2014-02-24 | 2015-08-26 | 乐金显示有限公司 | Thin Film Transistor Substrate And Display Using The Same |
| US20160087022A1 (en) * | 2014-09-24 | 2016-03-24 | Apple Inc. | Silicon and Semiconducting Oxide Thin-Film Transistor Displays |
| CN106935549A (en) * | 2017-03-20 | 2017-07-07 | 昆山工研院新型平板显示技术中心有限公司 | The preparation method and thin-film transistor array base-plate of thin-film transistor array base-plate |
| CN109300915A (en) * | 2018-09-30 | 2019-02-01 | 厦门天马微电子有限公司 | A kind of array substrate, display panel and display device |
| US20200395488A1 (en) * | 2019-06-14 | 2020-12-17 | Tianma Japan, Ltd. | Thin-film device |
| CN110649044A (en) * | 2019-09-30 | 2020-01-03 | 厦门天马微电子有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022241834A1 (en) * | 2021-05-21 | 2022-11-24 | 武汉华星光电半导体显示技术有限公司 | Display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110649043B (en) | Array substrate, display panel, display device and preparation method of array substrate | |
| CN110114885B (en) | Display substrate, preparation method thereof and display panel | |
| TWI425634B (en) | Organic light emitting display device and fabricating method thereof | |
| CN112289945B (en) | Display panel and manufacturing method thereof | |
| US20100182223A1 (en) | Organic light emitting display device | |
| CN109326624B (en) | Pixel circuit, manufacturing method thereof and display device | |
| CN104716156A (en) | Organic light emitting display device and manufacturing method thereof | |
| US10943984B2 (en) | Thin film transistor and manufacturing method thereof, display substrate and manufacturing method thereof, and display device | |
| KR20070074594A (en) | Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes | |
| CN111710685B (en) | Display panel, manufacturing method thereof and display device | |
| CN111725250A (en) | Array substrate, preparation method thereof and display panel | |
| WO2022179142A1 (en) | Display panel and manufacturing method therefor, and display device | |
| CN112713157A (en) | Array substrate, display panel and preparation method of array substrate | |
| US20080054268A1 (en) | Display device and method of manufacturing the display device | |
| KR100793105B1 (en) | Thin film transistor and flat panel display with the thin film transistor and fabrication method of the same | |
| CN112736092B (en) | Array substrate, preparation method thereof and display panel | |
| CN112289813B (en) | Array substrate, display panel and display device | |
| TWI703735B (en) | Semiconductor substrate, array substrate, inverter circuit, and switch circuit | |
| CN110649003A (en) | Semiconductor substrate, array substrate, inverter circuit, and switching circuit | |
| CN114267687B (en) | Array substrate and display panel | |
| CN220829962U (en) | Array substrate and display device | |
| JP2004272293A (en) | Electro-optical device | |
| CN112820743B (en) | Display panel, manufacturing method thereof and display device | |
| WO2022257081A9 (en) | Display panel and manufacturing method therefor, and display device | |
| WO2023231004A9 (en) | Display panel and manufacturing method therefor, and display apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |