CN112713101B - Overlay error compensation method for capacitor opening layer - Google Patents
Overlay error compensation method for capacitor opening layer Download PDFInfo
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- CN112713101B CN112713101B CN201911015756.2A CN201911015756A CN112713101B CN 112713101 B CN112713101 B CN 112713101B CN 201911015756 A CN201911015756 A CN 201911015756A CN 112713101 B CN112713101 B CN 112713101B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/7065—Defects, e.g. optical inspection of patterned layer for defects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
The invention relates to an overlay error compensation method of a capacitor opening layer, which comprises the steps of obtaining a contour picture of a test area of devices in a current batch; acquiring an alignment error between a capacitance opening layer of the test area and the capacitance layer according to the profile picture; and back-compensating and exposing the capacitor opening layer of the next batch of devices through the overlay error of the current batch of devices. The invention realizes effective feedback and regulation of the manufacturing process of the capacitor opening hole and improves the yield of qualified devices of the capacitor opening layer by acquiring the overlay error of the devices of the current batch and carrying out back-up exposure on the devices of the next batch based on the overlay error.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to an alignment error compensation method for a capacitor opening layer.
Background
With the continuous reduction of the size of the semiconductor device, the requirement on the processing precision of the device is higher and higher, and after each process is completed, the critical dimension of the process needs to be checked, and the defect point is found as early as possible so as to be corrected in time. In the prior art, the critical dimension of a pattern is usually measured using a critical dimension scanning electron microscope (CD-SEM) in order to find the defect points present in the pattern.
A Dynamic Random Access Memory (DRAM) needs to have a Memory capacitor in a device structure, and the Memory capacitor is controlled by a transistor and stores data by storing charges. When the memory capacitor is manufactured, a sacrificial layer and a supporting layer are deposited on the surface of a substrate, capacitor holes penetrating through the sacrificial layer and the supporting layer are formed through a two-step photoetching process, a lower electrode layer is formed on the surfaces of the capacitor holes, capacitor opening holes capable of being communicated with a plurality of capacitor holes are formed, an acid washing solution is injected into the capacitor opening holes to remove the sacrificial layer material, and finally a dielectric layer and an upper electrode layer are formed to jointly form the memory capacitor.
The connection quality of the capacitor hole is determined by the position of the capacitor opening hole, and the connection quality plays an important role in improving the effect and yield of the subsequent pickling process. In the traditional manufacturing process, a technician only tests and evaluates the position of the capacitor opening hole after the capacitor opening hole is formed, and the forming process of the capacitor opening hole is not controlled, so that the capacitor opening hole with the position not meeting the specification requirement consumes a large amount of manufacturing cost, and the yield of qualified devices on the capacitor opening layer is insufficient, so that the method for compensating the alignment error of the capacitor opening layer is urgently needed to be provided.
Disclosure of Invention
Therefore, it is necessary to provide a method for compensating the overlay error of the capacitor opening layer for the problem of insufficient yield of the qualified devices of the capacitor opening layer in the conventional manufacturing process.
In order to realize the purpose of the invention, the invention adopts the following technical scheme:
an overlay error compensation method for a capacitor opening layer comprises the following steps:
obtaining a profile picture of a test area of the devices in the current batch, wherein at least one capacitor opening hole and a plurality of capacitor holes which are designed to be communicated by the capacitor opening hole are formed in the test area;
defining a layer where the capacitor opening holes are located as a capacitor opening layer, defining layers where the plurality of capacitor holes are located as capacitor layers, and acquiring an alignment error between the capacitor opening layer of the test area and the capacitor layers according to the profile picture;
and back-compensating and exposing the capacitor opening layer of the next batch of devices through the overlay error of the current batch of devices.
In one embodiment, the capacitance opening hole and the plurality of capacitance holes designed to communicate with the capacitance opening hole are defined as a capacitance hole combination, the deviation between the actual position and the designed position of the capacitance opening hole in one capacitance hole combination is defined as a single set error,
the method comprises the following steps that the outline picture of the test area comprises at least two capacitor hole combinations, and the step of acquiring the overlay error between the capacitor opening layer and the capacitor layer of the test area comprises the following steps:
acquiring single group errors of at least two capacitor hole combinations in the test area;
and calculating the average value of at least two single group errors, and defining the average value as the overlay error of the test area.
In one embodiment, in the step of obtaining a single set of error of at least two capacitor hole combinations in the test area, the at least two capacitor hole combinations are respectively disposed at a center position or a corner position of the test area, and the positions of the capacitor hole combinations in the test area are distributed symmetrically.
In one embodiment, after the step of obtaining the overlay error between the capacitance opening layer of the test area and the capacitance layer, the method further includes the following steps:
presetting an error threshold;
and comparing the overlay error with the error threshold, and judging that the area with the overlay error larger than the error threshold is an unqualified area of the device.
In one embodiment, the step of back-exposing the capacitor open layer of the next batch of devices through the overlay error of the current batch of devices includes:
acquiring an overlay error of the devices in the current batch of each test area;
and exposing and compensating the capacitor opening layer of the next batch of devices in the corresponding test area according to the overlay error.
In one embodiment, after the step of obtaining the overlay error of the current batch of devices of each test area, the method further includes the following steps:
and drawing an overlay error wafer graph of the devices in the current batch.
In one embodiment, the step of exposing and compensating the capacitor open layer of the next batch of devices in the corresponding test region according to the overlay error comprises:
coating photoresist on the surface of the substrate of the next batch of devices;
adjusting the position of a photomask during exposure of the corresponding test area of the next batch of devices according to the overlay error of the current batch of devices in the test area;
the next batch of devices is exposed, developed and etched to form the capacitance opening layer.
In one embodiment, the adjustment distance of the mask position of the next lot of devices is the same as the value of the overlay error of the current lot of devices, and the adjustment direction is opposite to the direction of the overlay error of the current lot of devices.
In one embodiment, one of the capacitor hole combinations includes one capacitor opening hole and three capacitor holes, and a center position of the capacitor opening hole is designed to be the same distance as a center position of each capacitor hole.
In one embodiment, a connection line direction between the positioning groove and the center of the wafer is defined as a Y direction, a direction perpendicular to the Y direction is defined as an X direction, and the overlay error includes an X direction error and a Y direction error.
The alignment error compensation method of the capacitor opening layer comprises the steps of obtaining a contour picture of a test area of a current batch of devices; acquiring an alignment error between a capacitance opening layer of the test area and the capacitance layer according to the profile picture; and compensating and exposing the capacitor opening layer of the devices of the next batch through the overlay error of the devices of the current batch. The invention realizes effective feedback and regulation of the manufacturing process of the capacitor opening hole and improves the yield of qualified devices of the capacitor opening layer by acquiring the overlay error of the devices of the current batch and carrying out back-up exposure on the devices of the next batch based on the overlay error.
Drawings
FIG. 1 is a flow chart illustrating a method for compensating for overlay error of a capacitor opening layer in an embodiment;
FIG. 2 is a schematic design diagram of a test area in an example;
FIG. 3 is a schematic design diagram of a test area in another example;
FIG. 4 is a schematic view of a profile picture of a test area in an example;
FIG. 5 is a schematic view of a profile picture of a test area in another example;
FIG. 6 is a diagram of a single set of errors in an embodiment;
FIG. 7 is a sub-flowchart of step S200 in the embodiment of FIG. 1;
FIG. 8 is a diagram illustrating an exemplary selected capacitor hole combination;
FIG. 9 is a schematic view of a test area in one embodiment;
FIG. 10 is a sub-flowchart of step S300 in the embodiment of FIG. 1;
fig. 11 is a sub-flowchart of step S320 in the embodiment of fig. 10.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Fig. 1 is a flowchart of an alignment error compensation method for a capacitive opening layer in an embodiment, where as shown in fig. 1, the alignment error compensation method for the capacitive opening layer includes:
s100: acquiring a profile picture of a test area of the current batch of devices,
s200: acquiring an alignment error between a capacitance opening layer of the test area and the capacitance layer according to the profile picture;
s300: and back-compensating and exposing the capacitor opening layer of the next batch of devices through the overlay error of the current batch of devices.
In the S100 step, the test area is formed with at least one capacitance opening hole 200 and a plurality of capacitance holes 100 designed to be communicated with the capacitance opening hole 200, and the capacitance opening hole 200 and the plurality of capacitance holes 100 designed to be communicated with the capacitance opening hole 200 are defined as one capacitance hole combination 300. Fig. 2 to 3 are schematic design views of test regions in two examples, and as shown in fig. 2, one capacitor hole combination 300 includes one capacitor opening hole 200 and three capacitor holes 100, and a central position of the capacitor opening hole 200 is designed to be the same distance from a central position of each capacitor hole 100; as shown in fig. 3, one capacitor opening hole combination 300 includes one capacitor opening hole 200 and six capacitor holes 100, and the center position of the capacitor opening hole 200 is the same as the center position of the overall pattern formed by the six capacitor opening holes 200. It should be noted that the alignment error compensation method for the capacitive opening layer in this embodiment is applicable to capacitive opening holes 200 with different shapes and different sizes, and is not limited to the above two examples.
Fig. 4 to 5 are schematic diagrams of profile pictures of the test areas in the two previous examples, in this embodiment, a scanning electron microscope is used to obtain the coordinate positions and the critical dimensions of the capacitor holes 100 and the capacitor opening holes 200 in the subsequent steps, as shown in fig. 4 to 5, there is a certain deviation between the actual positions of the capacitor opening holes 200 and the design positions, when the positions of the capacitor opening holes 200 are deviated, the contact areas of each capacitor hole 100 and the pickling solution are different, and the corresponding pickling speeds are also different, and if the difference between the pickling speeds of different capacitor holes 100 is too large, the pickling quality of the device is further affected.
The number of the capacitor holes 100 determines the data storage capacity of the DRAM chip device, and therefore a large number of the capacitor holes 100 are designed in one DRAM chip. Defining the layer where the capacitor opening holes 200 are located as a capacitor opening layer, defining the layer where the plurality of capacitor holes 100 are located as a capacitor layer, and defining the deviation between the actual position 220 and the design position 210 of the capacitor opening hole 200 in one capacitor hole combination 300 as a single group error. As shown in fig. 6, a dotted circular area is a design position 210 of the capacitor opening hole 200, a dashed circular area is an actual position 220 of the capacitor opening hole 200, and a distance OVL between a center of the actual position 220 and a center of the design position 210 is the single set error. In one embodiment, in step S200, one of the capacitor hole combinations 300 in the test area is selected, and the single group error of the capacitor hole combination 300 is the overlay error of the test area.
In another embodiment, the outline picture of the test area includes at least two capacitor hole combinations 300, as shown in fig. 7, in the step S200, the following steps are included:
s210: acquiring a single set of errors of at least two capacitor hole combinations 300 in the test area;
s220: and calculating the average value of at least two single group errors, and defining the average value as the overlay error of the test area.
If only one capacitor hole combination 300 is selected, when the capacitor hole combination 300 has a defect not existing in other capacitor hole combinations 300 during the manufacturing process, an overlay error evaluation error of the test area may be caused, and the subsequent benefit exposure effect may be affected. This problem of evaluation error can be effectively prevented by selecting at least two of the capacitance hole combinations 300 and calculating a single set of error averages. In an example, the at least two capacitor hole assemblies 300 are respectively disposed at the center position or the corner position of the test area, and the position distribution of the selected capacitor hole assemblies 300 in the test area is a symmetric distribution, as shown in fig. 8, the capacitor hole assemblies 300 filled with oblique lines are the capacitor hole assemblies 300 selected in the test area, and the single group error of each capacitor hole assembly 300 obtained by the test is OVL1, OVL2, and OVL3, respectively, so that the overlay error OVL of the test area is (OVL1+ OVL2+ OVL3)/3, and by the selection manner of the capacitor hole assemblies 300, a more stable and accurate overlay error test result can be obtained.
In an embodiment, after the step of obtaining the overlay error between the capacitance opening layer of the test area and the capacitance layer, the method further includes the following steps: presetting an error threshold; and comparing the overlay error with the error threshold, and judging that the area with the overlay error larger than the error threshold is an unqualified area of the device. The devices in the current batch are divided according to the test result of the overlay error, so that the workload of manufacturing and testing in the subsequent steps can be reduced. If the overlay error of a test area does not meet the requirement of an error threshold and cannot be compensated in the subsequent process, the DRAM chip device meeting the specification requirement cannot be formed in the unqualified area of the device, so that the area can be skipped in the subsequent test step, and the test speed and the test efficiency of the device are improved.
In an embodiment, the wafer is divided into a plurality of test areas, as shown in fig. 9, each small square is one test area, and each test area is adjacently disposed, as shown in fig. 10, in the step S300, the method includes the following steps:
s310: acquiring the overlay error of the devices in the current batch in each test area;
s320: and exposing and compensating the capacitor opening layer of the next batch of devices in the corresponding test area according to the overlay error.
In an embodiment, after the step of obtaining the overlay error of the current batch of devices in each test area, the method further includes a step of drawing an overlay error wafer map of the current batch of devices, so that a technician can visually evaluate the overlay error of the current batch of wafers through the wafer map.
In an embodiment, as shown in fig. 11, in the step S320, the following steps are included:
s321: coating photoresist on the surface of the substrate of the next batch of devices;
s322: adjusting the position of a photomask during exposure of the corresponding test area of the next batch of devices according to the overlay error of the current batch of devices in the test area;
s323: the next batch of devices is exposed, developed and etched to form the capacitance opening layer.
In step S321, a photoresist is coated on the surface of the substrate by a spin coating or doctor blade coating process, and the device is baked at a suitable temperature to remove the solvent in the device, thereby improving the hardness and stability of the photoresist layer. In step S322, when adjusting the position of the mask of the next batch of devices, the adjusting distance is the same as the value of the overlay error of the current batch of devices, and the adjusting direction is opposite to the direction of the overlay error of the current batch of devices. In step S323, the next batch of devices is etched by using a dry etching process, further, the etching gas used in the dry etching process is a mixture of carbon tetrafluoride and chloroform, and the ratio of the carbon tetrafluoride to the chloroform is adjusted according to the material of the etching layer, so as to achieve the optimal etching effect.
In one embodiment, a connection line direction between the positioning groove and the center of the wafer is defined as a Y direction, a direction perpendicular to the Y direction is defined as an X direction, and the overlay error includes an X direction error and a Y direction error. The alignment error is divided into an X-direction error and a Y-direction error, so that the photomask can be more conveniently controlled to move in the process of carrying out compensation exposure.
The calculation method of the X-direction error and the Y-direction error will be described in detail herein with reference to the embodiment shown in fig. 6. The three capacitor holes 100 are respectively defined as a first capacitor hole, a second capacitor hole and a third capacitor hole in a clockwise direction; the direction of the first capacitor hole pointing to the second capacitor hole is defined as a first offset direction, the direction of the second capacitor hole pointing to the third capacitor hole is defined as a second offset direction, and the direction of the first capacitor hole pointing to the third capacitor hole is defined as a third offset direction. In the outline picture, the offset distance of the capacitor opening hole 200 along the first offset direction is defined as a first measurement offset value shift1, the offset distance along the second offset direction is defined as a second measurement offset value shift2, the offset distance along the third offset direction is defined as a third measurement offset value shift3, the included angle between the first offset direction and the X direction is defined as a first included angle θ, and the included angle between the second offset direction and the X direction is defined as a second included angle e along the negative direction of the Y direction.
In actual measurement, the same sample is rotated to three different angles, each angle uses a CD-SEM to obtain a clear and accurate profile picture through a set magnification, and offset values in different directions are measured, namely the shift1, the shift2 and the shift3 are obtained through three times of measurement, so that the measured offset value obtained from the profile picture and a real offset value are in a positive correlation relationship, and the correlation coefficient is k. In addition, during CD-SEM measurement, an electron beam with a set pressure is required to bombard a sample, after each electron beam bombardment, the sample may generate a different degree of electrification, and the electrification has a correlation with the electron beam voltage, the material of the film layer of the product, and the like, so that the offset value obtained by each measurement needs to be corrected correspondingly according to a set proportion, so as to obtain a more accurate real offset value result, and specifically, the real offset value and the measurement offset value satisfy the following relationship:
shift1’＝k*k1*shift1；
shift2’＝k*k2*shift2；
shift3’＝k*k3*shift3；
where shift1 ' represents a first true offset value along a first offset direction, shift2 ' represents a second true offset value along a second offset direction, shift3 ' represents a third true offset value along a third offset direction, and k1, k2, and k3 represent correction ratios for the first, second, and third measured offset values, respectively.
The X-direction error and the Y-direction error satisfy the following equations:
OVLX＝shift1’*cosθ+shift2’*cosε；
OVLY＝shift2’*sinε-shift1’*sinθ-shift3’；
wherein, OVLX represents the error in the X direction, and OVLY represents the error in the Y direction.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (9)
1. An overlay error compensation method for a capacitor opening layer comprises the following steps:
obtaining a profile picture of a test area of the devices in the current batch, wherein at least one capacitor opening hole and a plurality of capacitor holes which are designed to be communicated by the capacitor opening hole are formed in the test area;
defining a layer where the capacitor opening holes are located as a capacitor opening layer, defining layers where the plurality of capacitor holes are located as capacitor layers, and acquiring an alignment error between the capacitor opening layer of the test area and the capacitor layers according to the profile picture;
back-compensating and exposing the capacitor opening layer of the next batch of devices according to the overlay error of the current batch of devices;
wherein the capacitor opening hole and the plurality of capacitor holes designed to communicate with the capacitor opening hole are defined as a capacitor hole combination, and a deviation between an actual position and a design position of the capacitor opening hole in one capacitor hole combination is defined as a single set error,
the method comprises the following steps that the outline picture of the test area comprises at least two capacitor hole combinations, and the step of acquiring the overlay error between the capacitor opening layer and the capacitor layer of the test area comprises the following steps:
acquiring single group errors of at least two capacitor hole combinations in the test area;
and calculating the average value of at least two single group errors, and defining the average value as the overlay error of the test area.
2. The method according to claim 1, wherein in the step of obtaining the single set error of at least two capacitor hole combinations in the test area, the at least two capacitor hole combinations are respectively disposed at a center position or a corner position of the test area, and the positions of the capacitor hole combinations in the test area are symmetrically distributed.
3. The method for compensating for the overlay error of the capacitive opening layer according to claim 1, wherein the step of obtaining the overlay error between the capacitive opening layer of the test area and the capacitive layer further comprises the following steps:
presetting an error threshold;
and comparing the overlay error with the error threshold, and judging that the area with the overlay error larger than the error threshold is an unqualified area of the device.
4. The overlay error compensation method of claim 1, wherein the wafer is divided into a plurality of test regions, each test region is disposed adjacent to each other, and the step of back-compensating and exposing the capacitor open layer of the next batch of devices according to the overlay error of the current batch of devices comprises:
acquiring the overlay error of the devices in the current batch in each test area;
and according to the overlay error, exposing and compensating the capacitance opening layer of the devices of the next batch of the corresponding test area.
5. The method of claim 4, wherein the step of obtaining the overlay error of the current batch of devices for each test region is followed by the steps of:
and drawing an overlay error wafer graph of the devices in the current batch.
6. The method according to claim 4, wherein the step of exposing and compensating the capacitor open layers of the next batch of devices in the corresponding test regions according to the overlay error comprises:
coating photoresist on the surface of the substrate of the next batch of devices;
adjusting the position of a photomask in the exposure of the corresponding test area of the next batch of devices according to the alignment error of the current batch of devices in the test area;
the next batch of devices is exposed, developed and etched to form the capacitance opening layer.
7. The method as claimed in claim 6, wherein the adjustment distance of the mask position of the next lot of devices is the same as the alignment error of the current lot of devices, and the adjustment direction is opposite to the alignment error of the current lot of devices.
8. The overlay error compensation method of a capacitive opening layer according to claim 1, wherein one capacitive hole combination comprises one capacitive opening hole and three capacitive holes, and a central position of the capacitive opening hole is designed to be the same distance from a central position of each capacitive hole.
9. The method as claimed in any one of claims 1 to 8, wherein a line connecting the center of the positioning groove of the wafer and the center is defined as a Y direction, and a direction perpendicular to the Y direction is defined as an X direction, wherein the overlay error includes an X direction error and a Y direction error.
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| TW409406B (en) * | 1999-03-01 | 2000-10-21 | Vanguard Int Semiconduct Corp | Dynamic random access memory and its producing method |
| KR20010011000A (en) * | 1999-07-24 | 2001-02-15 | 김영환 | Forming method of capacitor pattern using double exposure |
| TW550722B (en) * | 2001-06-19 | 2003-09-01 | Infineon Technologies Ag | Method for controlling the quality of a lithographic structuring step |
| TW594852B (en) * | 2003-09-02 | 2004-06-21 | Nanya Technology Corp | Method of evaluating mask registration |
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