CN112702063A - Current steering DAC circuit - Google Patents

Current steering DAC circuit Download PDF

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Publication number
CN112702063A
CN112702063A CN201911012308.7A CN201911012308A CN112702063A CN 112702063 A CN112702063 A CN 112702063A CN 201911012308 A CN201911012308 A CN 201911012308A CN 112702063 A CN112702063 A CN 112702063A
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terminal
current
tube
pmos
nmos
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CN112702063B (en
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张识博
尤勇
刘军
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CRM ICBG Wuxi Co Ltd
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CRM ICBG Wuxi Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • Theoretical Computer Science (AREA)
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Abstract

The invention provides a current steering DAC circuit, which comprises a logic control circuit, a RESET circuit and a control circuit, wherein the logic control circuit is used for generating an N-bit binary code according to a voltage pulse signal and carrying out RESET operation under the control of a RESET signal; the binary code DAC conversion circuit is connected to the logic control circuit and used for generating reference current according to reference voltage and mirroring the reference current to the N current branches in proportion, and N switching tubes of the N current branches are controlled through the N-bit binary code to generate voltage output; meanwhile, a switching tube of the adjusting branch circuit is controlled through a switching signal to generate an adjusting voltage which is added to the output end of the binary code DAC converting circuit; and the comparison circuit is connected with the binary code DAC conversion circuit and the logic control circuit and is used for generating a RESET signal and a switch signal according to the comparison result of the output voltage and the preset voltage. The invention solves the problems that the brightness of the LED lamp is limited and the full load cannot be achieved due to the narrow output voltage regulation range of the current steering DAC circuit.

Description

Current steering DAC circuit
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a current steering DAC circuit.
Background
In an LED driving chip circuit, a DAC conversion circuit is sometimes used to realize some conversion from digital quantity to analog quantity. There are three current steering DAC structures commonly used in the industry at present, namely a binary code structure, a temperature code structure and a segmented structure; the binary code structure has the advantages of simple structure and small area, and has the defects of instantaneous burr output during switching action and the like; the temperature code structure has the advantages of good monotonicity and low matching precision requirement, and has the defect of huge chip area consumption; the segmented structure is the combination of a binary code structure and a temperature code structure, and the binary code is used for the low bit and the temperature code is used for the high bit, so the segmented structure has the advantages and the disadvantages of the binary code structure and the temperature code structure. Because the LED driving chip is not a special DAC chip, the performance requirement is not very high, and a current steering DAC with a binary code structure is directly selected to save area.
A typical current steering DAC circuit structure of a binary code structure is shown in fig. 1, and includes a logic control circuit and a binary code DAC conversion circuit connected thereto, where fig. 2 is the logic control circuit, and fig. 3 is the binary code DAC conversion circuit. As shown in FIG. 2, the conventional logic control circuit is used to generate a binary code when V isPULSEAfter pulse signals are sent to the series-connected D flip-flop groups, the output Qn … Q3Q2Q1 sequentially turns over from the binary code 0 … 000 at the lowest bit to the binary code 1 … 111 at the highest bit, wherein each bit output logic correspondingly controls one switching tube in the binary code DAC conversion circuit. As shown in fig. 3, the conventional DAC circuit generates a reference current, then mirrors the reference current into a current mirror group in binary relation, and finally outputs an analog voltage V in combination with the binary codeOUT。
As shown in fig. 2 and 3, assuming that the reference current is I, the switching tube NMK1The controlled branch current is I, and the switch tube NMK2The controlled branch current is 2I, and the switch tube NMK3The controlled branch current is 4I, and the switch tube NMKnThe controlled current is 2n-1I. When the binary code 0 … 000 with the lowest bit is provided to each switch tube NM of the DAC circuitK1To NMKnWhen the voltage is over, all branch circuit switch tubes are turned off, and the output voltage V is at the momentOUT＝0*R 20; when the binary code 1 … 111 with the most significant bit is provided to each switch tube NM of the DAC circuitK1To NMKnWhen the current mirror is started, all branch switching tubes are conducted, and the current is mirrored to the outputOutput voltage VOUT＝(I+2I+4I+…+2n-1I)*R2＝(2n-1)I*R2(ii) a When the binary code is converted from 0 … 000 to 1 … 111, the output voltage VOUTFrom 0 to (2)n-1)I*R2Gradually increased by unit step length of I R2(ii) a That is, the output voltage range of the existing circuit scheme is 0 to (2)n-1)I*R2The simulation resolution is I R2. It can be seen that the output voltage range of the existing circuit scheme is narrow, and the specific output voltage waveform is shown in fig. 4.
Because the output voltage regulation range of the existing circuit scheme is too narrow, the brightness of the LED lamp is usually limited, and the full load cannot be achieved; on the premise that the analog resolution meets the condition, if the output voltage regulation range is wider, the more DAC bits are needed, the more corresponding current branches and control logics are needed, and the problem of larger chip area is finally caused; if the output voltage adjusting range is enlarged by increasing the analog resolution, namely increasing the unit step length, the area of the chip is kept basically unchanged, and the problems of large unit step length of the output voltage, LED lamp flashing, electromagnetic interference and the like are caused.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a current steering DAC circuit, which is used to solve the problems that the brightness of an LED lamp is limited and the LED lamp cannot reach full load due to the too narrow output voltage adjustment range of the current steering DAC circuit.
To achieve the above and other related objects, the present invention provides a current steering DAC circuit, including:
the logic control circuit is used for generating an N-bit binary code according to the voltage pulse signal and carrying out RESET operation under the control of a RESET signal;
the binary code DAC conversion circuit is connected to the logic control circuit and used for generating a reference current according to a reference voltage, mirroring the reference current to the N current branches in proportion, and respectively controlling N switching tubes of the N current branches to generate voltage output through the N-bit binary code; meanwhile, a switching tube of the adjusting branch circuit is controlled through a switching signal to generate an adjusting voltage to be added to the output end of the binary code DAC converting circuit, and the adjusting voltage is used for widening the adjusting range of the output voltage of the binary code DAC converting circuit;
and the comparison circuit is connected with the binary code DAC conversion circuit and the logic control circuit and is used for generating the RESET signal and the switch signal according to the comparison result of the output voltage and the preset voltage.
Optionally, the logic control circuit comprises: and the input ends of the N series D triggers are connected with the voltage pulse signal, the output ends of the N D triggers are used for generating the N-bit binary code, and the RESET ends of the N D triggers are connected with the RESET signal output by the comparison circuit.
Optionally, the binary code DAC conversion circuit includes:
an operational amplifier for generating the reference current according to the reference voltage;
the current branch control module is connected with the operational amplifier, comprises N current branches and is used for mirroring the reference current to the N current branches in proportion and respectively controlling N switching tubes of the N current branches through the N-bit binary code so as to generate a branch total current according to the conducted current branches;
the adjusting module is connected with the operational amplifier and comprises at least one adjusting branch circuit, and the adjusting branch circuit is used for controlling a switching tube of the adjusting branch circuit according to the switching signal so as to generate an adjusting current;
and the voltage output module is connected with the current branch control module and the regulating module and used for generating a voltage output according to the total current of the branch and generating a regulating voltage according to the regulating current so as to add the regulating voltage to the output end of the voltage output module.
Optionally, the operational amplifier comprises: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a first resistor, wherein the source terminal of the first PMOS tube is connected with a power voltage, the drain terminal of the first PMOS tube is connected with the gate terminal of the first PMOS tube, the gate terminal of the second PMOS tube and the drain terminal of the first NMOS tube, the source terminal of the second PMOS tube is connected with the power voltage, the drain terminal of the second PMOS tube is connected with the drain terminal of the second NMOS tube and the gate terminal of the fourth NMOS tube, the gate terminal of the first NMOS tube is connected with a reference voltage, the source terminal of the first NMOS tube is connected with the source terminal of the second NMOS tube and the drain terminal of the third NMOS tube, the gate terminal of the second NMOS tube is connected with the source terminal of the fourth NMOS tube and one end of the first resistor, the gate terminal of the third NMOS tube is connected with a first bias voltage, the source end of the third NMOS tube is grounded, the source end of the third PMOS tube is connected with power supply voltage, the drain end of the third PMOS tube is connected to the gate end of the third PMOS tube and the drain end of the fourth NMOS tube and serves as the output end of the operational amplifier, and the other end of the first resistor is grounded.
Optionally, the current branch control module includes: a fourth PMOS tube, a fifth NMOS tube, N NMOS current tubes and N NMOS switch tubes, wherein the source terminal of the fourth PMOS tube is connected with a power supply voltage, the gate terminal of the fourth PMOS tube is connected with the output terminal of the operational amplifier, the drain terminal of the fourth PMOS tube is connected with the drain terminal of the fifth NMOS tube, the source terminal of the fifth NMOS tube is grounded, the gate terminal of the fifth NMOS tube is connected with the drain terminal of the fifth NMOS tube and the gate terminals of the N NMOS current tubes to form a second bias voltage, the source terminals of the N NMOS current tubes are grounded, the drain terminals of the N NMOS current sources are correspondingly connected with the source terminals of the N NMOS switch tubes, the gate terminals of the N NMOS switch tubes are correspondingly connected with the N-bit binary code, the drain terminals of the N NMOS switch tubes are connected with the drain terminal of the fifth PMOS tube, and the source terminal of the fifth PMOS tube is connected with the power supply voltage, the grid end of the fifth PMOS tube is connected to the drain end of the fifth PMOS tube and is used as the output end of the current branch control module; wherein N NMOS current tubes and N NMOS switch tubes correspondingly form N current branches, and the NMOS current tube of each current branch comprises 2n-1And N is the sequence of the current branch circuit where the corresponding NMOS tube is located in the N current branch circuits.
Optionally, the adjusting branch comprises: a PMOS current tube and a PMOS switch tube, wherein the source terminal of the PMOS current tube is connected with the power supply voltage, the grid terminal of the PMOS current tube is connected with the output terminal of the operational amplifier, the drain terminal of the PMOS current tube is connected with the drain terminal of the PMOS switch tube, the grid terminal of the PMOS switch tube is connected with the switch signal output by the comparison circuit, and the source terminal of the PMOS switch tube is used as the output terminal of the regulation branch; the PMOS current tube comprises a PMOS tubes connected in parallel, and a is less than or equal to 2n-1。
Optionally, the voltage output module includes: the source end of the sixth PMOS tube is connected with a power supply voltage, the grid end of the sixth PMOS tube is connected with the output end of the current branch control module, the drain end of the sixth PMOS tube is connected with the output end of the adjusting module, one end of the second resistor and one end of the first capacitor and serves as the output end of the voltage output module, the other end of the second resistor is grounded, and the other end of the first capacitor is grounded.
Optionally, the comparison circuit comprises: at least one comparison module and a NOR gate, the comparison module includes: the output end of the rising edge detection unit and the output end of the falling edge detection unit are connected to the input end of the NOR gate, and the output end of the NOR gate generates the RESET signal.
Optionally, the rising edge detection unit includes: a seventh PMOS transistor, a sixth NMOS transistor, a third resistor, a second capacitor, a first schmitt trigger, a first nand gate, and a first inverter, wherein a source terminal of the seventh PMOS transistor is connected to a power voltage, a drain terminal of the seventh PMOS transistor is connected to one terminal of the third resistor, one terminal of the second capacitor, and an input terminal of the first schmitt trigger, a gate terminal of the seventh PMOS transistor is connected to a gate terminal of the sixth NMOS transistor and an output terminal of the comparator, another terminal of the third resistor is connected to a drain terminal of the sixth NMOS transistor, a source terminal of the sixth NMOS transistor is grounded, another terminal of the second capacitor is grounded, an output terminal of the first schmitt trigger is connected to a first input terminal of the first nand gate, a second input terminal of the first nand gate is connected to an output terminal of the comparator, an output terminal of the first nand gate is connected to an input terminal of the first inverter, and the output end of the first inverter is used as the output end of the rising edge detection unit.
Optionally, the falling edge detection unit includes: an eighth PMOS transistor, a seventh NMOS transistor, a fourth resistor, a third capacitor, a second schmitt trigger, a second nand gate, a second inverter and a third inverter, wherein an input terminal of the second inverter is connected to an output terminal of the comparator, an output terminal of the second inverter is connected to a gate terminal of the eighth PMOS transistor, a gate terminal of the seventh NMOS transistor and a first input terminal of the second nand gate, a power voltage is applied to the eighth PMOS transistor, a drain terminal of the eighth PMOS transistor is connected to one end of the fourth resistor, one end of the third capacitor and an input terminal of the second schmitt trigger, another end of the fourth resistor is connected to a drain terminal of the seventh NMOS transistor, a source terminal of the seventh NMOS transistor is grounded, another end of the third capacitor is grounded, an output terminal of the second schmitt trigger is connected to a second input terminal of the second nand gate, the output end of the second nand gate is connected to the input end of the third inverter, and the output end of the third inverter is used as the output end of the falling edge detection unit.
As described above, according to the current steering DAC circuit of the present invention, the real-time value of the output voltage of the binary DAC conversion circuit is detected by the comparison circuit, and the RESET signal and the switching signal are generated; meanwhile, a switching tube of the adjusting branch circuit is controlled through a switching signal to generate an adjusting voltage to be added to the output end of the binary code DAC converting circuit, the adjusting voltage is utilized to widen the adjusting range of the output voltage of the binary code DAC converting circuit, and the problems that the brightness of an LED lamp is limited and the full load cannot be achieved under the condition that the area of a chip is basically unchanged are solved.
Drawings
Fig. 1 shows a block diagram of a prior art current steering DAC circuit.
Fig. 2 is a circuit diagram of a logic control circuit in a conventional current steering DAC circuit.
Fig. 3 is a circuit diagram of a binary code DAC conversion circuit in a conventional current steering DAC circuit.
Fig. 4 is a graph showing the output voltage waveform of a conventional current steering DAC circuit.
Fig. 5 is a block diagram of the current steering DAC circuit of the present invention.
Fig. 6 is a circuit diagram of a logic control circuit in the current steering DAC circuit according to the present invention.
Fig. 7 is a circuit diagram of a binary code DAC conversion circuit in the current steering DAC circuit according to the present invention.
Fig. 8 is a circuit diagram of a comparison circuit in the current steering DAC circuit of the present invention.
FIG. 9 is a circuit diagram of a rising edge detecting unit in the comparator circuit of the present invention.
FIG. 10 is a circuit diagram of a falling edge detection unit in the comparison circuit of the present invention.
Fig. 11 shows an embodiment of a binary DAC conversion circuit and a corresponding comparison circuit according to the present invention.
Fig. 12 is a graph of the output voltage waveform of the current steering DAC circuit of fig. 11.
Description of the element reference numerals
100 logic control circuit
200 binary code DAC converting circuit
201 operational amplifier
202 current branch control module
203 regulating module
204 voltage output module
300 comparison circuit
301 comparing module
3011 rising edge detection unit
3012 falling edge detection unit
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 5 to 12. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 5, the present embodiment provides a current steering DAC circuit including:
a logic control circuit 100 for controlling the output of the voltage pulse signal VPULSEGenerating an N-bit binary code Qn … Q3Q2Q1, and performing RESET operation under the control of a RESET signal;
a binary code DAC conversion circuit 200 connected to the logic control circuit 100 for converting the reference voltage VREFGenerating a reference current, mirroring the reference current to N current branches in proportion, and respectively controlling N switching tubes of the N current branches through the N-bit binary code to generate voltage output; by simultaneous switchingThe signal controls a switching tube of the adjusting branch circuit to generate an adjusting voltage to be added to the output end of the binary code DAC converting circuit, and the adjusting voltage is used for widening the adjusting range of the output voltage of the binary code DAC converting circuit;
a comparison circuit 300 connected to the binary DAC circuit 200 and the logic control circuit 100 for outputting the output voltage VOUTAnd a comparison result of the preset voltage, generating the RESET signal and the switching signal.
As an example, as shown in fig. 6, the logic control circuit 100 includes: n series-connected D flip-flops DFF 1-DFFn, wherein the input terminals of the N series-connected D flip-flops are connected with the voltage pulse signal VPULSEThe output terminals of the N D flip-flops are used for generating the N-bit binary code Qn … Q3Q2Q1, and the RESET terminals of the N D flip-flops are connected to the RESET signal output by the comparison circuit 300.
As shown in fig. 6, at the voltage pulse signal VPULSEWhen the voltage pulse signal V is inputted to the input terminal of the logic control circuit 100, the output terminals of the N D flip-flops generate an N-bit binary code Qn … Q3Q2Q1PULSEThe output ends of the N D flip-flops are sequentially turned over, so that the output N-bit binary code Qn … Q3Q2Q1 is gradually increased from 0 … 000 to 1 … 111; when the RESET signal arrives, the RESET signal is utilized to control the N D triggers to carry out RESET operation, so that the outputs of the N D triggers are RESET to 0 … 000.
As an example, as shown in fig. 7, the binary code DAC conversion circuit 200 includes:
an operational amplifier 201 for outputting a reference voltage VREFGenerating the reference current;
the current branch control module 202 is connected to the operational amplifier 201, and includes N current branches, and is configured to mirror the reference current to the N current branches in proportion, and respectively control N switching tubes of the N current branches through the N-bit binary code, so as to generate a branch total current according to the turned-on current branches;
the adjusting module 203 is connected to the operational amplifier 201, and includes at least one adjusting branch for controlling a switching tube of the adjusting branch according to the switching signal to generate an adjusting current;
and the voltage output module 204 is connected to the current branch control module 202 and the adjusting module 203, and is configured to generate a voltage output according to the total current of the branch, and generate an adjusting voltage according to the adjusting current, so as to add the adjusting voltage to the output end of the voltage output module 204.
Specifically, as shown in fig. 7, the operational amplifier 201 includes: first PMOS pipe PM1And a second PMOS tube PM2And a third PMOS tube PM3A first NMOS transistor NM1And a second NMOS tube NM2And a third NMOS transistor NM3And a fourth NMOS tube NM4And a first resistor R1The first PMOS tube PM1Source terminal of the switching circuit is connected to a power supply voltage VCCThe first PMOS tube PM1Drain end of the first PMOS tube PM is connected with1Gate terminal of the second PMOS tube PM2Gate terminal and the first NMOS transistor NM1The drain end of the second PMOS tube PM2Source terminal of the switching circuit is connected to a power supply voltage VCCThe second PMOS tube PM2Drain terminal thereof is connected to the second NMOS tube NM2Drain terminal of and the fourth NMOS tube NM4Said first NMOS transistor NM1Is connected with a reference voltage VREFThe first NMOS tube NM1Source terminal of is connected to the second NMOS transistor NM2Source terminal and the third NMOS transistor NM3The drain end of the second NMOS tube NM2Is connected to the fourth NMOS transistor NM4Source terminal and the first resistor R1One end of the third NMOS tube NM3Is connected to a first bias voltage VBIAS1The third NMOS tube NM3Source terminal of the third PMOS transistor PM is grounded, and the third PMOS transistor PM is connected to the source terminal of the third PMOS transistor3Source terminal of the switching circuit is connected to a power supply voltage VCCThe third PMOS tube PM3Drain end of the second PMOS tube PM is connected to the third PMOS tube PM3Gate terminal and the fourth NMOS transistor NM4And as the operational amplifierThe output terminal of the amplifier 201, the first resistor R1And the other end of the same is grounded.
As shown in fig. 7, the first NMOS transistor NM1And the second NMOS tube NM2Forming a differential input pair transistor, the third NMOS transistor NM3Providing a tail current of an operational amplifier, wherein the first PMOS tube PM1And the second PMOS tube PM2The fourth NMOS tube NM is used for forming a current mirror load of the operational amplifier4Realize the second-stage gain amplification, and the third PMOS tube PM3Realizing current output; by the operational amplifier of the present example, the first resistor R is made to be1Is equal to the reference voltage VREFSo as to enable the PM to flow through the third PMOS pipe3Current magnitude of VREF/R1I.e. the reference current I ═ VREF/R1。
Specifically, as shown in fig. 7, the current branch control module 202 includes: fourth PMOS pipe PM4And the fifth PMOS tube PM5And a fifth NMOS transistor NM5N NMOS current tubes NMS1To MNSnAnd N NMOS switching tubes NMK1To NMKnThe fourth PMOS tube PM4Source terminal of the switching circuit is connected to a power supply voltage VCCThe fourth PMOS tube PM4The gate terminal of the second PMOS transistor PM is connected to the output terminal of the operational amplifier 201, and the second PMOS transistor PM4Drain terminal thereof is connected to the fifth NMOS tube NM5The drain end of the fifth NMOS transistor NM5The source terminal of the fifth NMOS transistor NM is grounded5Is connected to the fifth NMOS transistor NM5Drain terminal and N NMOS current tubes NMS1To MNSnWhile forming a second bias voltage VBIAS2N NMOS current tubes NMS1To MNSnWith source terminals all grounded, N NMOS current sources NMS1To MNSnDrain terminal of the NMOS switch tube NM is correspondingly connected with N NMOS switch tubes NMK1To NMKnSource terminal of (NM), N NMOS switch tubes (NM)K1To NMKnThe grid end of the NMOS switch tube is correspondingly connected into the N-bit binary code Qn … Q3Q2Q1 and N NMOS switch tubes NMK1To NMKnIs connected to the drain terminal ofIn the fifth PMOS tube PM5The drain end of the fifth PMOS tube PM5Source terminal of the switching circuit is connected to a power supply voltage VCCThe fifth PMOS tube PM5Is connected with the grid end of the fifth PMOS tube PM5And at the same time as the output terminal of the current branch control module 202; wherein N NMOS current tubes NMS1To MNSnAnd N NMOS switching tubes NMK1To NMKnCorrespondingly forming N current branches, wherein the NMOS current tube of each current branch comprises 2n-1And N is the sequence of the current branch circuit where the corresponding NMOS tube is located in the N current branch circuits.
As shown in fig. 7, the fourth PMOS transistor PM4And the third PMOS transistor PM in the operational amplifier 2013Form a current mirror to make the PM flow through the fourth PMOS transistor4Is equal to the current flowing through the third PMOS tube PM3Is the magnitude of the current of VREF/R1(ii) a Since the present example is a binary DAC architecture, i.e. the currents on the N current branches and the reference current I need to be 2n-1So that the number of NMOS current tubes in each current branch of this example is 2n-1N is the sequence of the current branch circuit where the corresponding NMOS tube is located in the N current branch circuits, such as NMOS current tube NM in the 1 st current branch circuitS1Is 2 in number1-11, NMOS current tube NM connected in parallel in the 2 nd current branchS2Is 2 in number2-1NMOS current tube NM connected in parallel in the 3 rd current branchS3Is 2 in number3-1And analogizing in turn about 4, the parallel NMOS current tube NM in the nth current branchSnIs 2 in numbern-1The current flowing through the 1 st current branch after being conducted is I, the current flowing through the 2 nd current branch is 2I, the current flowing through the 3 rd current branch is 4I, and the current flowing through the nth current branch is 2n-1I. Then, the N binary codes Qn … Q3Q2Q1 are utilized to control N switching tubes NMK1To NMKnSo as to be in the fifth PMOS transistor PM (on or off)5A branch total current is generated.
Specifically, as shown in fig. 7, the adjusting branch includes: a PMOS current tube and a PMOS switch tube, the source terminal of the PMOS current tube is connected to the power voltage VCCThe gate terminal of the PMOS current tube is connected to the output terminal of the operational amplifier 201, the drain terminal of the PMOS current tube is connected to the drain terminal of the PMOS switch tube, the gate terminal of the PMOS switch tube is connected to the switching signal output by the comparison circuit 300, and the source terminal of the PMOS switch tube is used as the output terminal of the regulation branch; the PMOS current tube comprises a PMOS tubes connected in parallel, and a is less than or equal to 2n-1. It should be noted that when the adjusting module 203 includes a plurality of adjusting branches, the plurality of adjusting branches are connected in parallel, and the number of PMOS current tubes in each adjusting branch may be the same or different, but all of them need to be less than or equal to 2n-1。
As shown in FIG. 7, it is assumed that the switching signal controls the PMOS switch tube PMK1When the adjusting branch is turned on, the reference current output by the operational amplifier 201 is mirrored to the PMOS current tube PM in the adjusting branch in proportionS1So as to flow through the PMOS current tube PMS1Is aI, thereby introducing a regulated voltage aIR at the output of the binary DAC conversion circuit 2002. Of course, when the adjusting module 203 includes a plurality of adjusting branches, the plurality of switching signals output by the comparing circuit 300 respectively control the PMOS switches in the plurality of adjusting branches to mirror the reference current to the conducting adjusting branches in proportion, so as to introduce a plurality of adjusting voltages at the output end of the binary code DAC converting circuit 200.
Specifically, as shown in fig. 7, the voltage output module 204 includes: sixth PMOS pipe PM6A second resistor R2And a first capacitor C1The sixth PMOS tube PM6Source terminal of the switching circuit is connected to a power supply voltage VCCThe sixth PMOS tube PM6The gate terminal of the sixth PMOS transistor PM is connected to the output terminal of the current branch control module 2026Is connected to the output terminal of the regulating module 203 and the second resistor R2And said firstCapacitor C1And as an output terminal of the voltage output module 204, the second resistor R2Is grounded, the first capacitor C1And the other end of the same is grounded.
As shown in fig. 7, the sixth PMOS transistor PM6And a fifth PMOS transistor PM in the current branch control module 2025A current mirror is formed to make PM flow through the sixth PMOS tube6Is equal to the magnitude of the current flowing through the fifth PMOS tube PM5So that the current flowing through the sixth PMOS tube PM6At the second resistor R2And a first capacitor C1Generating a voltage output; meanwhile, due to the design of the adjusting module 203, in the sixth PMOS transistor PM6Is introduced into the regulating current, thereby forming a second resistance R2And a first capacitor C1On the output voltage of the output transistor, a regulated voltage is generated to realize the broadening of the output voltage V by the regulated voltageOUTVoltage regulation range of (1) to output a voltage VOUTIs equal to the sum of the corresponding voltage of the total current of the branch and the regulated voltage.
As an example, as shown in fig. 8, the comparison circuit 300 includes: at least one comparing module 301 and a nor gate OR, the comparing module 301 comprising: a comparator, a rising edge detection unit 3011 and a falling edge detection unit 3012, where a positive phase input terminal of the comparator is connected to a preset voltage, an inverted phase input terminal of the comparator is connected to an output terminal of the binary code DAC conversion circuit 200, an output terminal of the comparator is connected to an input terminal of the rising edge detection unit 3011 and an input terminal of the falling edge detection unit 3012, and generates the switch signal, an output terminal of the rising edge detection unit 3011 and an output terminal of the falling edge detection unit 3012 are connected to an input terminal of the nor gate OR, and an output terminal of the nor gate OR generates the RESET signal. It should be noted that the number of the comparing modules 301 is the same as the number of the adjusting branches, and the comparing modules correspond to the adjusting branches one to one; while broadening the output voltage VOUTIn order to make the output voltage V during the regulation rangeOUTNo jump occurs, and the pre-stage of each comparison module can be reasonably setAnd setting a voltage value to realize.
Specifically, as shown in fig. 9, the rising edge detection unit 3011 includes: seventh PMOS tube PM7And a sixth NMOS transistor NM6A third resistor R3A second capacitor C2A first Schmitt trigger Smit1, a first NAND gate AND1 AND a first inverter INV1, wherein the seventh PMOS transistor PM7Source terminal of the switching circuit is connected to a power supply voltage VCCThe seventh PMOS tube PM7Is connected to the third resistor R3One terminal of, the second capacitor C2And an input terminal of the first schmitt trigger Smit1, the seventh PMOS transistor PM7Is connected to the sixth NMOS tube NM6The gate terminal of (3), the output terminal of the comparator, and the third resistor R3Is connected to the sixth NMOS tube NM6The drain end of said sixth NMOS tube NM6The source terminal of which is grounded, the second capacitor C2The output end of the first schmitt trigger Smit1 is connected to the first input end of the first nand gate AND1, the second input end of the first nand gate AND1 is connected to the output end of the comparator, the output end of the first nand gate AND1 is connected to the input end of the first inverter INV1, AND the output end of the first inverter INV1 is used as the output end of the rising edge detection unit.
As shown in fig. 9, when the output of the comparator is at a low level, the seventh PMOS transistor PM7The output of the drain terminal of the nand gate is high, the output of the same-direction first schmitt trigger Smit1 is also high, AND the second input terminal of the first nand gate AND1 is low, so the output of the first nand gate AND1 is high, AND after being inverted by the first inverter INV1, the output of the rising edge detection unit 3011 is low. When the output of the comparator changes from low level to high level, i.e. when the rising edge signal arrives, the second input of the first nand gate AND1 immediately changes to high level, but the first input thereof changes to high level due to R3、C2And the hysteresis flip of the first schmitt trigger Smit1 only at C2When the voltage on the first Schmitt trigger is lowThe output of Smit1 will toggle to a low level; during a short time delay before the first schmitt trigger Smit1 is inverted to the low level, both input ends of the first nand gate AND1 are at the high level, so that the output is at the low level, AND is inverted by the first inverter INV1 to output the high level; after the first schmitt trigger Smit1 is inverted to the low level, the output of the first nand gate AND1 is at the high level, AND at this time, the high-level narrow pulse output by the rising edge detection unit 3011 is ended AND is inverted to the low level again. When the output of the comparator changes from high level to low level, the second input terminal of the first nand gate AND1 immediately changes to low level, AND the output thereof is high level, at this time, the output of the rising edge detection unit 3011 immediately toggles to low level, AND there is no high level pulse signal.
Specifically, as shown in fig. 10, the falling edge detection unit includes: eighth PMOS pipe PM8And a seventh NMOS transistor NM7A fourth resistor R4A third capacitor C3A second schmitt trigger Smit2, a second nand gate AND2, a second inverter INV2 AND a third inverter INV3, wherein an input end of the second inverter INV2 is connected to an output end of the comparator, an output end of the second inverter INV2 is connected to the eighth PMOS transistor PM8Gate terminal of, the seventh NMOS transistor NM7AND the gate terminal of the eighth PMOS transistor PM, the first input terminal of the second nand gate AND28Source terminal of the switching circuit is connected to a power supply voltage VCCThe eighth PMOS tube PM8Is connected to the fourth resistor R4One terminal of, the third capacitance C3And the input terminal of the second schmitt trigger Smit2, the fourth resistor R4Is connected to the seventh NMOS tube NM7The drain end of said seventh NMOS transistor NM7The source terminal of which is grounded, the third capacitor C3The output end of the second schmitt trigger Smit2 is connected to the second input end of the second nand gate AND2, the output end of the second nand gate AND2 is connected to the input end of the third inverter INV3, AND the output end of the third inverter INV3 is used as the output end of the falling edge detection unit.
As shown in fig. 10, when the comparator outputs a high level, the second inverter INV2 outputs a low level, and the eighth PMOS transistor PM8The drain terminal of the nand gate outputs a high level, the output of the same-direction second schmitt trigger Smit2 is also a high level, the output of the second nand gate AND2 is a high level because the first input terminal thereof is a low level, AND the falling edge detection unit 3012 outputs a low level after being inverted by the third inverter INV 3. When the output of the comparator changes from high level to low level, i.e. when the falling edge signal arrives, the first input terminal of the second nand gate AND2 immediately changes to high level, but the second input terminal thereof changes to high level due to R4、C3And the hysteresis flip of the second schmitt trigger Smit2 only at C3When the voltage on the second schmitt trigger Smit2 is low, the output of the second schmitt trigger Smit2 will be inverted to a low level; during a short time delay before the second schmitt trigger Smit2 is inverted to the low level, both input ends of the second nand gate AND2 are at the high level, so that the output is at the low level, AND is inverted by the third inverter INV3 to output the high level; after the second schmitt trigger Smit2 is inverted to the low level, the output of the second nand gate AND2 is at the high level, AND at this time, the high-level narrow pulse output by the falling edge detection unit 3012 is ended AND is inverted to the low level again. When the output of the comparator changes from low level to high level, the first input terminal of the second nand gate AND2 immediately changes to low level, AND the output thereof is high level, at this time, the output of the falling edge detection unit 3012 immediately toggles to low level, AND there is no high level pulse signal.
The working principle of the current steering DAC circuit according to the present embodiment is described in detail with reference to fig. 6, fig. 11, and fig. 12, wherein the present embodiment takes 2 adjusting branches as an example, and the comparing circuit includes 2 comparing modules.
As shown in FIG. 11, the PMOS current tube PM is setS1And PMOS switching tube PMK1The PMOS current tube PM in the first regulating branchS1The parallel connection number of the PMOS current tubes PM is aS2And PMOS switching tube PMK2The PMOS current tube PM in the second regulating branchS2B is the number of parallel connection, anda and b may be the same or different; while a first preset voltage VS1＝(2n-1)IR2A second predetermined voltage VS2＝(2n-1)IR2+aIR2。
The output voltage V of the binary DAC circuit is gradually increased from 0 … 000 to 1 … 111 along with the N-bit binary code Qn … Q3Q2Q1 output by the logic control circuit 100OUTGradually increases from 0 to (2)n-1)IR2；
At the output voltage V of the binary code DAC conversion circuitOUT＝(2n-1)IR2Time, output voltage VOUTAnd a first predetermined voltage VS1A second predetermined voltage VS2After comparison, the first comparator CMP1 outputs a low level, the second comparator CMP2 outputs a high level, that is, the switch signal SW1 is at a low level and the switch signal SW2 is at a high level, at this time, the PMOS switch tube PM in the first adjusting branch is at the same timeK1PMOS switching tube PM in conducting and second adjusting branchK2Turning off; meanwhile, since the output of the first comparator CMP1 is inverted from high to low, the falling edge detection unit connected to the output terminal of the first comparator CMP1 outputs a high short pulse, at this time, the comparison circuit generates a RESET signal, and the output of the logic control circuit is RESET to 0 … 000, i.e., N NMOS switching tubes NM in the binary code DAC conversion circuitK1To NMKnAll are turned off, at which time the output voltage VOUTBecomes aIR2。
The output voltage V of the binary DAC circuit is gradually increased from 0 … 000 to 1 … 111 along with the N-bit binary code Qn … Q3Q2Q1 output by the logic control circuit 100OUTFrom aIR2Gradually increase to (2)n-1)IR2+aIR2；
At the output voltage V of the binary code DAC conversion circuitOUT＝(2n-1)IR2+aIR2Time, output voltage VOUTAnd a first predetermined voltage VS1A second predetermined voltage VS2After the comparison, the first comparator CMP1 and the second comparator CMP2 each output a low level,that is, the switching signals SW1 and SW2 are both low, and the PMOS switch tube PM in the first adjusting branch is at this timeK1And a PMOS switching tube PM in the second regulating branchK2Are all conducted; meanwhile, since the output of the second comparator CMP2 is inverted from high to low, the falling edge detection unit connected to the output terminal of the second comparator CMP2 outputs a high short pulse, at this time, the comparison circuit generates a RESET signal, and the output of the logic control circuit is RESET to 0 … 000, i.e., N NMOS switching tubes NM in the binary code DAC conversion circuitK1To NMKnAll are turned off, at which time the output voltage VOUTBecomes aIR2+bIR2。
The output voltage V of the binary DAC circuit is gradually increased from 0 … 000 to 1 … 111 along with the N-bit binary code Qn … Q3Q2Q1 output by the logic control circuit 100OUTFrom aIR2+bIR2Gradually increase to (2)n-1)IR2+aIR2+bIR2。
It can be seen that the current steering DAC circuit of the present example: when the SW1 and the SW2 are both high level, namely the first regulating branch and the second regulating branch are both off, the output voltage V isOUTIn the range of 0 to (2)n-1)IR2(ii) a When the SW1 is low and the SW2 is high, that is, the first adjusting branch is turned on and the second adjusting branch is turned off, the output voltage V isOUTIn the range of aIR2To (2)n-1)IR2+aIR2(ii) a When the SW1 and the SW2 are both low level, that is, the first regulating branch and the second regulating branch are both conductive, the output voltage V isOUTIn the range of aIR2+bIR2To (2)n-1)IR2+aIR2+bIR2(ii) a That is, the output voltage V of the current steering DAC circuit described in this exampleOUTIn the range of 0 to (2)n-1)IR2+aIR2+bIR2The simulation resolution is I R2The output voltage waveform is schematically shown in fig. 12.
In summary, in the current steering DAC circuit of the present invention, the comparison circuit detects the real-time value of the output voltage of the binary code DAC conversion circuit, and generates the RESET signal and the switch signal; meanwhile, a switching tube of the adjusting branch circuit is controlled through a switching signal to generate an adjusting voltage to be added to the output end of the binary code DAC converting circuit, the adjusting voltage is utilized to widen the adjusting range of the output voltage of the binary code DAC converting circuit, and the problems that the brightness of an LED lamp is limited and the full load cannot be achieved under the condition that the area of a chip is basically unchanged are solved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A current steering DAC circuit, wherein the current steering DAC circuit comprises:
the logic control circuit is used for generating an N-bit binary code according to the voltage pulse signal and carrying out RESET operation under the control of a RESET signal;
the binary code DAC conversion circuit is connected to the logic control circuit and used for generating a reference current according to a reference voltage, mirroring the reference current to the N current branches in proportion, and respectively controlling N switching tubes of the N current branches to generate voltage output through the N-bit binary code; meanwhile, a switching tube of the adjusting branch circuit is controlled through a switching signal to generate an adjusting voltage to be added to the output end of the binary code DAC converting circuit, and the adjusting voltage is used for widening the adjusting range of the output voltage of the binary code DAC converting circuit;
and the comparison circuit is connected with the binary code DAC conversion circuit and the logic control circuit and is used for generating the RESET signal and the switch signal according to the comparison result of the output voltage and the preset voltage.
2. The current steering DAC circuit of claim 1, wherein the logic control circuit comprises: and the input ends of the N series D triggers are connected with the voltage pulse signal, the output ends of the N D triggers are used for generating the N-bit binary code, and the RESET ends of the N D triggers are connected with the RESET signal output by the comparison circuit.
3. The current steering DAC circuit of claim 1 wherein the binary code DAC conversion circuit comprises:
an operational amplifier for generating the reference current according to the reference voltage;
the current branch control module is connected with the operational amplifier, comprises N current branches and is used for mirroring the reference current to the N current branches in proportion and respectively controlling N switching tubes of the N current branches through the N-bit binary code so as to generate a branch total current according to the conducted current branches;
the adjusting module is connected with the operational amplifier and comprises at least one adjusting branch circuit, and the adjusting branch circuit is used for controlling a switching tube of the adjusting branch circuit according to the switching signal so as to generate an adjusting current;
and the voltage output module is connected with the current branch control module and the regulating module and used for generating a voltage output according to the total current of the branch and generating a regulating voltage according to the regulating current so as to add the regulating voltage to the output end of the voltage output module.
4. The current steering DAC circuit of claim 3, wherein the operational amplifier comprises: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a first resistor, wherein the source terminal of the first PMOS tube is connected with a power voltage, the drain terminal of the first PMOS tube is connected with the gate terminal of the first PMOS tube, the gate terminal of the second PMOS tube and the drain terminal of the first NMOS tube, the source terminal of the second PMOS tube is connected with the power voltage, the drain terminal of the second PMOS tube is connected with the drain terminal of the second NMOS tube and the gate terminal of the fourth NMOS tube, the gate terminal of the first NMOS tube is connected with a reference voltage, the source terminal of the first NMOS tube is connected with the source terminal of the second NMOS tube and the drain terminal of the third NMOS tube, the gate terminal of the second NMOS tube is connected with the source terminal of the fourth NMOS tube and one end of the first resistor, the gate terminal of the third NMOS tube is connected with a first bias voltage, the source end of the third NMOS tube is grounded, the source end of the third PMOS tube is connected with power supply voltage, the drain end of the third PMOS tube is connected to the gate end of the third PMOS tube and the drain end of the fourth NMOS tube and serves as the output end of the operational amplifier, and the other end of the first resistor is grounded.
5. The current steering DAC circuit of claim 3, wherein the current branch control module comprises: a fourth PMOS tube, a fifth NMOS tube, N NMOS current tubes and N NMOS switch tubes, wherein the source terminal of the fourth PMOS tube is connected with a power supply voltage, the gate terminal of the fourth PMOS tube is connected with the output terminal of the operational amplifier, the drain terminal of the fourth PMOS tube is connected with the drain terminal of the fifth NMOS tube, the source terminal of the fifth NMOS tube is grounded, the gate terminal of the fifth NMOS tube is connected with the drain terminal of the fifth NMOS tube and the gate terminals of the N NMOS current tubes to form a second bias voltage, the source terminals of the N NMOS current tubes are grounded, the drain terminals of the N NMOS current sources are correspondingly connected with the source terminals of the N NMOS switch tubes, the gate terminals of the N NMOS switch tubes are correspondingly connected with the N-bit binary code, the drain terminals of the N NMOS switch tubes are connected with the drain terminal of the fifth PMOS tube, and the source terminal of the fifth PMOS tube is connected with the power supply voltage, the grid end of the fifth PMOS tube is connected to the drain end of the fifth PMOS tube and is used as the output end of the current branch control module; wherein N NMOS current tubes and N NMOS switch tubes correspondingly form N current branches, and the NMOS current tube of each current branch comprises 2n-1A plurality of NMOS tubes connected in parallel, N is the row of the current branch circuit corresponding to the NMOS tube in the N current branch circuitsAnd (4) sequencing.
6. The current steering DAC circuit of claim 3 wherein the regulation branch comprises: a PMOS current tube and a PMOS switch tube, wherein the source terminal of the PMOS current tube is connected with the power supply voltage, the grid terminal of the PMOS current tube is connected with the output terminal of the operational amplifier, the drain terminal of the PMOS current tube is connected with the drain terminal of the PMOS switch tube, the grid terminal of the PMOS switch tube is connected with the switch signal output by the comparison circuit, and the source terminal of the PMOS switch tube is used as the output terminal of the regulation branch; the PMOS current tube comprises a PMOS tubes connected in parallel, and a is less than or equal to 2n-1。
7. The current steering DAC circuit of claim 3, wherein the voltage output module comprises: the source end of the sixth PMOS tube is connected with a power supply voltage, the grid end of the sixth PMOS tube is connected with the output end of the current branch control module, the drain end of the sixth PMOS tube is connected with the output end of the adjusting module, one end of the second resistor and one end of the first capacitor and serves as the output end of the voltage output module, the other end of the second resistor is grounded, and the other end of the first capacitor is grounded.
8. The current steering DAC circuit of claim 1, wherein the comparison circuit comprises: at least one comparison module and a NOR gate, the comparison module includes: the output end of the rising edge detection unit and the output end of the falling edge detection unit are connected to the input end of the NOR gate, and the output end of the NOR gate generates the RESET signal.
9. The current steering DAC circuit according to claim 8, wherein the rising edge detection unit comprises: a seventh PMOS transistor, a sixth NMOS transistor, a third resistor, a second capacitor, a first schmitt trigger, a first nand gate, and a first inverter, wherein a source terminal of the seventh PMOS transistor is connected to a power voltage, a drain terminal of the seventh PMOS transistor is connected to one terminal of the third resistor, one terminal of the second capacitor, and an input terminal of the first schmitt trigger, a gate terminal of the seventh PMOS transistor is connected to a gate terminal of the sixth NMOS transistor and an output terminal of the comparator, another terminal of the third resistor is connected to a drain terminal of the sixth NMOS transistor, a source terminal of the sixth NMOS transistor is grounded, another terminal of the second capacitor is grounded, an output terminal of the first schmitt trigger is connected to a first input terminal of the first nand gate, a second input terminal of the first nand gate is connected to an output terminal of the comparator, an output terminal of the first nand gate is connected to an input terminal of the first inverter, and the output end of the first inverter is used as the output end of the rising edge detection unit.
10. The current steering DAC circuit according to claim 8, wherein the falling edge detection unit comprises: an eighth PMOS transistor, a seventh NMOS transistor, a fourth resistor, a third capacitor, a second schmitt trigger, a second nand gate, a second inverter and a third inverter, wherein an input terminal of the second inverter is connected to an output terminal of the comparator, an output terminal of the second inverter is connected to a gate terminal of the eighth PMOS transistor, a gate terminal of the seventh NMOS transistor and a first input terminal of the second nand gate, a power voltage is applied to the eighth PMOS transistor, a drain terminal of the eighth PMOS transistor is connected to one end of the fourth resistor, one end of the third capacitor and an input terminal of the second schmitt trigger, another end of the fourth resistor is connected to a drain terminal of the seventh NMOS transistor, a source terminal of the seventh NMOS transistor is grounded, another end of the third capacitor is grounded, an output terminal of the second schmitt trigger is connected to a second input terminal of the second nand gate, the output end of the second nand gate is connected to the input end of the third inverter, and the output end of the third inverter is used as the output end of the falling edge detection unit.
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CN108449089A (en) * 2018-03-23 2018-08-24 上海唯捷创芯电子技术有限公司 Realize current steering digital-to-analog converter, chip and the communication terminal of digital calibration
CN108491023A (en) * 2018-05-22 2018-09-04 电子科技大学 A kind of current reference circuit of low power consumption high-precision
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CN102447476A (en) * 2010-09-30 2012-05-09 珠海全志科技股份有限公司 Current-steering type digital-to-analog converter
CN103546157A (en) * 2013-10-23 2014-01-29 电子科技大学 Current steering digital-to-analog conversion device
CN104716962A (en) * 2014-12-31 2015-06-17 南京天易合芯电子有限公司 Digital-analog converter unit and current steering type digital-analog converter
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