CN112701562B - Multi-path synchronous output laser light source module - Google Patents
Multi-path synchronous output laser light source module Download PDFInfo
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- CN112701562B CN112701562B CN202011597497.1A CN202011597497A CN112701562B CN 112701562 B CN112701562 B CN 112701562B CN 202011597497 A CN202011597497 A CN 202011597497A CN 112701562 B CN112701562 B CN 112701562B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0428—Electrical excitation ; Circuits therefor for applying pulses to the laser
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
- H01S5/068—Stabilisation of laser output parameters
- H01S5/06804—Stabilisation of laser output parameters by monitoring an external parameter, e.g. temperature
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Abstract
The invention discloses a multi-path synchronous output laser light source module which comprises a multi-path laser light source generating circuit, a temperature control circuit and a processor, wherein the multi-path laser light source generating circuit comprises a trigger signal synchronous circuit, a driving circuit and a DFB laser modulation circuit; any one path of trigger signal synchronizing circuit, the driving circuit and the DFB laser modulation circuit are connected with the processor, the temperature control circuit collects the temperature in the cavity of the DFB laser modulation circuit and feeds the temperature back to the processor, and the processor adjusts the temperature according to the control TEC refrigeration piece. The invention adopts the delay circuit and the processor to carry out delay adjustment on the circuit, accurately controls the trigger signal of each laser, realizes that each laser can emit light at the same phase moment, thereby realizing the light source output of a multi-path synchronous output laser, having high control accuracy and ensuring the system performance.
Description
Technical Field
The invention relates to the field of lasers, in particular to a multi-path synchronous output laser light source module.
Background
At present, a QKD (Quantum Key Distribution) communication system is mainly based on a BB84 protocol, and encoding of the protocol requires that a sending end of the QKD system needs to prepare two groups of non-orthogonal four polarization state single photons.
In the existing engineering scheme, two methods are generally used for realizing the preparation of single photons in four polarization states.
One method is as follows: a laser LD is used as a light source, the beam splitter BS divides the light into four parts, the four light paths after light splitting are respectively and sequentially connected with an intensity modulator IM, a polarization beam splitter PBS and an electric control polarization controller EPC to realize the preparation of the polarization state single photon of each branch, and finally the light beams are combined through the BS to be output to an optical fiber.
The other method comprises the following steps: four lasers LD are used as light sources, a polarization beam splitter PBS and a polarization state controller EPC are sequentially connected to four light paths respectively to realize the preparation of a polarization state single photon of each light path, and finally the polarization state single photon is output to an optical fiber through a BS combined beam.
Since the cost of the intensity modulator IM is very high, method one can only be adopted in scientific research systems, while in commercial systems, method two is more adopted. However, in the second method, because the four lasers LD are used as the system light source, if the phases of the output moments of the four lasers LD cannot be guaranteed to be consistent, hidden danger exists in system safety. Therefore, there is a need to improve the prior art and provide a multichannel synchronous output laser light source system with better precision and system safety.
Disclosure of Invention
In order to solve the technical problem, a multichannel synchronous output laser light source system which has better precision and ensures the system safety is provided.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a multi-path synchronous output laser light source module comprises a multi-path laser light source generating circuit, a temperature control circuit and a processor, wherein:
the multi-path laser light source generating circuit comprises a trigger signal synchronous circuit, a driving circuit and a DFB laser modulation circuit;
in this embodiment, the multi-path laser light source has 4 paths of laser light sources in total, and the 4 paths of laser light sources emit laser trigger signals.
Any one path of trigger signal synchronization circuit is connected with the processor, and the processor controls the trigger signal synchronization circuit to correspondingly delay and adjust the trigger signal;
any one path of driving circuit is connected with the processor, and the processor controls the driving circuit to carry out ultra-narrow pulse width modulation and amplification processing on the trigger signal;
any DFB (Distributed Feedback) laser modulation circuit is connected with a temperature control circuit, the temperature control circuit is connected with the processor, the temperature control circuit collects the temperature in the cavity of the DFB laser modulation circuit and feeds the temperature back to the processor, the processor calculates an adjusted value according to the received temperature data and a PID (Proportion integration differentiation) algorithm, and sends the adjusted value to a TEC (Thermo Electric Cooler) refrigeration piece of the DFB laser modulation circuit to adjust the temperature;
the trigger signal synchronization circuit comprises a trigger signal delay chip, and the adjustment range of the trigger signal delay chip is as follows: and signal delay adjustment of 10ps stepping in a 10ns range is realized.
Preferably, the model of the trigger signal delay chip is MC100EP196BFAR2G.
Preferably, the driving circuit comprises a narrow pulse generating circuit and a signal modulating and amplifying circuit, wherein the narrow pulse generating circuit is used for adjusting the trigger signal into an ultra-narrow pulse width signal, enhancing and driving the ultra-narrow pulse width signal and then sending the ultra-narrow pulse width signal to the signal modulating and amplifying circuit;
and the signal modulation and amplification circuit amplifies the received signal and then transmits the amplified signal to the DFB laser modulation circuit.
Preferably, the narrow pulse generating circuit comprises a level conversion chip, a narrow pulse delay chip and a level driving chip;
one path of trigger signal is divided into two paths of differential signals after passing through a level conversion chip, the two paths of trigger signals are output, the two groups of differential signals are input into a narrow pulse delay chip, the processor adjusts the signal delay value in the narrow pulse delay chip through an SPI bus, the difference between the two groups of differential signals is 100ps, and then the two groups of differential signals are input into a level driving chip, are synthesized into a path of 100ps ultra-narrow pulse width signal, are subjected to enhanced driving and are output to a DFB laser modulation circuit.
Preferably, the signal modulation and amplification circuit comprises a signal modulation DAC chip and a signal amplification chip, the FPGA chip of the processor adjusts the output of the signal modulation DAC chip through an I2C bus, and the signal is amplified through the signal amplification chip and then output to the DFB laser modulation circuit.
Preferably, the type of the divided level conversion chip is NB7L11M, the type of the narrow pulse delay chip is NB6L295MNTXG, and the type of the level driving chip is MC100LVEP05;
the model of the signal modulation DAC chip is AD5665RBRUZ-2, and the model of the signal amplification chip is OPA4188AIPW.
Preferably, the temperature control circuit comprises a temperature acquisition circuit, a temperature control ADC circuit, a temperature control DAC circuit, an amplification circuit, and a TEC drive circuit, wherein the temperature acquisition circuit is configured to acquire a temperature in the cavity of the DFB laser module, input the temperature into the temperature control ADC circuit, perform digital-to-analog conversion, and then transmit the temperature to the processor;
preferably, the processor reads real-time temperature acquisition data of the temperature control ADC circuit through the SPI bus, calculates temperature adjustment data according to a PID algorithm, outputs the temperature adjustment data to the temperature control DAC circuit through the I2C bus, performs analog-to-digital conversion on the temperature adjustment data, sends the temperature adjustment data to the amplification circuit for signal amplification, and then inputs the temperature adjustment data to the TEC drive circuit, and the TEC drive circuit generates drive voltage of the TEC refrigeration plate according to the received data to complete temperature adjustment.
Preferably, the temperature acquisition circuit comprises an operational amplifier, and the operational amplifier carries out direct current bias and amplification on a voltage signal output by a thermistor in a cavity of the DFB laser module and inputs the voltage signal into the temperature control ADC circuit;
the model of the operational amplifier is OPA4350UA.
Preferably, the temperature-controlled ADC circuit includes an ADC chip ADS8370IB; the temperature control DAC circuit comprises a DAC chip AD5665RBRUZ-2; the TEC driving circuit comprises a TEC driving chip MAX8520ETP.
The invention has the beneficial technical effects that:
the invention adopts the delay circuit and the processor to carry out delay adjustment on the circuit, accurately controls the trigger signal of each laser, realizes that each laser can emit light at the same phase moment, thereby realizing the light source output of a multi-path synchronous output laser, having high control accuracy and ensuring the system performance.
The invention has stable work and lower cost, and is suitable for being used as a basic unit for preparing a single photon source to be applied to commercial product integration and scientific research systems in the quantum communication industry.
Drawings
FIG. 1 is a block diagram of the overall structure of the present invention;
FIG. 2 is a block diagram of the overall structure of the trigger signal synchronizing circuit according to the present invention;
FIG. 3 is a schematic diagram of a part of a trigger signal synchronizing circuit according to the present invention;
FIG. 4 is a block diagram showing the overall structure of a driving circuit according to the present invention;
fig. 5 is a block diagram showing the overall structure of the temperature control circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments, but the scope of the present invention is not limited to the following embodiments.
As shown in fig. 1, a multi-channel synchronous output laser light source module includes a multi-channel laser light source generating circuit, a temperature control circuit and a processor, wherein:
the multiple laser light source generating circuits are arranged in parallel, and each laser light source generating circuit is connected with the processor and the temperature control circuit; the temperature control circuit is connected with the processor, and the temperature of each path of laser light source generating circuit is controlled through the processor.
Specifically, each laser light source generating circuit comprises a trigger signal synchronization circuit, a driving circuit and a DFB laser modulation circuit;
any path of trigger signal synchronization circuit is connected with the processor, and the processor controls the trigger signal synchronization circuit to perform corresponding delay adjustment on the trigger signal;
any one path of driving circuit is connected with the processor, and the processor controls the driving circuit to carry out ultra-narrow pulse width modulation and amplification processing on the trigger signal;
any DFB laser modulation circuit is connected with a temperature control circuit, the temperature control circuit is also connected with the processor, the temperature control circuit collects the temperature in the cavity of the DFB laser modulation circuit and feeds the temperature back to the processor, the processor calculates an adjusted value according to the received temperature data and a PID algorithm, and sends the adjusted value to a TEC (thermoelectric cooler) of the DFB laser modulation circuit to adjust the temperature;
specifically, the trigger signal synchronization circuit includes a trigger signal delay chip, and the adjustment range of the trigger signal delay chip is as follows: the signal delay adjustment of stepping 10ps in the range of 10ns is realized, specifically, the signal delay adjustment of stepping 10ps in the range of 2.2ns to 12.4ns is realized in the embodiment.
The processor adopts an FPGA processor, the model of a chip of the FPGA processor adopts an EP4CGX150 series or other chips with the same index model, the model of an EP4CGX150DF27I7 chip is adopted in the embodiment, and the processor controls the trigger signal delay chip to step by 10ps of signal delay adjustment from 2.2ns to 12.4ns through a 10-bit bus.
As shown in fig. 3, the processor FPGA is connected to the input/output ports D0 to D10 of the trigger signal Delay chip U1 through a 10-bit bus SI-Delay, the external trigger signal of the laser is input from the input pins 4 and 5 of the trigger signal Delay chip U1, and is delayed and output from the output pins 20 and 21 after being delayed, the trigger signal Delay chip may be an MC100EP196 series or other chips with the same index model, and an MC100EP196BFAR2G chip is used in this embodiment.
Referring specifically to fig. 1, the specific process of the trigger signal synchronization circuit controlled by the processor is as follows: taking a first path of laser external signal 1# and a second path of laser external signal 2# as an example, two paths of lasers simultaneously send out trigger signals, the two paths of signals sequentially pass through a trigger signal synchronization circuit, a driving circuit and a DFB laser modulation circuit and then output processed laser signals, at this time, an oscilloscope is needed to be connected with the 2 paths of circuits, the processed laser signals are input into the oscilloscope, the time difference of the two paths of light paths is obtained through a waveform diagram of the oscilloscope, the oscilloscope can also be directly connected to a processor, and the obtained time difference T is sent to the processor. Because the multiple lasers emit trigger signals almost simultaneously, the time interval between the two optical paths is between 2.2ns and 12.4 ns.
If the signal of the first path of signal 1# is earlier than the signal of the second path of signal 2#, the processor controls the trigger signal synchronous circuit of the first path of laser light source generating circuit to delay the laser trigger signal of the ground path for time T, and after the delay, the signals output by the two paths of laser light source generating circuits can be synchronously output.
The driving circuit comprises a narrow pulse generating circuit and a signal modulating and amplifying circuit, wherein the narrow pulse generating circuit is used for adjusting the trigger signal into an ultra-narrow pulse width signal, performing enhanced driving on the ultra-narrow pulse width signal and then sending the ultra-narrow pulse width signal to the signal modulating and amplifying circuit;
and the signal modulation and amplification circuit amplifies the received signal and then transmits the amplified signal to the DFB laser modulation circuit.
Preferably, the narrow pulse generating circuit comprises a level conversion chip divided into two parts, a narrow pulse delay chip and a level driving chip, wherein the level driving chip is an LVPECL level driving chip;
one path of trigger signal is divided into two paths of differential signals after passing through a level conversion chip, the two paths of trigger signals are output, the two groups of differential signals are input into a narrow pulse delay chip, the processor adjusts the signal delay value in the narrow pulse delay chip through an SPI bus, the difference between the two groups of differential signals is 100ps, and then the two groups of differential signals are input into a level driving chip, combined into a path of 100ps ultra-narrow pulse width signal, subjected to enhanced driving and output to a DFB laser modulation circuit.
The signal modulation and amplification circuit comprises a signal modulation DAC chip and a signal amplification chip, the FPGA chip of the processor adjusts the output of the signal modulation DAC chip through an I2C bus, and the signal is amplified through the signal amplification chip and then output to the DFB laser modulation circuit.
Specifically, the type of the split level conversion chip may be NB7L11M series or other equivalent index types, specifically, an NB7L11M chip and a narrow pulse delay chip may be NB6L295 series or other equivalent index types, in this embodiment, an NB6L295MNTXG chip and a level driving chip may be MC100LVEP05 series or other equivalent index types, and in this embodiment, the type is MC100LVEP05; the signal modulation DAC chip can select AD5665 series or other equivalent index models, the embodiment adopts AD5665RBRUZ-2, the signal amplification chip can select OPA4188 series or other equivalent index models, and the embodiment adopts OPA4188AIPW.
The circuit comprises a two-level conversion chip, a narrow pulse delay chip, an LVPECL level driving chip and a DFB laser modulation circuit which are sequentially connected; the modulation DAC chip and the signal amplification chip are sequentially connected, and the signal amplification chip is in electrical signal connection with the DFB laser modulation circuit; the FPCA processor is respectively connected with the narrow pulse delay chip and the modulation DAC chip through electric signals to drive and control the narrow pulse delay chip and the modulation DAC chip.
Specifically, the working principle of the whole driving circuit is as follows: one path of trigger signal is divided into two level conversion chips (NB 7L 11M) to output two groups of differential signals, and then the two groups of differential signals are input into a narrow pulse delay chip (NB 6L295 MNTXG); the FPGA chip EP4CGX150DF27I7 of the processor adjusts the internal signal delay value of a narrow pulse delay chip (NB 6L295 MNTXG) through an SPI bus, so that the difference between two groups of differential signals is 100ps, and then the signals are input to a chip level driving chip; the level driving chip (MC 100LVEP 05) is used for synthesizing two groups of differential signals into one path of differential signal, enhancing the driving and then outputting the differential signal, thereby generating an ultra-narrow pulse width signal of 100 ps; the signal is output to a DFB laser modulation circuit.
The FPGA processor adjusts the output of the modulation signal modulation DAC chip (AD 5665 RBRUZ-2) through an I2C bus, and the signal is amplified through the signal amplification chip (OPA 4188 AIPW) and then output to the DFB laser modulation circuit.
In summary, the narrow pulse generating circuit and the signal modulating and amplifying circuit are used to jointly generate the driving signal to drive the DFB laser and then output the laser light source with the ultra-narrow pulse width of 100 ps.
The temperature control circuit comprises a temperature acquisition circuit, a temperature control ADC circuit, a temperature control DAC circuit, an amplification circuit and a TEC drive circuit, wherein the temperature acquisition circuit is used for acquiring the temperature in the DFB laser module cavity, inputting the temperature into the temperature control ADC circuit for digital-to-analog conversion and then sending the temperature to the processor;
preferably, the processor reads real-time temperature acquisition data of the temperature control ADC circuit through the SPI bus, calculates temperature adjustment data according to a PID algorithm, outputs the temperature adjustment data to the temperature control DAC circuit through the I2C bus, performs analog-to-digital conversion on the temperature adjustment data, sends the temperature adjustment data to the amplification circuit for signal amplification, and then inputs the temperature adjustment data to the TEC drive circuit, and the TEC drive circuit generates drive voltage of the TEC refrigeration plate according to the received data to complete temperature adjustment.
Preferably, the temperature acquisition circuit comprises an operational amplifier with an OPA4350UA model, and the operational amplifier performs dc bias and amplification on a voltage signal output by a thermistor TH in a cavity of the DFB laser module and inputs the voltage signal to the temperature control ADC circuit. The temperature control ADC circuit comprises an ADC chip (the ADC chip can select ADS8370 series or other equivalent index models, and the model adopted in the embodiment is ADS8370 IB); the temperature control DAC circuit comprises a DAC chip (the DAC chip can select AD5665 series or other equivalent index models, and the model of the embodiment is AD5665 RBRUZ-2); the TEC driving circuit comprises a TEC driving chip (the TEC driving chip can be MAX8520 series or other equivalent index models, and the model of the TEC driving chip is MAX8520 ETP).
The temperature acquisition circuit is connected with a TH thermistor in the DFB laser module, then the temperature control ADC circuit is connected with the FPGA processor, and the FPGA processor is connected with the temperature control DAC circuit; the temperature control DAC circuit, the amplifying circuit and the TEC driving circuit are sequentially connected, and the TEC driving circuit is connected with a TEC refrigerating piece in the DFB laser module.
The temperature control circuit is used for feeding back the temperature in the DFB laser cavity to the processor by acquiring, and the processor controls the temperature of the TEC refrigerating plate in the DFB laser according to a PID algorithm (in the process control, a PID controller (also called a PID regulator) which controls according to the proportion (P), the integral (I) and the derivative (D) of the deviation is an automatic controller which is most widely applied), so that the rapid adjustment of the temperature in the DFB laser cavity is realized, and the stable 25-DEG C working temperature requirement of the DFB laser is ensured.
Variations and modifications to the above-described embodiments may occur to those skilled in the art based upon the disclosure and teachings of the above specification. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and variations of the present invention should fall within the scope of the claims of the present invention. Furthermore, although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (9)
1. The utility model provides a multichannel synchronization output laser light source module which characterized in that, includes multichannel laser light source production circuit, temperature control circuit and treater, wherein:
the multi-path laser light source generating circuit comprises a trigger signal synchronous circuit, a driving circuit and a DFB laser modulation circuit;
any path of trigger signal synchronization circuit is connected with the processor, and the processor controls the trigger signal synchronization circuit to perform corresponding delay adjustment on the trigger signal; the trigger signal synchronization circuit comprises a trigger signal delay chip, and the adjustment range of the trigger signal delay chip is as follows: the signal delay adjustment of stepping 10ps within the range of 10ns is realized;
any one path of driving circuit is connected with the processor, and the processor controls the driving circuit to carry out ultra-narrow pulse width modulation and amplification processing on the trigger signal;
any one DFB laser modulation circuit is connected with a temperature control circuit, the temperature control circuit is also connected with the processor, the temperature control circuit collects the temperature in the cavity of the DFB laser modulation circuit and feeds the temperature back to the processor, the processor calculates an adjusted value according to the received temperature data and by combining a PID algorithm, and sends the adjusted value to a TEC refrigeration piece of the DFB laser modulation circuit to adjust the temperature;
the driving circuit comprises a narrow pulse generating circuit and a signal modulating and amplifying circuit;
the narrow pulse generating circuit comprises a level conversion chip, a narrow pulse delay chip and a level driving chip which are divided into two parts;
one path of trigger signal is divided into two paths of differential signals after passing through the two level conversion chips, then the two paths of differential signals are output, then the two paths of differential signals are input into the narrow pulse delay chip, the processor adjusts the signal delay value in the narrow pulse delay chip through the SPI bus, the two groups of differential signals have a phase difference of 100ps, then the two groups of differential signals are input into the level driving chip, the two groups of differential signals are synthesized into a path of 100ps ultra-narrow pulse width signal, the ultra-narrow pulse width signal is enhanced and driven, and then the ultra-narrow pulse width signal is output to the DFB laser modulation circuit.
2. The light source module of claim 1, wherein the trigger delay chip is an MC100EP196 series chip.
3. The light source module of claim 1, wherein the narrow pulse generating circuit is configured to adjust the trigger signal to an ultra-narrow pulse width signal, to drive the trigger signal in an enhanced manner, and to send the trigger signal to the signal modulating and amplifying circuit;
and the signal modulation and amplification circuit amplifies the received signal and then transmits the amplified signal to the DFB laser modulation circuit.
4. The light source module of claim 3, wherein the signal modulation and amplification circuit comprises a signal modulation DAC chip and a signal amplification chip, and the FPGA chip adjusts the output of the signal modulation DAC chip through the I2C bus, and amplifies the signal through the signal amplification chip and outputs the amplified signal to the DFB laser modulation circuit.
5. The light source module of claim 3, wherein the split level shifter chip is an NB7L11M series chip, the narrow pulse delay chip is an NB6L295 series chip, and the level driver chip is an MC100LVEP05 series chip;
the signal modulation DAC chip adopts an AD5665 series chip, and the signal amplification chip adopts an OPA4188 series chip.
6. The light source module of claim 1, wherein the temperature control circuit comprises a temperature acquisition circuit, a temperature control ADC circuit, a temperature control DAC circuit, an amplifier circuit, and a TEC driver circuit, and the temperature acquisition circuit is configured to acquire temperature in the DFB laser module cavity, input the temperature to the temperature control ADC circuit for digital-to-analog conversion, and send the temperature to the processor.
7. The light source module of claim 6, wherein the processor reads real-time temperature acquisition data of the temperature-controlled ADC circuit through the SPI bus, calculates temperature adjustment data according to a PID algorithm, outputs the temperature adjustment data to the temperature-controlled DAC circuit through the I2C bus for analog-to-digital conversion, sends the temperature adjustment data to the amplifying circuit for signal amplification, and inputs the temperature adjustment data to the TEC driving circuit, and the TEC driving circuit generates a driving voltage of the TEC cooling plate according to the received data to complete temperature adjustment.
8. The light source module of claim 7, wherein the temperature acquisition circuit comprises an operational amplifier, and the operational amplifier performs dc bias and amplification on a voltage signal output by a thermistor in the cavity of the DFB laser module, and inputs the voltage signal to the temperature-controlled ADC circuit;
the chips of the operational amplifier adopt OPA4350 series chips.
9. The light source module of claim 8, wherein the temperature controlled ADC circuit comprises an ADC chip, and the ADC chip is an ADS8370 series chip; the temperature control DAC circuit comprises a DAC chip, and the DAC chip adopts an AD5665 series chip; the TEC driving circuit comprises a TEC driving chip, and the type of the TEC driving chip adopts MAX8520 series chips.
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