CN112701120A - SRAM (static random Access memory), forming method thereof and electronic device - Google Patents
SRAM (static random Access memory), forming method thereof and electronic device Download PDFInfo
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- CN112701120A CN112701120A CN201911012006.XA CN201911012006A CN112701120A CN 112701120 A CN112701120 A CN 112701120A CN 201911012006 A CN201911012006 A CN 201911012006A CN 112701120 A CN112701120 A CN 112701120A
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 230000003068 static effect Effects 0.000 title description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 238000000226 double patterning lithography Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for forming an SRAM, which comprises the following steps: providing a substrate; forming an NMOS device region comprising a first semiconductor material and a PMOS device region comprising a second semiconductor material on a substrate, wherein the first semiconductor material is SiP and the second semiconductor material is SiGe; a fin structure is formed including a first fin and a second fin, wherein the first fin is formed in an NMOS device region and the second fin is formed in a PMOS device region. Compared with the traditional fin structure which is composed of Si and positioned in the NMOS device, the method for forming the SRAM can improve the performance of the SRAM by about 20-30%.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to an SRAM, a method for forming the same, and an electronic device.
Background
Static Random Access Memory (SRAM), an important memory device, is widely used in digital and communication circuit design, and is widely used for data storage due to its advantages of low power consumption, fast reading speed, etc.
In the Field of semiconductor integrated circuit devices, Field Effect Transistors (FETs), abbreviated as FETs, have been the main semiconductor devices used to manufacture products such as application specific integrated circuit chips, Static Random Access Memory (SRAM) chips, and the like.
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component or line that can be made using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs, and similar developments in semiconductor manufacturing are required to achieve such advances.
For example, as the semiconductor industry has progressed to nanotechnology processing nodes pursuing higher device densities, higher performance, and lower costs, challenges from both fabrication and design have led to the development of fin field effect transistor (FinFET) devices. For example, the FinFET device may be a Complementary Metal Oxide Semiconductor (CMOS) device, including a P-type metal oxide semiconductor (PMOS) FinFET device and an N-type metal oxide semiconductor (NMOS) FinFET device. CMOS technology is widely used for a variety of circuit designs. Accordingly, it is desirable to have improvements in the fabrication of CMOS FinFET semiconductor structures.
Disclosure of Invention
The invention aims to provide an SRAM, a forming method thereof and an electronic device.
The technical scheme adopted by the invention is as follows: a forming method for constructing an SRAM comprises the following steps:
providing a substrate;
forming an NMOS device region comprising a first semiconductor material and a PMOS device region comprising a second semiconductor material on the substrate, wherein the first semiconductor material is SiP and the second semiconductor material is SiGe;
forming a fin structure comprising a first fin and a second fin, wherein the first fin is formed in the NMOS device region and the second fin is formed in the PMOS device region.
In the forming method of the SRAM provided by the present invention, the step of forming a fin structure including a first fin and a second fin includes:
depositing a hybrid resist layer on the NMOS device region and the PMOS device region;
patterning the resist to form gaps in the mixed resist layer;
performing an etch to form the fin structure in the NMOS device region and the PMOS device region.
In the forming method of the SRAM provided by the present invention, the height of the first fin and the second fin is 30 to 100 nm.
According to another aspect of the present invention, there is also provided an SRAM, including:
the device comprises a substrate, wherein an NMOS device region containing a first semiconductor material and a PMOS device region containing a second semiconductor material are formed on the substrate, the first semiconductor material is SiP, and the second semiconductor material is SiGe;
a fin structure comprising a first fin and a second fin, wherein the first fin is formed in the NMOS device region and the second fin is formed in the PMOS device region.
In the SRAM provided by the invention, the substrate is made of Si.
In the SRAM provided by the present invention, the first fin and the second fin have a height of 30 to 100 nm.
In the SRAM provided by the invention, the SRAM has a 6T structure.
According to another aspect of the present invention, there is also provided a sub-device including the SRAM as described above.
The SRAM, the forming method thereof and the electronic device have the following beneficial effects: compared with the traditional fin structure which is composed of Si and positioned in the NMOS device, the method for forming the SRAM can improve the performance of the SRAM by about 20-30%.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:
FIG. 1 is a flow chart of a method for forming an SRAM according to an embodiment of the present invention;
FIG. 2 is a block diagram of the SRAM provided in one embodiment of the present invention;
fig. 3 is a semiconductor structure according to an embodiment of the invention after a subsequent processing step of fin formation.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
In order to thoroughly understand the present invention, detailed steps will be set forth in the following description in order to explain the SRAM and the method of manufacturing the same, and the electronic device according to the present invention. It will be apparent that the invention may be practiced without limitation to specific details that are within the skill of one of ordinary skill in the semiconductor arts. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
An example of a device that may be derived from one or more embodiments of the present application is an SRAM. For example, such a device may be a Complementary Metal Oxide Semiconductor (CMOS) device including a P-type metal oxide semiconductor (PMOS) FinFET device and an N-type metal oxide semiconductor (NMOS) FinFET device. The following disclosure will continue to employ the CMOS FinFET example to illustrate various embodiments of the present application. It should be understood, however, that the present application is not limited to a particular type of device, except as specifically claimed.
In the present invention, the SRAM is a CMOS FinFET device. The CMOS FinFET devices include NMOS FinFET devices and PMOS FinFET devices. The FinFET device may be included in a microprocessor, memory cell, and/or other integrated circuit device. For the purpose of clarity and to better understand the inventive concepts of the present invention, the drawings have been simplified. Additional features may be added to the CMOS FinFET device, and some of the features described below may be replaced or removed in other embodiments of the CMOS FinFET device.
In order to solve the foregoing technical problem, the present invention provides a method for forming an SRAM, as shown in fig. 1, which mainly includes the following steps:
step S101, providing a substrate;
in particular, the semiconductor substrate is a bulk silicon substrate, which may be at least one of the materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like.
Step S102, forming an NMOS device area containing a first semiconductor material and a PMOS device area containing a second semiconductor material on the substrate, wherein the first semiconductor material is SiP, and the second semiconductor material is SiGe;
specifically, substrate 210 forms the base of the SRAM. The NMOS device region 220 is composed of SiP, the PMOS device region 230 is composed of SiGe, and the PMOS device region 230 is disposed on one side of the NMOS device region 220.
Step S103, forming a fin structure including a first fin and a second fin, wherein the first fin is formed in the NMOS device region, and the second fin is formed in the PMOS device region.
In particular, the first and second fins have a height of 30 to 100 nm. The fin structure (including the plurality of fins 212a-212d) is formed by any suitable process, such as a photolithography process and an etching process. For example, in the present embodiment, the fin structure is formed by: depositing a hybrid resist layer on the NMOS device region and the PMOS device region; patterning the resist to form gaps in the mixed resist layer; performing an etch to form the fin structure in the NMOS device region and the PMOS device region.
In some embodiments, the fin structure is formed by: the method includes exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer and a mask layer. The photoresist layer patterning may comprise the following process steps: photoresist coating, soft baking, mask alignment, pattern exposure, post exposure baking, photoresist development, and hard baking. In some embodiments, patterning may also be performed or replaced by other suitable methods, such as maskless lithography, e-beam writing, ion-beam writing, and molecular imprinting. The mask elements (including the photoresist layer and the mask layer) may then be used in an etching process to etch the fin structure into the substrate 210. The etch process uses a patterned masking layer to define the etched areas and to protect other areas of the cmos finfet device. In some embodiments, the etching process comprises a wet etching process, a dry etching process, or a combination thereof. The fin structure may be formed by an etching process using a plasma etch and/or other suitable processes. In one example, hydrofluoric acid (HF) or buffered hydrofluoric acid solution (buffered HF) is used to etch the dielectric layer to expose the substrate 210 according to a pattern defined by the mask layer. In another example, the dry etch process used to etch substrate 210 includes a fluorine gas containing chemistry. In yet another example, the dry etch chemistry includes CF4, SF6, or NF 3. Optionally, the fin structure is formed by a Double Patterning Lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows for increased component (e.g., fin) density. Various DPL methods that may be used include double exposure (e.g., using two mask sets).
In particular, it is noted that the method of forming the first fin and the second fin is merely exemplary and not limited to the above method.
In one example, various well structures are also formed in the semiconductor substrate, such as an N-type well formed in the PMOS device region and a P-type well formed in the NMOS device region.
Fig. 2 is a structural diagram of an SRAM provided in an embodiment of the present invention at the beginning. Bulk substrate 210 forms the base of the semiconductor structure. The bulk substrate 210 may be composed of any of several known semiconductor materials, such as Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors. In an embodiment, NMOS device region 220 is comprised of SiP, PMOS device region 230 is comprised of SiGe, and PMOS device region 230 is disposed on one side of NMOS device region 220. Fig. 3 is a semiconductor structure according to an embodiment of the invention after a subsequent processing step of fin formation. As shown in fig. 3, the finally formed SRAM includes a fin structure composed of a first fin (212a and 212b) and a second fin (212c and 212d), wherein the first fin is formed in the NMOS device region, and the second fin is formed in the PMOS device region. The first and second fins have a height of 30 to 100 nm. Specifically, the formed SRAM has a 6T structure including 4 NMOS transistors and 2 PMOS transistors.
The present invention also provides an electronic device including an SRAM manufactured according to the method of the exemplary embodiment of the present invention. The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including the SRAM. The electronic device has better performance due to the use of the SRAM.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. A method for forming an SRAM includes:
providing a substrate;
forming an NMOS device region comprising a first semiconductor material and a PMOS device region comprising a second semiconductor material on the substrate, wherein the first semiconductor material is SiP and the second semiconductor material is SiGe;
forming a fin structure comprising a first fin and a second fin, wherein the first fin is formed in the NMOS device region and the second fin is formed in the PMOS device region.
2. The method of forming the SRAM of claim 1, wherein the step of forming a fin structure comprising a first fin and a second fin comprises:
depositing a hybrid resist layer on the NMOS device region and the PMOS device region;
patterning the resist to form gaps in the mixed resist layer;
performing an etch to form the fin structure in the NMOS device region and the PMOS device region.
3. The method of claim 1, wherein the first fin and the second fin have a height of 30 to 100 nm.
4. An SRAM, comprising:
the device comprises a substrate, wherein an NMOS device region containing a first semiconductor material and a PMOS device region containing a second semiconductor material are formed on the substrate, the first semiconductor material is SiP, and the second semiconductor material is SiGe;
a fin structure comprising a first fin and a second fin, wherein the first fin is formed in the NMOS device region and the second fin is formed in the PMOS device region.
5. The SRAM of claim 4, wherein the material of the substrate is Si.
6. The SRAM of claim 4, wherein the first fin and the second fin have a height of 30 to 100 nm.
7. The SRAM of claim 4, wherein the SRAM has a 6T structure.
8. An electronic device comprising the SRAM of any one of claims 4 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911012006.XA CN112701120A (en) | 2019-10-23 | 2019-10-23 | SRAM (static random Access memory), forming method thereof and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911012006.XA CN112701120A (en) | 2019-10-23 | 2019-10-23 | SRAM (static random Access memory), forming method thereof and electronic device |
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| CN112701120A true CN112701120A (en) | 2021-04-23 |
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| CN201911012006.XA Pending CN112701120A (en) | 2019-10-23 | 2019-10-23 | SRAM (static random Access memory), forming method thereof and electronic device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023605A (en) * | 2014-04-18 | 2015-11-04 | 台湾积体电路制造股份有限公司 | Connection structure for vertical gate all around (VGAA) devices on a semiconductor-on-insulator (SOI) substrate |
| US9281400B1 (en) * | 2015-04-08 | 2016-03-08 | United Microelectronics Corp. | Method of fabricating a semiconductor device with fin-shaped structures |
| US20190096891A1 (en) * | 2017-09-28 | 2019-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ic including standard cells and sram cells |
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2019
- 2019-10-23 CN CN201911012006.XA patent/CN112701120A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023605A (en) * | 2014-04-18 | 2015-11-04 | 台湾积体电路制造股份有限公司 | Connection structure for vertical gate all around (VGAA) devices on a semiconductor-on-insulator (SOI) substrate |
| US9281400B1 (en) * | 2015-04-08 | 2016-03-08 | United Microelectronics Corp. | Method of fabricating a semiconductor device with fin-shaped structures |
| US20190096891A1 (en) * | 2017-09-28 | 2019-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ic including standard cells and sram cells |
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Application publication date: 20210423 |
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