CN112701084A - Structure of flexible thin film transistor array and manufacturing method thereof - Google Patents

Structure of flexible thin film transistor array and manufacturing method thereof Download PDF

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Publication number
CN112701084A
CN112701084A CN202011592468.6A CN202011592468A CN112701084A CN 112701084 A CN112701084 A CN 112701084A CN 202011592468 A CN202011592468 A CN 202011592468A CN 112701084 A CN112701084 A CN 112701084A
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layer
thin film
film transistor
substrate
metal
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CN112701084B (en
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陆磊
张盛东
焦海龙
张敏
周航
周雨恒
王云萍
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

The structure comprises a substrate and a thin film transistor array formed on the substrate, wherein an active layer in the thin film transistor is vertical to the substrate, the structure also comprises a metal connecting wire, the metal connecting wire is used for connecting each thin film transistor to a scanning module or a data module, and the metal connecting wire is a connecting wire with a bending path. The active layer is vertical to the substrate, the metal connecting wire in the wiring is a connecting wire with a bending path, when the device is bent, the stress on the device is reduced, the stability of each transistor is improved, the metal connecting wire is a connecting wire with a bending path, the metal connecting wire is not easy to break when stressed, the tolerance capability is strong, the stress problem when the whole flexible thin film transistor array is bent or stretched can be further improved, and the stability of the whole flexible thin film transistor array is improved.

Description

Structure of flexible thin film transistor array and manufacturing method thereof
Technical Field
The invention relates to the technical field of flexible electronics, in particular to a structure of a flexible thin film transistor array and a manufacturing method thereof.
Background
With the development of display technology, flexible display panels are becoming one of the most interesting categories of display panels. Organic Light-Emitting Diode (OLED) display panels are one of the mainstream technologies of flexible display panels due to their self-luminescence, high contrast ratio and flexible characteristics.
The active layer plane of the thin film transistor array of the flexible electron in the prior art is the same as the bendable direction, and when the thin film transistor array is bent, the performance of the device is seriously influenced, and the stability is reduced.
Disclosure of Invention
The invention mainly solves the technical problem of providing a structure of a flexible thin film transistor array and a manufacturing method thereof, and improving the performance stability of a device.
According to a first aspect, an embodiment provides a method of manufacturing a flexible thin film transistor array, comprising:
providing a substrate;
forming a thin film transistor array on the substrate, wherein a channel region in the thin film transistor is vertical to the substrate;
and forming a metal connecting wire, wherein the metal connecting wire is used for connecting each thin film transistor to the scanning module or the data module, and the metal connecting wire is a connecting wire with a bent path.
In some embodiments, forming a thin film transistor array on the substrate includes:
forming a source layer on the substrate, wherein the source layer is located on a part of the surface of the substrate, the part of the surface of the source layer is a first part of the surface, and the rest part of the surface of the source layer is a second part of the surface;
sequentially depositing an insulating medium layer and a drain layer on the first part surface of the source layer;
forming a control layer, the control layer comprising: the gate dielectric layer is positioned between the active layer and the gate electrode layer, and the active layer is vertical to the substrate;
and forming a passivation layer which covers the rest part of the surface of the substrate, the second part of the surface of the source layer, the surface of the drain layer and the side surfaces and the surfaces of the control layer.
In some embodiments, the control layer is located on the same side of the source layer, the insulating dielectric layer and the drain layer, and is perpendicular to the substrate.
In some embodiments, forming the control layer comprises:
depositing an active layer, wherein the active layer covers part of the surface of the substrate, the side surfaces of the source electrode layer and the insulating medium layer, and the side surfaces and the surface of the drain electrode layer;
sequentially depositing a gate dielectric layer and a gate electrode layer on the surface of the metal oxide layer;
and patterning the active layer, the gate dielectric layer and the gate electrode layer by adopting an alignment process, and reserving the active layer, the gate dielectric layer and the gate electrode layer which are positioned on one side of the source electrode layer, the insulating dielectric layer and the drain electrode layer and are vertical to the substrate to form the control layer.
In some embodiments, forming the passivation layer further comprises:
opening a hole in the passivation layer, the opening comprising: a first opening extending to a second portion of the surface of the source layer, a second opening extending to the surface of the drain layer, and a third opening extending to the surface of the gate layer;
and filling conductive metal in the first opening hole, the second opening hole and the third opening hole to form a metal interconnection layer, wherein the metal interconnection layer is used for connecting the thin film transistor to the metal connecting line.
In some embodiments, the metal wire includes a scan line for connecting to the scan module and a data line for connecting to the data module, the scan line or the data line has a double-line structure, and the metal wire further includes a wire connection layer for connecting the thin film transistor to the scan line or the data line, and the wire connection layer is a bent wire.
According to a second aspect, an embodiment provides a structure of a flexible thin film transistor array, including:
a substrate;
the thin film transistor array layer is positioned on the substrate, wherein a channel region in the thin film transistor is vertical to the substrate;
and the metal connecting wire is used for connecting each thin film transistor to the scanning module or the data module, and the metal connecting wire is a connecting wire with a bent path.
In some embodiments, the thin film transistor includes:
a source layer and a drain layer on the substrate, wherein the source layer has a first partial surface and a second partial surface, the drain layer is located on the first partial surface, and an insulating medium layer is arranged between the source layer and the drain layer;
the control layer is positioned on the same side of the source electrode layer, the insulating dielectric layer and the drain electrode layer, the control layer comprises a gate electrode layer and an active layer, a channel region is arranged in the active layer, the length direction of the channel region is vertical to the substrate, and the source electrode layer and the drain electrode layer are respectively arranged at two ends of the channel region;
a passivation layer covering the source layer, the drain layer and the control layer;
and a first opening extending from the surface of the passivation layer to the surface of the second portion, a second opening extending to the surface of the drain layer, and a third opening extending to the surface of the gate layer;
and the metal interconnection layer is positioned in the first opening hole, the second opening hole and the third opening hole and is used for connecting the thin film transistor to the metal connecting wire.
In some embodiments, the material of the active layer is a non-metal oxide, amorphous silicon, graphene, molybdenum dioxide, or carbon nanotubes.
In some embodiments, the metal wire includes a scan line for connecting to the scan module and a data line for connecting to the data module, the scan line or the data line has a double-line structure, and the metal wire further includes a wire connection layer for connecting the thin film transistor to the scan line or the data line, the wire connection layer is a bent wire.
According to the structure of the flexible thin film transistor array and the manufacturing method thereof in the embodiment, the structure comprises a substrate and the thin film transistor array formed on the substrate, wherein an active layer in the thin film transistor is vertical to the substrate, and the structure further comprises a metal connecting wire, wherein the metal connecting wire is used for connecting each thin film transistor to a scanning module or a data module, and is a connecting wire with a bending path. Because the channel region in the thin film transistor device is vertical to the substrate, the bending stress on the thin film transistor device is small, the influence on the performance of the transistor during bending can be reduced, in addition, the metal connecting wire used for connecting each thin film transistor to the scanning module or the data module in the flexible thin film transistor array is a connecting wire with a bending path, because the metal connecting wire is used for connecting a plurality of thin film transistors in the flexible thin film transistor array device and connecting the transistors to a circuit, when the metal connecting wire for connecting all the thin film transistors is not linear, certain buffer capacity can be realized when the metal connecting wire is subjected to tensile and bending stress, and the performance and the stability of the whole device are improved.
Drawings
Fig. 1 and 2 are schematic structural views of a thin film transistor in the prior art;
FIG. 3A is a schematic diagram of a flexible TFT array and a metal interconnection structure in the prior art;
FIG. 3B is a top view of scan lines and data lines in the prior art;
FIG. 4 is a schematic diagram of a flexible TFT array and a metal interconnection structure according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a TFT structure provided in an embodiment of the invention;
FIG. 6 is a schematic diagram of a TFT structure provided in an embodiment of the invention;
FIG. 7 is a schematic diagram of a TFT structure provided in an embodiment of the invention;
FIG. 8 is a schematic diagram of a TFT structure provided in an embodiment of the invention;
FIG. 9 is a schematic view of a metal interconnect structure according to an embodiment of the present invention;
FIG. 10 is a schematic view of a metal interconnect structure according to an embodiment of the present invention;
FIG. 11 is a top view of scan lines and data lines in a metal line according to an embodiment of the present invention;
FIG. 12 is a schematic view of a flexible TFT array and a metal line structure according to an embodiment of the present invention;
fig. 13 is a schematic flow chart illustrating a manufacturing process of a flexible thin film transistor array according to an embodiment of the present invention;
fig. 14A is a schematic view of a part of a structure of a flexible thin film transistor array in a manufacturing process according to an embodiment of the present invention;
FIG. 14B is a top view of the structure of FIG. 14A;
fig. 15A is a schematic structural diagram of a portion of a flexible thin film transistor array in a manufacturing process according to an embodiment of the invention;
FIG. 15B is a top view of the structure of FIG. 15A;
fig. 16A is a schematic structural diagram of a portion of a flexible thin film transistor array in a manufacturing process according to an embodiment of the invention;
FIG. 16B is a top view of the structure of FIG. 16A;
fig. 17A is a schematic structural diagram of a part of a flexible thin film transistor array in a manufacturing process according to an embodiment of the present invention;
fig. 17B is a top view of the structure of fig. 17A.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
As can be seen from the background art, the performance stability of the flexible thin film transistor in the prior art is low.
Through analysis, referring to fig. 1 and 2, in the flexible thin film transistor array in the prior art, the active layer 20 in the transistor in either the bottom gate structure or the top gate structure is parallel to the entire substrate 10, and when the substrate is bent, the stress applied to the active layer 20 is large, and therefore, the influence applied to the transistor is large. In addition, referring to fig. a and B, the wiring 30 of the flexible electronic device in the prior art is designed in a straight line, and when the device is stretched or bent, the stability of the device will be seriously affected because the straight line connection does not have a certain bearing capacity.
In an embodiment of the present invention, a flexible thin film transistor array is provided, which includes a substrate and a thin film transistor array formed on the substrate, wherein an active layer of the thin film transistor is perpendicular to the substrate, and a metal wire for connecting each thin film transistor to a scan module or a data module, wherein the metal wire is a wire having a bent path. When the device is bent, the channel region in the thin film transistor device is perpendicular to the substrate, so that the bending stress is small, and the problem that the bending causes the performance reduction of the device is solved. Further, the connection lines connected to each thin film transistor in the flexible thin film transistor array provided by this embodiment are designed to be non-linear structures, that is, the metal connection lines used for connecting each thin film transistor to the scan module or the data module are connection lines with bent paths, which can further reduce the influence of tensile or bending stress on the whole flexible thin film transistor array device.
Referring to fig. 1, the present embodiment provides a flexible thin film transistor array, which includes: the thin film transistor array substrate comprises a substrate 100, a thin film transistor array layer located on the substrate 100 and a metal connecting line 600.
The substrate 100 has a front surface and a back surface opposite to the front surface, the substrate 100 may be a flexible material such as PI, PET, etc., a plurality of thin film transistors are disposed in a thin film transistor array layer, and active layers of the thin film transistors are perpendicular to the substrate 100.
The thin film transistor includes a source layer 301, a drain layer 302, a control layer, and a passivation layer 500 on the substrate 100.
The source layer 301 and the drain layer 302 are made of a metal material, and may be a conductive metal such as copper or aluminum.
The control layer includes a gate layer 200 and an active layer 210, the active layer 210 has a channel region 211 therein, a length direction of the channel region 211 is perpendicular to the substrate 100, and the source layer 301 and the drain layer 302 are respectively disposed at two ends of the channel region 211. Since the channel region 211 is perpendicular to the substrate along the channel length, the channel region 211 has an upper end surface, a lower end surface, and a left side surface and a right side surface, the source layer 301 and the drain layer 302 may be located on the same side of the channel region 211, for example, referring to fig. 5, the source layer 301 and the drain layer 302 are located on the left side of the channel region 211.
In some embodiments, referring to fig. 8, the active layer 210 is disposed around the gate layer 200, the source layer 301 and the drain layer 302 are respectively disposed at upper and lower ends of the active layer 210, and when viewed from above, the source layer 301 and the drain layer 302 may be shaped as a circular ring surrounding the active layer 210, and an insulating dielectric layer 401 is disposed between the source layer 301 and the drain layer 302.
The gate layer 200 may control the channel region 211 to be turned on and off, and since the channel region 211 is perpendicular to the substrate 100, when the substrate 100 is bent, the stress applied to the channel region 211 may be reduced, so that the stability of the entire device may be improved.
The gate layer 200 is made of a metal material, and may be made of a conductive metal such as copper or aluminum, and the active layer 210 may be made of a non-metal oxide, amorphous silicon, graphene, molybdenum dioxide, or a carbon nanotube.
It should be noted that, during the manufacturing process, when the active layer 210 is deposited and formed, a part of the active layer 210 is a non-channel region 212 in addition to a channel region 211, so that the channel region 211 is required to be partially perpendicular to the substrate, and the non-channel region 212 may not be perpendicular to the substrate.
A gate dielectric layer having an insulating function is disposed between the gate layer 200 and the active layer 210.
In some embodiments, the source layer 301 and the drain layer 302 may both be located above the active layer 210 or both be located below the active layer 210. For example, as shown in fig. 6, the source layer 301 and the drain layer 302 are both located above the active layer 210.
In some embodiments, the source layer 301 and the drain layer 302 may be respectively located above and below the active layer 210, for example, as shown in fig. 7, the source layer 301 is located above the active layer 210, and the drain layer 302 is located below the active layer 210.
In one embodiment, referring to fig. 5, a source layer 301 is disposed on a portion of the surface of the substrate 100, the source layer 301 has a first portion surface and a second portion surface, wherein the insulating dielectric layer 401 is disposed on the first portion surface, the source layer 301 is a conductive metal, such as copper or aluminum, and the insulating dielectric layer 401 is an insulating material, such as silicon oxide. The drain layer 302 is located on the insulating medium layer 401, and the drain layer 302 is a metal conductor and may be made of copper or aluminum. The insulating dielectric layer 401 is located between the source layer 301 and the drain layer 302, and plays roles of isolation and insulation. The control layer is located on one side of the source layer 301, the insulating dielectric layer 401 and the drain layer 302, and is perpendicular to the substrate 100.
In this embodiment, the control layer includes: the semiconductor device comprises an active layer 210, a gate dielectric layer 402 and a gate layer 200, wherein the gate dielectric layer 402 is positioned between the active layer 210 and the gate layer 200. The active layer 210, the gate dielectric layer 402 and the gate layer 200 are parallel to each other and perpendicular to the substrate 100, the source layer 301 on the substrate 100, the insulating dielectric layer 401 and the drain layer 302. The control layer is perpendicular to the plane and the substrate bending plane, so that the problem that the active layer 210 in the control layer is stressed when being bent is solved, and the performance and the stability of the device are improved.
The passivation layer 500 serves to protect the device. In this embodiment, the passivation layer 500 covers the remaining surface of the substrate 100, the second surface of the source layer 301, the drain layer 302, and the side surfaces and surfaces of the control layer. The material of the passivation layer 500 may be silicon oxide.
In this embodiment, the metal interconnection layer 510 is further included to contact the gate layer 200, the source layer 301, and the drain layer 302, respectively.
Specifically, the metal interconnect layer 510 includes a first opening extending from the surface of the passivation layer 500 to the surface of the second portion, a second opening extending to the surface of the drain layer 302, and a third opening extending to the surface of the gate layer 200, and is located in the first opening, the second opening, and the third opening.
The thin film transistor array substrate further comprises a metal connecting wire 600, wherein the metal connecting wire 600 is used for connecting each thin film transistor and connecting each thin film transistor into the scanning module or the data module to complete wiring, and the metal connecting wire 600 is a connecting wire with a bent path.
In this embodiment, referring to fig. 9 to 12, the metal connecting wire 600 is a connecting wire having a bent path.
The metal connecting line 600 includes a scanning line for connecting a scanning module and a data line for connecting a data module, the scanning line or the data line may be designed as a double-line structure (the line in the prior art may refer to fig. 3B, compare fig. 3, the line structure in this embodiment may refer to fig. 11), the scanning line or the data line in this embodiment is a double-line structure, which may ensure stability during bending on the one hand, and even if one line is broken during bending stress, the other line may also function, providing double guarantee for stability of the wiring line; on the other hand, in the embodiment, the double lines can be made into a rectangular or rhombic structure during design, so that the stress bearing capacity during bending is improved.
The thin film transistor device further comprises a wiring connection layer for connecting the thin film transistor to the scanning line or the data line, wherein the wiring connection layer can also be a bent connecting line, a bending path can be wavy (as shown in fig. 9) or a metal connecting part is hollowed out, and then an insulating medium is filled in the hollowed-out position (as shown in fig. 10) to enable the metal connecting line 600 to have a wrinkle, so that the metal connecting line 600 has certain buffering capacity (as shown in fig. 11) when the device is bent or stretched. Since the plurality of thin film transistors are connected by the metal connecting lines 600 in the flexible thin film transistor array device, when the metal connecting lines 600 connecting the thin film transistors are nonlinear, that is, when the metal connecting lines 600 are bent or folded, the tensile and bending stress of the wiring can be improved, and when the flexible thin film transistor array is integrally bent or stretched, the performance and stability of the whole device are improved.
The structure in the above embodiments may be used in a thin film transistor device such as a top gate structure, a bottom gate structure, or a double gate structure.
Fig. 13 is a flowchart of a method for manufacturing the flexible thin film transistor array according to the present embodiment.
Referring to fig. 1, the present embodiment further provides a method for manufacturing a flexible thin film transistor array, including providing a substrate 100, forming a thin film transistor array on the substrate 100, wherein an active layer 210 of a thin film transistor is perpendicular to the substrate 100, and then forming a metal wire 600, where the metal wire 600 is used to connect the thin film transistor and connect each thin film transistor to a scan module or a data module, and the formed metal wire 600 is a wire having a bent path.
Referring to fig. 14A and 14B, in the present embodiment, the manufacturing method includes:
step 1, a substrate 100 is provided, and a source layer 301 is formed on a portion of a surface of the substrate 100.
The substrate 100 in this embodiment may be a flexible material such as PI or PET.
The source layer 301 may be formed by: first, a layer of source layer 301 metal is deposited on the surface of the substrate 100, and then, a patterning process is performed on the layer of source layer 301 metal, which may be a step of forming a patterned source layer 301 mask layer on the layer of source layer 301 metal, and the source layer 301 metal is etched by using the source layer 301 mask layer as a mask, so as to obtain the source layer 301. A part of the surface of the source layer 301 is a first part of the surface, and the rest of the surface is a second part of the surface.
In step 2, referring to fig. 15A and fig. 15B, an insulating dielectric layer 401 and a drain layer 302 are sequentially deposited on the first surface portion of the source layer 301.
In some embodiments, the step of sequentially depositing the insulating dielectric layer 401 and the drain layer 302 on the first surface portion of the source layer 301 comprises: firstly, an insulating medium layer 401 covering the source layer 301 is deposited on the surface of the source layer 301, then a drain layer 302 is formed on the insulating medium layer 401, and finally, the drain layer 302 and the insulating medium layer 401 are patterned in sequence, and the drain layer 302 and the insulating medium layer 401 on the first part of the surface are reserved.
In some embodiments, the step of sequentially depositing the insulating dielectric layer 401 and the drain layer 302 on the first surface portion of the source layer 301 comprises: firstly, an insulating dielectric layer 401 covering the source layer 301 is deposited on the surface of the source layer 301, then the insulating dielectric layer 401 is subjected to patterning treatment, only the insulating dielectric layer 401 on the first part of the surface is reserved, and then a drain layer 302 is deposited on the insulating dielectric layer 401.
In this embodiment, the source layer 301 and the drain layer 302 are made of a conductive metal, such as copper or aluminum, and the insulating dielectric layer 401 is made of an insulating material, such as silicon oxide or silicon nitride.
Step 3, please refer to fig. 16A and fig. 16B in combination, a control layer is formed, and the control layer is located on one side of the source layer 301, the insulating dielectric layer 401 and the drain layer 302 and is perpendicular to the substrate 100.
The control layer includes: the semiconductor device comprises an active layer 210, a gate dielectric layer 402 and a gate layer 200, wherein the gate dielectric layer 402 is positioned between the active layer 210 and the gate layer 200.
The step of generating the control layer may include: depositing a layer of active layer 210 material on the surface of the drain layer 302 and the rest surface of the substrate 100, wherein the active layer 210 material may be a non-metal oxide, amorphous silicon, graphene, molybdenum dioxide, or a carbon nanotube; then, depositing a gate dielectric layer 402 on the active layer 210, wherein the gate dielectric layer 402 may be made of an insulating material such as silicon oxide or silicon nitride; finally, depositing a gate layer 200 on the gate dielectric layer 402, where the material of the gate layer 200 may be a conductive metal material, such as copper or aluminum, or an alloy metal; then, an alignment process is used to pattern the active layer 210, the gate dielectric layer 402 and the gate layer 200, so that three layers of materials on one side of the source layer 301, the insulating dielectric layer 401 and the drain layer 302 remain, thereby forming a control layer portion perpendicular to the substrate 100.
It should be noted that, during the manufacturing process, when the active layer 210 is deposited and formed, a portion of the active layer 210 is a non-channel region in addition to a portion of the channel region 211, and the non-channel region may not be strictly perpendicular to the substrate.
It should be noted that, in this embodiment, an alignment process is adopted to remove the control layer on the surface of the drain layer 302, and the control layer on the surface of the substrate 100 is not removed, so that the gate layer 200 has a surface parallel to the substrate 100, which is convenient for forming an opening on the surface of the gate layer 200, thereby forming a metal contact of the gate layer 200, so as to facilitate an external circuit.
In step 4, please refer to fig. 17A and 17B in combination, a passivation layer 500 is formed, and a metal interconnection layer 510 is formed in the passivation layer 500.
The passivation layer 500 covers the remaining surface of the substrate 100, the second surface of the source layer 301, the surface of the drain layer 302, and the side surfaces and surfaces of the control layer, and the passivation layer 500 can protect the internal circuits of the device.
In this embodiment, an opening is formed on the passivation layer 500, and the opening includes: a first opening extending to a second partial surface of the source layer 301, a second opening extending to a surface of the drain layer 302, and a third opening extending to a surface of the gate layer 200, and then depositing conductive metal in the first opening, the second opening, and the third opening, respectively, to form metal interconnection layers 510 respectively contacting the source layer 301, the drain layer 302, and the gate layer 200, so as to connect to an external circuit.
Referring to fig. 9 to 12 in conjunction with the drawings, in the present embodiment, when forming the wiring, a metal wiring 600 for connecting each thin film transistor to the scan module or the data module is provided as a wiring having a bent path.
The metal line 600 includes a scan line for connecting to a scan module and a data line for connecting to a data module, and the scan line or the data line may be designed as a dual-line structure (the line in the prior art may refer to fig. 3B, and compared with fig. 3, the line structure in this embodiment may refer to fig. 11 and 12).
In this embodiment, the method for forming the lines with such a structure may be to deposit a metal interconnection layer on the surface of the substrate on which the transistor array has been formed, perform patterning on the metal interconnection layer, and form the lines with a double-line structure (fig. 11) after etching. In the embodiment, the scanning line or the data line is of a double-line structure, so that on one hand, the stability during bending can be ensured, and even if one line is broken in the bending stress process, the other line can also play a role, thereby providing double guarantee for the stability of the wiring line; on the other hand, in the embodiment, the double lines can be made into a rectangular or rhombic structure during design, so that the stress bearing capacity during bending is improved.
The metal line 600 further includes a wiring connection layer for connecting the tft to a scan line or a data line, and the wiring connection layer may also be a curved line, wherein the bending path may be a wave (as shown in fig. 9), and the structure is formed by: firstly, depositing a first metal connecting line layer on the surface of a substrate on which a transistor array is formed, then etching to make the first metal connecting line layer be in an intermittent strip shape, finally forming a second metal connecting line layer above the first metal connecting line layer, etching the second metal connecting line layer, wherein the etching position is complementary with the etched position of the first connecting line layer, so that the formed metal connecting line 600 for connecting the thin film transistor is a wavy connecting line.
The connection line of the bent path may also be a connection line formed by the metal connection portion and the insulating medium, and three kinds of metal connection lines with bent paths are respectively shown in the upper part, the middle part and the lower part in fig. 10. For example, in the metal interconnection 600 shown above fig. 10, a metal interconnection layer is deposited, a plurality of grooves are etched on the metal interconnection layer, such that the cross-section of the metal interconnection layer looks like a plurality of waves, and then the grooves are filled with an insulating medium, such that the metal interconnection 600 has a plurality of meandering paths.
For example, the metal line 600 in the middle of fig. 10 may be formed by first forming an insulating dielectric layer, then etching the insulating dielectric layer to form a plurality of discontinuous insulating dielectric protrusions, and then covering the plurality of discontinuous insulating dielectric protrusions with a metal conductor material.
The method for forming the metal line 600 in the lower portion of fig. 10 is a combination of the above two methods, and is not described herein again.
In this embodiment, the wiring connection layer for connecting the thin film transistor to the scan line or the data line is formed in a corrugated shape, so that the wiring connection layer has a certain buffer capacity when the device is bent or stretched. The device can be improved in the stretching and bending stress, and the performance and stability of the device are guaranteed when the flexible thin film transistor array is integrally bent or stretched.
The metal connecting wire 600 may be made of a conductor material such as aluminum, copper, ITO, graphite, or a composite material, or a material such as a superconductor.
In the flexible thin film transistor array structure and the method provided by the embodiment, the channel region 211 for controlling the on and off of the device is set to be perpendicular to the substrate 100 direction, so that the stability of each thin film transistor during bending is improved, and the metal connecting wire 600 for connecting each thin film transistor array structure is also set to be a connecting wire with a bending path, so that the flexible thin film transistor array structure is not easy to break and strong in tolerance capability, the problem of stress when the whole flexible thin film transistor array is bent or stretched can be further improved, and the stability of the whole flexible thin film transistor array is improved.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims (10)

1. A method of fabricating a flexible thin film transistor array, comprising:
providing a substrate;
forming a thin film transistor array on the substrate, wherein a channel region in the thin film transistor is vertical to the substrate;
and forming a metal connecting wire, wherein the metal connecting wire is used for connecting each thin film transistor to the scanning module or the data module, and the metal connecting wire is a connecting wire with a bent path.
2. The method of manufacturing of claim 1, wherein forming a thin film transistor array on the substrate comprises:
forming a source layer on the substrate, wherein the source layer is located on a part of the surface of the substrate, the part of the surface of the source layer is a first part of the surface, and the rest part of the surface of the source layer is a second part of the surface;
sequentially depositing an insulating medium layer and a drain layer on the first part surface of the source layer;
forming a control layer, the control layer comprising: the gate dielectric layer is positioned between the active layer and the gate electrode layer, and the active layer is vertical to the substrate;
and forming a passivation layer which covers the rest part of the surface of the substrate, the second part of the surface of the source layer, the surface of the drain layer and the side surfaces and the surfaces of the control layer.
3. The method of claim 2, wherein the control layer is on a same side of the source, dielectric, and drain layers and is perpendicular to the substrate.
4. The manufacturing method according to claim 3, wherein forming the control layer comprises:
depositing an active layer, wherein the active layer covers part of the surface of the substrate, the side surfaces of the source electrode layer and the insulating medium layer, and the side surfaces and the surface of the drain electrode layer;
sequentially depositing a gate dielectric layer and a gate electrode layer on the surface of the metal oxide layer;
and patterning the active layer, the gate dielectric layer and the gate electrode layer by adopting an alignment process, and reserving the active layer, the gate dielectric layer and the gate electrode layer which are positioned on one side of the source electrode layer, the insulating dielectric layer and the drain electrode layer and are vertical to the substrate to form the control layer.
5. The method of manufacturing of claim 2, wherein forming the passivation layer further comprises:
opening a hole in the passivation layer, the opening comprising: a first opening extending to a second portion of the surface of the source layer, a second opening extending to the surface of the drain layer, and a third opening extending to the surface of the gate layer;
and filling conductive metal in the first opening hole, the second opening hole and the third opening hole to form a metal interconnection layer, wherein the metal interconnection layer is used for connecting the thin film transistor to the metal connecting line.
6. The method of claim 1, wherein the metal wires include scan lines for connecting scan modules and data lines for connecting data modules, the scan lines or the data lines have a double-line structure, and further comprising a wire connection layer for connecting the thin film transistors to the scan lines or the data lines, the wire connection layer being a bent wire.
7. A structure of a flexible thin film transistor array, comprising:
a substrate;
the thin film transistor array layer is positioned on the substrate, wherein a channel region in the thin film transistor is vertical to the substrate;
and the metal connecting wire is used for connecting each thin film transistor to the scanning module or the data module, and the metal connecting wire is a connecting wire with a bent path.
8. The structure of claim 7, wherein the thin film transistor comprises:
a source layer and a drain layer on the substrate, wherein the source layer has a first partial surface and a second partial surface, the drain layer is located on the first partial surface, and an insulating medium layer is arranged between the source layer and the drain layer;
the control layer is positioned on the same side of the source electrode layer, the insulating dielectric layer and the drain electrode layer, the control layer comprises a gate electrode layer and an active layer, a channel region is arranged in the active layer, the length direction of the channel region is vertical to the substrate, and the source electrode layer and the drain electrode layer are respectively arranged at two ends of the channel region;
a passivation layer covering the source layer, the drain layer and the control layer;
and a first opening extending from the surface of the passivation layer to the surface of the second portion, a second opening extending to the surface of the drain layer, and a third opening extending to the surface of the gate layer;
and the metal interconnection layer is positioned in the first opening hole, the second opening hole and the third opening hole and is used for connecting the thin film transistor to the metal connecting wire.
9. The structure of claim 8, wherein the material of the active layer is a non-metal oxide, amorphous silicon, graphene, molybdenum dioxide, or carbon nanotubes.
10. The structure of claim 7, wherein the metal wire includes a scan line for connecting to a scan module and a data line for connecting to a data module, the scan line or the data line having a two-line structure, and further comprising a wire connection layer for connecting the thin film transistor to the scan line or the data line, the wire connection layer being a bent wire.
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CN107219696A (en) * 2017-06-20 2017-09-29 武汉华星光电技术有限公司 A kind of array base palte, liquid crystal panel and liquid crystal display
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