CN112687703B - Display panel - Google Patents
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- CN112687703B CN112687703B CN202011544119.7A CN202011544119A CN112687703B CN 112687703 B CN112687703 B CN 112687703B CN 202011544119 A CN202011544119 A CN 202011544119A CN 112687703 B CN112687703 B CN 112687703B
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Abstract
The application provides a display panel, display panel includes: a substrate; a first metal oxide transistor disposed on the substrate, the first metal oxide transistor including a first metal oxide active layer; the capacitor is arranged on the substrate and comprises a first electrode plate, and the first electrode plate and the first metal oxide active layer are arranged on the same layer; and the first transparent conductive piece is arranged on the same layer as the first metal oxide active layer and is connected with the first metal oxide active layer and the first electrode plate. The first electrode plate and the first metal oxide active layer are arranged on the same layer, and the first transparent conductive piece arranged on the same layer as the first metal oxide active layer is connected with the first electrode plate and the first metal oxide active layer, so that the number of through holes and metal wiring for overlapping are reduced, and the aperture opening ratio of the display panel is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
An Organic light-emitting diode (OLED) display has the characteristics of self-luminescence, high contrast ratio and fast reaction speed, and has a very good development prospect.
At present, how to improve the aperture ratio of an organic light emitting diode display is a technical problem to be solved.
Disclosure of Invention
An object of the present application is to provide a display panel, so as to reduce the number of via holes and metal wiring for overlapping, and to facilitate improving the aperture ratio of the display panel.
To achieve the above object, the present application provides a display panel including:
a substrate;
a first metal oxide transistor disposed on the substrate, the first metal oxide transistor including a first metal oxide active layer;
a capacitor disposed on the substrate, the capacitor including a first electrode plate disposed in the same layer as the first metal oxide active layer; and
and the first transparent conductive piece is arranged on the same layer as the first metal oxide active layer and is connected with the first metal oxide active layer and the first electrode plate.
Has the advantages that: the first electrode plate and the first metal oxide active layer are arranged on the same layer, and the first transparent conductive piece arranged on the same layer as the first metal oxide active layer is connected with the first electrode plate and the first metal oxide active layer, so that the number of the through holes and the metal wiring for lap joint are reduced, and the improvement of the resolution of the display panel is facilitated.
Drawings
FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a pixel driving circuit of a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic plan view of a second patterned active layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The application provides a display panel, which is an organic light emitting diode display panel. As shown in fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure, and fig. 2 is a schematic view of a pixel driving circuit of the display panel according to the embodiment of the present disclosure. The display panel 100 has a display area 100a and a pad area 100b. The display area 100a of the display panel 100 is provided with a plurality of pixel driving circuits arranged in an array. The pad region 100b of the display panel 100 is provided with a plurality of pads.
As shown in fig. 2, each pixel driving circuit includes a first polysilicon transistor M1, a second polysilicon transistor M2, a first metal oxide transistor M3, a second metal oxide transistor M4, a third polysilicon transistor M5, a fourth polysilicon transistor M6, a fifth polysilicon transistor M7, a light emitting device OLED, and a capacitor C. The first polysilicon transistor M1 is a driving transistor, the second polysilicon transistor M2 is a second switching control transistor, the first metal oxide transistor M3 is a compensation transistor, the second metal oxide transistor M4 is an initialization transistor M4, the third polysilicon transistor M5 is a first lighting control transistor, the fourth polysilicon transistor M6 is a switching transistor, and the fifth polysilicon transistor M7 is a reset transistor.
The first polysilicon transistor M1, the second polysilicon transistor M2, the third polysilicon transistor M5, the fourth polysilicon transistor M6, and the fifth polysilicon transistor M7 are all low-temperature polysilicon transistors, and the first metal oxide transistor M3 and the second metal oxide transistor M4 are all metal oxide transistors. The first polysilicon transistor M1, the second polysilicon transistor M2, the first metal oxide transistor M3, the second metal oxide transistor M4, the third polysilicon transistor M5, the fourth polysilicon transistor M6 and the fifth polysilicon transistor M7 are all P-type transistors.
The light emitting device OLED is an organic light emitting diode. The organic light emitting diode includes a cathode, an anode, and an organic light emitting layer between the cathode and the anode.
The gate of the first polysilicon transistor M1 is connected to the first electrode plate C1 of the capacitor C, the source of the second metal oxide transistor M4, and the drain of the first metal oxide transistor M3, the source of the first polysilicon transistor M1 is connected to the data line D (M) through the fourth polysilicon transistor M6, the source of the first polysilicon transistor M1 is further connected to the first dc power signal line VDD through the third polysilicon transistor M5, the drain of the first polysilicon transistor M1 is connected to the light emitting device OLED through the second polysilicon transistor M2, and the drain of the first polysilicon transistor M1 is connected to the source of the first metal oxide transistor M3. The first polysilicon transistor M1 is used to supply a driving current to the light emitting device OLED.
The fourth polysilicon transistor M6 is a switching transistor. The gate of the fourth polysilicon transistor M6 is connected to the nth SCAN signal line SCAN (n), the source of the fourth polysilicon transistor M6 is connected to the data line D (M), and the drain of the fourth polysilicon transistor M6 is connected to the source of the first polysilicon transistor M1 and the drain of the third polysilicon transistor M5. The fourth polysilicon transistor M6 is turned on or off according to a SCAN signal input from the nth SCAN signal line SCAN (n), and controls whether to output a data signal transmitted from the data line D (M) to the source of the first polysilicon transistor M1.
The gate of the first metal oxide transistor M3 is connected to the nth SCAN signal line SCAN (n), the source of the first metal oxide transistor M3 is connected to the drain of the first polysilicon transistor M1 and the source of the second polysilicon transistor M2, and the drain of the first metal oxide transistor M3 is connected to the gate of the first polysilicon transistor M1, the source of the second metal oxide transistor M4, and the first electrode plate C1. The first metal oxide transistor M3 is turned on or off according to a SCAN signal inputted from the nth SCAN signal line SCAN (n), and controls whether the gate of the first polysilicon transistor M1 is electrically connected to the drain of the first polysilicon transistor M1.
The gate of the second metal oxide transistor M4 is connected to the n-1 th SCAN signal line SCAN (n-1), the source of the second metal oxide transistor M4 is connected to the first electrode plate C1, the gate of the first polysilicon transistor M1, and the drain of the first metal oxide transistor M3, and the drain of the second metal oxide transistor M4 is connected to the initialization signal line VI and the drain of the fifth polysilicon transistor M7. The second metal oxide transistor M4 is turned on or off according to the n-1 th SCAN signal inputted from the n-1 th SCAN signal line SCAN (n-1), and controls whether the initialization signal inputted from the initialization signal line VI is transmitted to the gate of the first polysilicon transistor M1.
The gate of the third polysilicon transistor M5 is connected to the emission control signal line EM (n), the source of the third polysilicon transistor M5 is connected to the second electrode plate C2 and the first dc power supply signal line VDD, and the drain of the third polysilicon transistor M5 is connected to the drain of the fourth polysilicon transistor M6 and the source of the first polysilicon transistor M1. The third polysilicon transistor M5 controls whether the dc power signal transmitted by the first dc power signal line VDD is transmitted to the source of the first polysilicon transistor M1 according to whether the light emission control signal transmitted by the light emission control signal line EM (n) is in an on or off state.
The gate of the second polysilicon transistor M2 is connected to the emission control signal line EM (n), the source of the second polysilicon transistor M2 is connected to the drain of the first polysilicon transistor M1 and the source of the first metal oxide transistor M3, and the drain of the second polysilicon transistor M2 is connected to the anode of the light emitting device OLED and the source of the fifth polysilicon transistor M7. The second polysilicon transistor M2 is turned on or off according to the light emission control signal transmitted from the light emission control signal line EM (n), and controls whether or not the driving current is output to the light emitting device OLED.
The gate of the fifth polysilicon transistor M7 is electrically connected to the nth stage SCAN signal line SCAN (n), the source of the fifth polysilicon transistor M7 is connected to the drain of the second polysilicon transistor M2 and the anode of the light emitting device OLED, and the drain of the fifth polysilicon transistor M7 is connected to the drain of the second metal oxide transistor M4 and the initialization signal line VI. The fifth polysilicon transistor M7 is turned on or off according to the nth-stage SCAN signal transmitted from the nth-stage SCAN signal line SCAN (n), and controls whether or not to output the initialization signal transmitted from the initialization signal line to the anode of the light emitting device.
A first electrode plate C1 of the capacitor C is connected to the gate of the first polysilicon transistor M1, the drain of the first metal oxide transistor M3, and the source of the second metal oxide transistor M4, and a second electrode plate C2 of the capacitor C is connected to the first dc power signal line VDD and the source of the third polysilicon transistor M5.
As shown in fig. 1, the display panel includes a substrate 101, a buffer layer 102, an inorganic stack layer 103, a first patterned active layer, a fourth insulating layer 107, a first patterned metal layer, a third insulating layer 106, a second patterned metal layer, a first insulating layer 104, a second patterned active layer, a second insulating layer 105, a third patterned metal layer, a fifth insulating layer 108, a fourth patterned metal layer, a sixth insulating layer 109, an anode 110, a pixel defining layer, and an organic light emitting layer 111, which are sequentially stacked.
The substrate 101 includes a first polyimide layer, a first barrier layer, and a second polyimide layer, which are sequentially stacked. The first barrier layer is made of at least one material selected from silicon nitride and silicon oxide.
The buffer layer 102 is disposed on the substrate 101. The buffer layer 102 is made of silicon oxide. The buffer layer 102 functions to protect the substrate 101.
The inorganic stack 103 includes a silicon nitride layer, a silicon oxide layer, and an amorphous silicon layer sequentially disposed on the buffer layer 102. The silicon nitride layer functions to block impurities in the substrate 101. The silicon oxide layer plays a role in heat preservation. The amorphous silicon layer is subsequently treated by a dehydrogenation process, so that hydrogen explosion in the excimer laser annealing process caused by overhigh hydrogen content in the amorphous silicon is prevented.
A first patterned active layer is disposed on the inorganic stack 103. In the display region 100a, the first patterned active layer includes a first polysilicon active layer 1121 and a second polysilicon active layer 1122 which are disposed at the same layer and interval. The first polysilicon active layer 1121 includes a first polysilicon channel 1121a, a first source 1121b, and a first drain 1121c, and the first source 1121b and the first drain 1121c are located at two opposite sides of the first polysilicon channel 1121 a. The second polysilicon active layer 1122 includes a second polysilicon channel 1122a, a second source 1122b and a second drain 1122c, and the second source 1122b and the second drain 1122c are located at opposite sides of the second polysilicon channel 1122 a. The first patterned active layer is a patterned low temperature polysilicon layer. The first source 1121b, the first drain 1121c, the second source 1122b, and the second drain 1122c are all obtained by ion doping a low temperature polysilicon layer.
The fourth insulating layer 107 covers the first patterned active layer and the inorganic stack 103. The fourth insulating layer 107 is a first gate insulating layer. The material for forming the fourth insulating layer 107 is at least one of silicon nitride and silicon oxide. The fourth insulating layer 107 is disposed between the first polysilicon active layer 1121 and the third gate 1131.
The first patterned metal layer is disposed on the fourth insulating layer 107. In the display area 100a, the first patterned metal layer includes a third gate 1131 and a fourth gate 1132 disposed in the same layer. The third gate 1131 is disposed above the first polysilicon active layer 1121, and the third gate 1131 is disposed corresponding to the first polysilicon channel 1121 a. The fourth gate electrode 1132 is disposed above the second polysilicon active layer 1122 and the fourth gate electrode 1132 is disposed corresponding to the second polysilicon channel 1122 a. The third gate electrode 1131 and the first polysilicon active layer 1121 constitute a portion of a first polysilicon transistor M1, and the fourth gate electrode 1132 and the second polysilicon active layer 1122 constitute a portion of a second polysilicon transistor M6. The first patterned metal layer is made of at least one material selected from molybdenum, aluminum, titanium, and copper. The first patterned metal layer has a thickness of 2000 angstroms to 3000 angstroms. Specifically, the material for preparing the first patterned metal layer was molybdenum, and the thickness of the first patterned metal layer was 2500 angstroms.
The third insulating layer 106 covers the fourth insulating layer 107 and the first patterned metal layer. The third insulating layer 106 is a second gate insulating layer. The third insulating layer 106 is made of at least one of silicon nitride or silicon oxide. The third insulating layer 106 has a thickness of 1000 angstroms to 2500 angstroms.
The second patterned metal layer includes a first gate 1141 and a fifth gate 1142 disposed at an interval in the same layer. The second patterned metal layer is disposed on the third insulating layer 106, such that the first gate 1141 and the fifth gate 1142 are disposed on the third insulating layer 106. The second patterned metal layer is made of at least one material selected from molybdenum, aluminum, titanium, and copper. The second patterned metal layer has a thickness of 2000 angstroms to 3000 angstroms. Specifically, the material for preparing the second patterned metal layer was molybdenum, and the thickness of the second patterned metal layer was 2500 angstroms.
The first insulating layer 104 covers the second patterned metal layer and the third insulating layer 106 such that the third insulating layer 106 is disposed between the third gate 1131 and the first insulating layer 104. The first insulating layer 104 is a first interlayer insulating layer. The thickness of the first insulating layer 104 is 4500 a-6000 a. The first insulating layer 104 is made of at least one of silicon nitride and silicon nitride.
The second patterned active layer is disposed on the first insulating layer 104. The second patterned active layer includes a first metal oxide active layer 1151, a second metal oxide active layer 1152, a first transparent conductive piece 1153, a second transparent conductive piece 1154 and a first electrode plate C1, such that the first metal oxide active layer 1151, the second metal oxide active layer 1152, the first transparent conductive piece 1153, the second transparent conductive piece 1154 and the first electrode plate C1 are disposed on the same layer and are all disposed on the first insulating layer 104. The first metal oxide active layer 1151 includes a first metal oxide channel, a third source and a third drain, which are located on opposite sides of the first metal oxide channel. The second metal oxide active layer 1152 includes a second metal oxide channel, a fourth source electrode, and a fourth drain electrode. The preparation material of the second patterned active layer is indium gallium zinc oxide. The third source electrode, the third drain electrode, the fourth source electrode and the fourth drain electrode are obtained by ion doping the indium gallium zinc oxide layer. First transparent conductive piece 1153, second transparent conductive piece 1154 and first electrode plate C1 are obtained by conducting treatment on an indium gallium zinc oxide layer. The method of the conductor formation includes any one of plasma treatment, doping, and implantation.
Fig. 3 is a schematic plan view of the second patterned active layer. The first transparent conductive member 1153 connects the first metal oxide active layer 1151 and the first electrode plate C1, so that the third drain electrode of the first metal oxide active layer 1151 is electrically connected to the first electrode plate C1. The second transparent conductive member 1154 is connected to the second metal oxide active layer 1152 and the first electrode plate C1, so that the fourth source of the second metal oxide active layer 1152 is electrically connected to the first electrode plate C1.
The second insulating layer 105 covers the second patterned active layer and the first insulating layer 104. The second insulating layer 105 is a third gate insulating layer. The material for forming the second insulating layer 105 is selected from at least one of silicon nitride and silicon oxide. The thickness of the second insulating layer 105 is smaller than that of the first insulating layer 104. The second insulating layer 105 has a thickness of 1000 angstroms to 2500 angstroms.
The third patterned metal layer is disposed on the second insulating layer 105, and includes a second gate 1161, a second electrode plate C2, and a sixth gate 1162. The second gate electrode 1161 is disposed above the first metal oxide active layer 1151 and corresponds to the first metal oxide active layer 1151, and the sixth gate electrode 1162 is disposed above the second metal oxide active layer 1152 and corresponds to the second metal oxide active layer 1152. The first gate electrode 1141, the second gate electrode 1161 and the first metal oxide active layer 1151 constitute a portion of the first metal oxide transistor M3. The fifth gate electrode 1142, the sixth gate electrode 1162, and the second metal oxide active layer 1152 constitute a portion of the second metal oxide transistor M4. The second electrode plate C2 is disposed corresponding to the first electrode plate C1 and above the first electrode plate C1. The second electrode plate C2, the first electrode plate C1, and the second insulating layer 105 therebetween constitute a capacitor C. The capacitor C is disposed corresponding to the first polysilicon transistor M1. The first electrode plate C1 is disposed above the first polysilicon transistor M1, and the first insulating layer 104 is disposed between the first polysilicon transistor M1 and the first electrode plate C1. The first metal oxide transistor M3 and the second metal oxide transistor M4 include two gates. The third patterned metal is made of at least one material selected from molybdenum, aluminum, titanium, and copper.
The fifth insulating layer 108 covers the third patterned metal layer and the second insulating layer 105 such that the fifth insulating layer is positioned on the second electrode plate C2. The fifth insulating layer 108 is a second interlayer insulating layer. The fifth insulating layer 108 is made of at least one of silicon nitride and silicon oxide. The thickness of the fifth insulating layer 108 is 4500 angstroms-6000 angstroms.
The fourth patterned metal layer is disposed on the fifth insulating layer 108, and the fourth patterned metal layer includes a bridge wire 1171 and an anode wire 1172, such that the bridge wire 1171 and the anode wire 1172 are both located on the fifth insulating layer 108. One end of the bridge wire 1171 is electrically connected to the first polysilicon active layer 1121 through a first via 100e passing through the fifth insulating layer 108, the second insulating layer 105, the first insulating layer 104, the third insulating layer 106, and the fourth insulating layer 107, and the other end of the bridge wire 1171 is electrically connected to the first metal oxide active layer 1151 through a second via 100f passing through the fifth insulating layer 108 and the second insulating layer 105. The anode lead 1172 is electrically connected to the second polysilicon active layer 1122 through a third via 100g passing through the fifth insulating layer 108, the second insulating layer 105, the first insulating layer 104, the third insulating layer 106, and the fourth insulating layer 107.
A sixth insulating layer 109 covering the fourth pattern a metallization layer and a fifth insulating layer 108. The sixth insulating layer 109 is a planarization layer. The thickness of the sixth insulating layer 109 is 1 micrometer to 2.5 micrometers. The sixth insulating layer 109 is an organic insulating layer, and a material for preparing the organic insulating layer may be polyimide, polyacrylate, or the like.
The anode 110 is disposed on the sixth insulating layer 109. The anode 110 may be a transparent electrode or a reflective electrode. The anode 110 is electrically connected to the anode lead 1172 through a fourth via 100h penetrating the sixth insulating layer. When the anode 110 is a transparent electrode, the anode 110 may be made of indium tin oxide; when the anode 110 is a reflective electrode, the anode 110 may be an ito layer, an ag layer, and an ito layer stacked in this order.
The pixel defining layer is disposed on the anode 110 and the sixth insulating layer 109, an opening is disposed on the pixel defining layer, and the opening is disposed corresponding to the anode 110, and the organic light emitting layer 111 is disposed in the opening and located on the anode 110.
Compared with the prior art that the metal oxide active layer and the electrode plate of the capacitor are located on different layers, the part of the fourth patterning metal layer needs to be bridged with the metal oxide active layer and the electrode plate of the capacitor through the through hole to cause the increase of metal wiring and further cause the reduction of aperture opening ratio.
In addition, compared to the capacitor C which is composed of the third gate 1131 of the first polysilicon transistor M1, the first electrode plate C1, the first insulating layer 104 between the third gate 1131 and the first electrode plate C1, and the third insulating layer 106, the distance between the third gate 1131 and the first electrode plate C1 is larger, and the capacitance value is smaller; the capacitor C comprises the first electrode plate C1, the second electrode plate C2 and the second insulating layer 105, so that the capacitance value of the capacitor C is large, and the response speed is high. Compared with the arrangement of the first gate 1141 and the fifth gate 1142 on the same layer as the third gate 1131, the distance between the first gate 1141 and the first metal oxide active layer 1151 and the distance between the fifth gate 1142 and the second metal oxide active layer 1152 are both larger, and the first gate 1141, the fifth gate 1142 and the third gate 1131 are arranged on different layers, so that the distance between the first gate 1141 and the first metal oxide active layer 1151 and the distance between the fifth gate 1142 and the second metal oxide active layer 1152 are reduced.
The pad region 100b is provided with a first groove 100c and a second groove 100d, the first groove 100c sequentially penetrates through the fourth insulating layer 107, the inorganic stack 103 and the buffer layer 102, and the second groove 100d sequentially penetrates through the fifth insulating layer 108, the second insulating layer 105, the first insulating layer 104 and the third insulating layer 106. The first groove 100c is communicated with the second groove 100d, and the first groove 100c and the second groove 100d are filled with organic layers, so as to prevent the portion of the display panel corresponding to the pad area 100b from being bent or cracks from being generated in the bending process.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (9)
1. A display panel, comprising:
a substrate;
a first metal oxide transistor disposed on the substrate, the first metal oxide transistor including a first metal oxide active layer;
the capacitor is arranged on the substrate and comprises a first electrode plate and a second electrode plate, the first electrode plate and the first metal oxide active layer are arranged on the same layer, and the second electrode plate is arranged corresponding to the first electrode plate and is positioned above the first electrode plate;
a first transparent conductive member disposed on the same layer as the first metal oxide active layer and connecting the first metal oxide active layer and the first electrode plate;
the first polycrystalline silicon transistor is arranged on the substrate, the capacitor is arranged corresponding to the first polycrystalline silicon transistor, and the first electrode plate is arranged above the first polycrystalline silicon transistor;
a first insulating layer disposed between the first polysilicon transistor and the first electrode plate, the first metal oxide active layer, the first electrode plate, and the first transparent conductive member being disposed on the first insulating layer; and
the second insulating layer is arranged between the second electrode plate and the first electrode plate, the second electrode plate is arranged on the second insulating layer, and the thickness of the second insulating layer is smaller than that of the first insulating layer.
2. The display panel according to claim 1, wherein the first insulating layer has a thickness of 4500 angstroms to 6000 angstroms, and wherein the second insulating layer has a thickness of 1000 angstroms to 2500 angstroms.
3. The display panel according to claim 1, wherein the first metal oxide transistor further comprises a first gate electrode and a second gate electrode, the first metal oxide active layer is disposed above and corresponding to the first gate electrode, and the second gate electrode is disposed above and corresponding to the first metal oxide active layer;
the first polycrystalline silicon transistor comprises a first polycrystalline silicon active layer and a third grid electrode, and the third grid electrode is arranged above the first polycrystalline silicon active layer;
the display panel further includes:
a third insulating layer disposed between the third gate and the first insulating layer, the first gate being disposed on the third insulating layer; and
and the fourth insulating layer is arranged between the first polycrystalline silicon active layer and the third grid electrode.
4. The display panel according to claim 3, wherein the display panel further comprises:
the fifth insulating layer is arranged on the second electrode plate; and
and the bridging lead is arranged on the fifth insulating layer, one end of the bridging lead is electrically connected with the first polycrystalline silicon active layer through a first via hole penetrating through the fifth insulating layer, the second insulating layer, the first insulating layer, the third insulating layer and the fourth insulating layer, and the other end of the bridging lead is electrically connected with the first metal oxide active layer through a second via hole penetrating through the fifth insulating layer and the second insulating layer.
5. The display panel according to claim 4, characterized in that the display panel further comprises:
the second polycrystalline silicon transistor comprises a second polycrystalline silicon active layer and a fourth grid electrode, the second polycrystalline silicon active layer and the first polycrystalline silicon active layer are arranged on the same layer, and the fourth grid electrode and the third grid electrode are arranged on the same layer;
an anode lead disposed on the fifth insulating layer;
a sixth insulating layer disposed on the anode lead and the bridging lead; and
an anode disposed on the sixth insulating layer;
the anode lead is electrically connected with the second polysilicon active layer through a third via hole penetrating through the fifth insulating layer, the second insulating layer, the first insulating layer, the third insulating layer and the fourth insulating layer, and the anode is electrically connected with the anode lead through a fourth via hole penetrating through the sixth insulating layer.
6. The display panel according to claim 1, wherein the first insulating layer is made of a material selected from at least one of silicon nitride and silicon oxide, and wherein the second insulating layer is made of a material selected from at least one of silicon nitride and silicon oxide.
7. The display panel according to claim 1, characterized in that the display panel further comprises:
a second metal oxide transistor comprising a second metal oxide active layer disposed in a same layer as the first metal oxide active layer; and
and the second transparent conductive piece and the second metal oxide active layer are arranged on the same layer and are connected with the second metal oxide active layer and the first electrode plate.
8. The display panel of claim 7, wherein the first transparent conductive member, the second transparent conductive member and the first electrode plate are made of materials including indium gallium zinc oxide.
9. The display panel according to claim 7, wherein a preparation material of the first metal oxide active layer and the second metal oxide active layer comprises indium gallium zinc oxide.
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| CN108376672A (en) * | 2018-03-15 | 2018-08-07 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof and display device |
| CN108493198A (en) * | 2018-04-11 | 2018-09-04 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, organic LED display device |
| CN208848909U (en) * | 2018-10-17 | 2019-05-10 | 京东方科技集团股份有限公司 | Array substrate and display device including the array substrate |
| CN111785759A (en) * | 2020-07-17 | 2020-10-16 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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